Revert "DSPJit: Sign-extend acS.h to 32 bits"
This reverts commit dc2eab1778
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parent
bc10412d24
commit
1abaff758a
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@ -704,6 +704,23 @@ OpArg DSPJitRegCache::GetReg(int reg, bool load)
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const OpArg oparg = m_regs[real_reg].loc;
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m_regs[real_reg].used = true;
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// do some register specific fixup
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switch (reg)
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{
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case DSP_REG_ACC0_64:
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case DSP_REG_ACC1_64:
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if (load)
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{
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// need to do this because interpreter only does 48 bits
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// (and PutReg does the same)
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m_emitter.SHL(64, oparg, Imm8(64 - 40)); // sign extend
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m_emitter.SAR(64, oparg, Imm8(64 - 40));
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}
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break;
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default:
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break;
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}
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return oparg;
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}
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@ -721,13 +738,15 @@ void DSPJitRegCache::PutReg(int reg, bool dirty)
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case DSP_REG_ACH1:
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if (dirty)
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{
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// no need to extend to full 64bit here until interpreter
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// uses that
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if (oparg.IsSimpleReg())
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{
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// register is already shifted correctly
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// (if at all)
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// sign extend from the bottom 8 bits.
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m_emitter.MOVSX(32, 8, oparg.GetSimpleReg(), oparg);
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m_emitter.MOVSX(16, 8, oparg.GetSimpleReg(), oparg);
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}
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else if (oparg.IsImm())
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{
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@ -740,8 +759,8 @@ void DSPJitRegCache::PutReg(int reg, bool dirty)
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// of real_reg, since it has the right loc
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X64Reg tmp = GetFreeXReg();
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// Sign extend from the bottom 8 bits.
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m_emitter.MOVSX(32, 8, tmp, m_regs[reg].loc);
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m_emitter.MOV(32, m_regs[reg].loc, R(tmp));
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m_emitter.MOVSX(16, 8, tmp, m_regs[reg].loc);
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m_emitter.MOV(16, m_regs[reg].loc, R(tmp));
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PutXReg(tmp);
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}
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}
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