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make FPSCR.RN an enum

This commit is contained in:
Shawn Hoffman 2021-07-17 18:55:06 -07:00
parent d7a5558dc5
commit 197075293d
5 changed files with 11 additions and 21 deletions
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4
Source/Core/Common/ArmFPURoundMode.cpp
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@ -35,12 +35,12 @@ namespace FPURoundMode
static const u64 default_fpcr = GetFPCR(); static const u64 default_fpcr = GetFPCR();
static u64 saved_fpcr = default_fpcr; static u64 saved_fpcr = default_fpcr;
void SetRoundMode(int mode) void SetRoundMode(RoundMode mode)
{ {
// We don't need to do anything here since SetSIMDMode is always called after calling this // We don't need to do anything here since SetSIMDMode is always called after calling this
} }
void SetSIMDMode(int rounding_mode, bool non_ieee_mode) void SetSIMDMode(RoundMode rounding_mode, bool non_ieee_mode)
{ {
// When AH is disabled, FZ controls flush-to-zero for both inputs and outputs. When AH is enabled, // When AH is disabled, FZ controls flush-to-zero for both inputs and outputs. When AH is enabled,
// FZ controls flush-to-zero for outputs, and FIZ controls flush-to-zero for inputs. // FZ controls flush-to-zero for outputs, and FIZ controls flush-to-zero for inputs.

17
Source/Core/Common/FPURoundMode.h
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@ -7,28 +7,17 @@
namespace FPURoundMode namespace FPURoundMode
{ {
// TODO: MSVC currently produces broken code: enum RoundMode : u32
// https://connect.microsoft.com/VisualStudio/feedback/details/828892/vc-2013-miscompilation-with-enums-and-bit-fields
// Once that is fixed, change types in SetRoundMode(), SetSIMDMode(), and in UReg_FPSCR to
// 'RoundMode'.
enum RoundMode
{ {
ROUND_NEAR = 0, ROUND_NEAR = 0,
ROUND_CHOP = 1, ROUND_CHOP = 1,
ROUND_UP = 2, ROUND_UP = 2,
ROUND_DOWN = 3 ROUND_DOWN = 3
}; };
enum PrecisionMode
{
PREC_24 = 0,
PREC_53 = 1,
PREC_64 = 2
};
void SetRoundMode(int mode); void SetRoundMode(RoundMode mode);
void SetSIMDMode(int rounding_mode, bool non_ieee_mode); void SetSIMDMode(RoundMode rounding_mode, bool non_ieee_mode);
/* /*
* There are two different flavors of float to int conversion: * There are two different flavors of float to int conversion:

4
Source/Core/Common/GenericFPURoundMode.cpp
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@ -7,10 +7,10 @@
// Generic, do nothing // Generic, do nothing
namespace FPURoundMode namespace FPURoundMode
{ {
void SetRoundMode(int mode) void SetRoundMode(RoundMode mode)
{ {
} }
void SetSIMDMode(int rounding_mode, bool non_ieee_mode) void SetSIMDMode(RoundMode rounding_mode, bool non_ieee_mode)
{ {
} }
void SaveSIMDState() void SaveSIMDState()

4
Source/Core/Common/x64FPURoundMode.cpp
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@ -14,14 +14,14 @@ namespace FPURoundMode
static u32 saved_sse_state = _mm_getcsr(); static u32 saved_sse_state = _mm_getcsr();
static const u32 default_sse_state = _mm_getcsr(); static const u32 default_sse_state = _mm_getcsr();
void SetRoundMode(int mode) void SetRoundMode(RoundMode mode)
{ {
// Convert PowerPC to native rounding mode. // Convert PowerPC to native rounding mode.
static const int rounding_mode_lut[] = {FE_TONEAREST, FE_TOWARDZERO, FE_UPWARD, FE_DOWNWARD}; static const int rounding_mode_lut[] = {FE_TONEAREST, FE_TOWARDZERO, FE_UPWARD, FE_DOWNWARD};
fesetround(rounding_mode_lut[mode]); fesetround(rounding_mode_lut[mode]);
} }
void SetSIMDMode(int rounding_mode, bool non_ieee_mode) void SetSIMDMode(RoundMode rounding_mode, bool non_ieee_mode)
{ {
// OR-mask for disabling FPU exceptions (bits 7-12 in the MXCSR register) // OR-mask for disabling FPU exceptions (bits 7-12 in the MXCSR register)
const u32 EXCEPTION_MASK = 0x1F80; const u32 EXCEPTION_MASK = 0x1F80;

3
Source/Core/Core/PowerPC/Gekko.h
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@ -7,6 +7,7 @@
#include "Common/BitField.h" #include "Common/BitField.h"
#include "Common/CommonTypes.h" #include "Common/CommonTypes.h"
#include "Common/FPURoundMode.h"
// --- Gekko Instruction --- // --- Gekko Instruction ---
@ -435,7 +436,7 @@ union UReg_FPSCR
struct struct
{ {
// Rounding mode (towards: nearest, zero, +inf, -inf) // Rounding mode (towards: nearest, zero, +inf, -inf)
u32 RN : 2; FPURoundMode::RoundMode RN : 2;
// Non-IEEE mode enable (aka flush-to-zero) // Non-IEEE mode enable (aka flush-to-zero)
u32 NI : 1; u32 NI : 1;
// Inexact exception enable // Inexact exception enable