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Fixes some overzealous optimizations from ARMv7 BindToRegister. 

We can't do it in rlw and friends.
subfx had an inccorect check.
Minor whitespace and reordering.
This commit is contained in:
Ryan Houdek 2014-10-25 20:36:29 -05:00
parent 484fc392d6
commit 17f352e2aa
1 changed files with 5 additions and 8 deletions
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9
Source/Core/Core/PowerPC/JitArm32/JitArm_Integer.cpp
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@ -570,10 +570,10 @@ void JitArm::arith(UGeckoInstruction inst)
ANDS(RA, RS, RB);
break;
case 40: // subfx
gpr.BindToRegister(d, d == s || d == b);
gpr.BindToRegister(d, d == b || d == a);
RD = gpr.R(d);
RA = gpr.R(a);
RB = gpr.R(b);
RA = gpr.R(a);
SUBS(RD, RB, RA);
break;
case 60:
@ -841,8 +841,8 @@ void JitArm::negx(UGeckoInstruction inst)
JITDISABLE(bJITIntegerOff);
gpr.BindToRegister(inst.RD, inst.RD == inst.RA);
ARMReg RA = gpr.R(inst.RA);
ARMReg RD = gpr.R(inst.RD);
ARMReg RA = gpr.R(inst.RA);
RSB(RD, RA, 0);
if (inst.Rc)
@ -860,7 +860,6 @@ void JitArm::rlwimix(UGeckoInstruction inst)
JITDISABLE(bJITIntegerOff);
u32 mask = Helper_Mask(inst.MB,inst.ME);
gpr.BindToRegister(inst.RA, inst.RA == inst.RS);
ARMReg RA = gpr.R(inst.RA);
ARMReg RS = gpr.R(inst.RS);
ARMReg rA = gpr.GetReg();
@ -883,7 +882,6 @@ void JitArm::rlwinmx(UGeckoInstruction inst)
JITDISABLE(bJITIntegerOff);
u32 mask = Helper_Mask(inst.MB,inst.ME);
gpr.BindToRegister(inst.RA, inst.RA == inst.RS);
ARMReg RA = gpr.R(inst.RA);
ARMReg RS = gpr.R(inst.RS);
ARMReg rA = gpr.GetReg();
@ -904,7 +902,6 @@ void JitArm::rlwnmx(UGeckoInstruction inst)
JITDISABLE(bJITIntegerOff);
u32 mask = Helper_Mask(inst.MB,inst.ME);
gpr.BindToRegister(inst.RA, inst.RA == inst.RS || inst.RA == inst.RB);
ARMReg RA = gpr.R(inst.RA);
ARMReg RS = gpr.R(inst.RS);
ARMReg RB = gpr.R(inst.RB);