some comments and cleanup
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2891 8ced0084-cf51-0410-be5f-012b33b47a6e
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@ -423,6 +423,9 @@ void tst(const UDSPInstruction& opc)
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tsta((opc.hex >> 11) & 0x1);
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tsta((opc.hex >> 11) & 0x1);
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}
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}
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// ADDAXL $acD, $axS.l
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// 0111 00sd xxxx xxxx
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// Adds secondary accumulator $axS.l to accumulator register $acD.
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void addaxl(const UDSPInstruction& opc)
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void addaxl(const UDSPInstruction& opc)
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{
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{
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u8 sreg = (opc.hex >> 9) & 0x1;
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u8 sreg = (opc.hex >> 9) & 0x1;
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@ -438,6 +441,9 @@ void addaxl(const UDSPInstruction& opc)
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Update_SR_Register64(acc);
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Update_SR_Register64(acc);
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}
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}
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// ADDARN $arD, $ixS
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// 0000 0000 0001 ssdd
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// Adds indexing register $ixS to an addressing register $arD.
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void addarn(const UDSPInstruction& opc)
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void addarn(const UDSPInstruction& opc)
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{
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{
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u8 dreg = opc.hex & 0x3;
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u8 dreg = opc.hex & 0x3;
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@ -504,6 +510,10 @@ void xorr(const UDSPInstruction& opc)
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tsta(dreg);
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tsta(dreg);
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}
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}
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// ANDR $acD.m, $axS.h
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// 0011 01sd xxxx xxxx
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// Logic AND middle part of accumulator $acD.m with hight part of
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// secondary accumulator $axS.h.
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void andr(const UDSPInstruction& opc)
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void andr(const UDSPInstruction& opc)
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{
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{
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u8 sreg = (opc.hex >> 9) & 0x1;
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u8 sreg = (opc.hex >> 9) & 0x1;
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@ -524,6 +534,10 @@ void orr(const UDSPInstruction& opc)
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tsta(dreg);
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tsta(dreg);
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}
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}
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// ANDC $acD.m, $ac(1-D).m
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// 0011 110d xxxx xxxx
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// Logic AND middle part of accumulator $acD.m with middle part of
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// accumulator $ax(1-D).m.s
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void andc(const UDSPInstruction& opc)
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void andc(const UDSPInstruction& opc)
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{
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{
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u8 D = (opc.hex >> 8) & 0x1;
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u8 D = (opc.hex >> 8) & 0x1;
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@ -555,6 +569,11 @@ void nx(const UDSPInstruction& opc)
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// FIXME inside
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// FIXME inside
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// Hermes switched andf and andcf, so check to make sure they are still correct
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// Hermes switched andf and andcf, so check to make sure they are still correct
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// ANDCF $acD.m, #I
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// 0000 001r 1100 0000
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// iiii iiii iiii iiii
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// Set logic zero (LZ) flag in status register $sr if result of logic AND of
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// accumulator mid part $acD.m with immediate value I is equal zero.
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void andfc(const UDSPInstruction& opc)
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void andfc(const UDSPInstruction& opc)
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{
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{
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if (opc.hex & 0xf)
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if (opc.hex & 0xf)
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@ -579,6 +598,13 @@ void andfc(const UDSPInstruction& opc)
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// FIXME inside
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// FIXME inside
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// Hermes switched andf and andcf, so check to make sure they are still correct
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// Hermes switched andf and andcf, so check to make sure they are still correct
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// ANDF $acD.m, #I
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// 0000 001r 1010 0000
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// iiii iiii iiii iiii
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// Set logic zero (LZ) flag in status register $sr if result of logical AND
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// operation of accumulator mid part $acD.m with immediate value I is equal
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// immediate value I.
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void andf(const UDSPInstruction& opc)
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void andf(const UDSPInstruction& opc)
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{
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{
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u8 reg;
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u8 reg;
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@ -634,6 +660,10 @@ void xori(const UDSPInstruction& opc)
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}
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}
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//FIXME inside
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//FIXME inside
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// ANDI $acD.m, #I
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// 0000 001r 0100 0000
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// iiii iiii iiii iiii
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// Logic AND of accumulator mid part $acD.m with immediate value I.
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void andi(const UDSPInstruction& opc)
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void andi(const UDSPInstruction& opc)
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{
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{
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if (opc.hex & 0xf)
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if (opc.hex & 0xf)
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@ -671,6 +701,10 @@ void ori(const UDSPInstruction& opc)
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//-------------------------------------------------------------
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//-------------------------------------------------------------
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// ADD $acD, $ac(1-D)
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// 0100 110d xxxx xxxx
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// Adds accumulator $ac(1-D) to accumulator register $acD.
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void add(const UDSPInstruction& opc)
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void add(const UDSPInstruction& opc)
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{
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{
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u8 areg = (opc.hex >> 8) & 0x1;
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u8 areg = (opc.hex >> 8) & 0x1;
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@ -686,11 +720,14 @@ void add(const UDSPInstruction& opc)
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//-------------------------------------------------------------
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//-------------------------------------------------------------
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// ADDP $acD
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// 0100 111d xxxx xxxx
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// Adds product register to accumulator register.
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void addp(const UDSPInstruction& opc)
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void addp(const UDSPInstruction& opc)
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{
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{
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u8 dreg = (opc.hex >> 8) & 0x1;
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u8 dreg = (opc.hex >> 8) & 0x1;
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s64 acc = dsp_get_long_acc(dreg);
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s64 acc = dsp_get_long_acc(dreg);
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acc = acc + dsp_get_long_prod();
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acc += dsp_get_long_prod();
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dsp_set_long_acc(dreg, acc);
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dsp_set_long_acc(dreg, acc);
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Update_SR_Register64(acc);
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Update_SR_Register64(acc);
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@ -709,6 +746,10 @@ void cmpis(const UDSPInstruction& opc)
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Update_SR_Register64(res);
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Update_SR_Register64(res);
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}
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}
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// ADDPAXZ $acD, $axS
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// 1111 10sd xxxx xxxx
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// Adds secondary accumulator $axS to product register and stores result
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// in accumulator register. Low 16-bits of $acD ($acD.l) are set to 0.
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void addpaxz(const UDSPInstruction& opc)
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void addpaxz(const UDSPInstruction& opc)
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{
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{
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u8 dreg = (opc.hex >> 8) & 0x1;
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u8 dreg = (opc.hex >> 8) & 0x1;
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@ -808,6 +849,9 @@ void mov(const UDSPInstruction& opc)
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ERROR_LOG(DSPHLE, "dsp_opc.hex_mov\n");
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ERROR_LOG(DSPHLE, "dsp_opc.hex_mov\n");
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}
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}
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// ADDAX $acD, $axS
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// 0100 10sd xxxx xxxx
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// Adds secondary accumulator $axS to accumulator register $acD.
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void addax(const UDSPInstruction& opc)
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void addax(const UDSPInstruction& opc)
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{
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{
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u8 areg = (opc.hex >> 8) & 0x1;
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u8 areg = (opc.hex >> 8) & 0x1;
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@ -821,6 +865,9 @@ void addax(const UDSPInstruction& opc)
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Update_SR_Register64(acc);
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Update_SR_Register64(acc);
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}
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}
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// ADDR $acD, $(0x18+S)
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// 0100 0ssd xxxx xxxx
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// Adds register $(0x18+S) to accumulator $acD register.
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void addr(const UDSPInstruction& opc)
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void addr(const UDSPInstruction& opc)
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{
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{
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u8 areg = (opc.hex >> 8) & 0x1;
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u8 areg = (opc.hex >> 8) & 0x1;
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@ -862,6 +909,9 @@ void subax(const UDSPInstruction& opc)
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Update_SR_Register64(Acc);
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Update_SR_Register64(Acc);
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}
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}
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// ADDIS $acD, #I
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// 0000 010d iiii iiii
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// Adds short immediate (8-bit sign extended) to mid accumulator $acD.hm.
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void addis(const UDSPInstruction& opc)
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void addis(const UDSPInstruction& opc)
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{
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{
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u8 areg = (opc.hex >> 8) & 0x1;
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u8 areg = (opc.hex >> 8) & 0x1;
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@ -875,6 +925,10 @@ void addis(const UDSPInstruction& opc)
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Update_SR_Register64(acc);
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Update_SR_Register64(acc);
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}
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}
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// ADDI $amR, #I
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// 0000 001r 0000 0000
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// iiii iiii iiii iiii
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// Adds immediate (16-bit sign extended) to mid accumulator $acD.hm.
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void addi(const UDSPInstruction& opc)
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void addi(const UDSPInstruction& opc)
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{
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{
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u8 areg = (opc.hex >> 8) & 0x1;
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u8 areg = (opc.hex >> 8) & 0x1;
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@ -51,7 +51,7 @@ u16 dsp_dmem_read(u16 addr)
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return dsp_swap16(g_dsp.dram[addr & DSP_DRAM_MASK]);
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return dsp_swap16(g_dsp.dram[addr & DSP_DRAM_MASK]);
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case 0x8: // 8xxx DROM
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case 0x8: // 8xxx DROM
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ERROR_LOG(DSPHLE, "someone reads from ROM\n");
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ERROR_LOG(DSPHLE, "someone reads from ROM");
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return dsp_swap16(g_dsp.drom[addr & DSP_DROM_MASK]);
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return dsp_swap16(g_dsp.drom[addr & DSP_DROM_MASK]);
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case 0x1: // 1xxx COEF
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case 0x1: // 1xxx COEF
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@ -61,7 +61,7 @@ u16 dsp_dmem_read(u16 addr)
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return gdsp_ifx_read(addr);
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return gdsp_ifx_read(addr);
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default: // error
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default: // error
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ERROR_LOG(DSPHLE, "%04x DSP ERROR: Read from UNKNOWN (%04x) memory\n", g_dsp.pc, addr);
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ERROR_LOG(DSPHLE, "%04x DSP ERROR: Read from UNKNOWN (%04x) memory", g_dsp.pc, addr);
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return 0;
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return 0;
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}
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}
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}
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}
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@ -72,7 +72,7 @@ void dsp_dmem_write(u16 addr, u16 val)
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switch (addr >> 12)
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switch (addr >> 12)
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{
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{
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case 0x8: // 8xxx DROM
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case 0x8: // 8xxx DROM
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ERROR_LOG(DSPHLE, "someone writes to ROM\n");
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ERROR_LOG(DSPHLE, "someone writes to ROM");
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/* val = dsp_swap16(val);
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/* val = dsp_swap16(val);
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g_dsp.drom[addr & DSP_DROM_MASK] = val;*/
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g_dsp.drom[addr & DSP_DROM_MASK] = val;*/
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break;
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break;
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@ -86,7 +86,7 @@ void dsp_dmem_write(u16 addr, u16 val)
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break;
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break;
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default: // error
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default: // error
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ERROR_LOG(DSPHLE, "%04x DSP ERROR: Write to UNKNOWN (%04x) memory\n", g_dsp.pc, addr);
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ERROR_LOG(DSPHLE, "%04x DSP ERROR: Write to UNKNOWN (%04x) memory", g_dsp.pc, addr);
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break;
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break;
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}
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}
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}
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}
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