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FifoPlayer: Use more enums.

This commit is contained in:
degasus 2016-01-26 08:37:30 +01:00
parent 9199539798
commit 159d83c5a9
3 changed files with 37 additions and 37 deletions
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46
Source/Core/Core/FifoPlayer/FifoPlayer.cpp
View File

@ -15,10 +15,12 @@
#include "Core/FifoPlayer/FifoPlayer.h" #include "Core/FifoPlayer/FifoPlayer.h"
#include "Core/HW/GPFifo.h" #include "Core/HW/GPFifo.h"
#include "Core/HW/Memmap.h" #include "Core/HW/Memmap.h"
#include "Core/HW/ProcessorInterface.h"
#include "Core/HW/SystemTimers.h" #include "Core/HW/SystemTimers.h"
#include "Core/HW/VideoInterface.h" #include "Core/HW/VideoInterface.h"
#include "Core/PowerPC/PowerPC.h" #include "Core/PowerPC/PowerPC.h"
#include "VideoCommon/BPMemory.h" #include "VideoCommon/BPMemory.h"
#include "VideoCommon/CommandProcessor.h"
bool IsPlayingBackFifologWithBrokenEFBCopies = false; bool IsPlayingBackFifologWithBrokenEFBCopies = false;
@ -317,42 +319,42 @@ void FifoPlayer::WriteFifo(u8* data, u32 start, u32 end)
void FifoPlayer::SetupFifo() void FifoPlayer::SetupFifo()
{ {
WriteCP(0x02, 0); // disable read, BP, interrupts WriteCP(CommandProcessor::CTRL_REGISTER, 0); // disable read, BP, interrupts
WriteCP(0x04, 7); // clear overflow, underflow, metrics WriteCP(CommandProcessor::CLEAR_REGISTER, 7); // clear overflow, underflow, metrics
const FifoFrameInfo& frame = m_File->GetFrame(m_CurrentFrame); const FifoFrameInfo& frame = m_File->GetFrame(m_CurrentFrame);
// Set fifo bounds // Set fifo bounds
WriteCP(0x20, frame.fifoStart); WriteCP(CommandProcessor::FIFO_BASE_LO, frame.fifoStart);
WriteCP(0x22, frame.fifoStart >> 16); WriteCP(CommandProcessor::FIFO_BASE_HI, frame.fifoStart >> 16);
WriteCP(0x24, frame.fifoEnd); WriteCP(CommandProcessor::FIFO_END_LO, frame.fifoEnd);
WriteCP(0x26, frame.fifoEnd >> 16); WriteCP(CommandProcessor::FIFO_END_HI, frame.fifoEnd >> 16);
// Set watermarks // Set watermarks
u32 fifoSize = frame.fifoEnd - frame.fifoStart; u32 hi_watermark = frame.fifoEnd - frame.fifoStart;
WriteCP(0x28, fifoSize); WriteCP(CommandProcessor::FIFO_HI_WATERMARK_LO, hi_watermark);
WriteCP(0x2a, fifoSize >> 16); WriteCP(CommandProcessor::FIFO_HI_WATERMARK_HI, hi_watermark >> 16);
WriteCP(0x2c, 0); WriteCP(CommandProcessor::FIFO_LO_WATERMARK_LO, 0);
WriteCP(0x2e, 0); WriteCP(CommandProcessor::FIFO_LO_WATERMARK_HI, 0);
// Set R/W pointers to fifo start // Set R/W pointers to fifo start
WriteCP(0x30, 0); WriteCP(CommandProcessor::FIFO_RW_DISTANCE_LO, 0);
WriteCP(0x32, 0); WriteCP(CommandProcessor::FIFO_RW_DISTANCE_HI, 0);
WriteCP(0x34, frame.fifoStart); WriteCP(CommandProcessor::FIFO_WRITE_POINTER_LO, frame.fifoStart);
WriteCP(0x36, frame.fifoStart >> 16); WriteCP(CommandProcessor::FIFO_WRITE_POINTER_HI, frame.fifoStart >> 16);
WriteCP(0x38, frame.fifoStart); WriteCP(CommandProcessor::FIFO_READ_POINTER_LO, frame.fifoStart);
WriteCP(0x3a, frame.fifoStart >> 16); WriteCP(CommandProcessor::FIFO_READ_POINTER_HI, frame.fifoStart >> 16);
// Set fifo bounds // Set fifo bounds
WritePI(12, frame.fifoStart); WritePI(ProcessorInterface::PI_FIFO_BASE, frame.fifoStart);
WritePI(16, frame.fifoEnd); WritePI(ProcessorInterface::PI_FIFO_END, frame.fifoEnd);
// Set write pointer // Set write pointer
WritePI(20, frame.fifoStart); WritePI(ProcessorInterface::PI_FIFO_WPTR, frame.fifoStart);
FlushWGP(); FlushWGP();
WritePI(20, frame.fifoStart); WritePI(ProcessorInterface::PI_FIFO_WPTR, frame.fifoStart);
WriteCP(0x02, 17); // enable read & GP link WriteCP(CommandProcessor::CTRL_REGISTER, 17); // enable read & GP link
} }
void FifoPlayer::LoadMemory() void FifoPlayer::LoadMemory()

15
Source/Core/Core/HW/ProcessorInterface.cpp
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@ -15,21 +15,6 @@
namespace ProcessorInterface namespace ProcessorInterface
{ {
// Internal hardware addresses
enum
{
PI_INTERRUPT_CAUSE = 0x00,
PI_INTERRUPT_MASK = 0x04,
PI_FIFO_BASE = 0x0C,
PI_FIFO_END = 0x10,
PI_FIFO_WPTR = 0x14,
PI_FIFO_RESET = 0x18, // ??? - GXAbortFrame writes to it
PI_RESET_CODE = 0x24,
PI_FLIPPER_REV = 0x2C,
PI_FLIPPER_UNK = 0x30 // BS1 writes 0x0245248A to it - prolly some bootstrap thing
};
// STATE_TO_SAVE // STATE_TO_SAVE
u32 m_InterruptCause; u32 m_InterruptCause;
u32 m_InterruptMask; u32 m_InterruptMask;

13
Source/Core/Core/HW/ProcessorInterface.h
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@ -34,6 +34,19 @@ enum InterruptCause
INT_CAUSE_RST_BUTTON = 0x10000 // ResetButtonState (1 = unpressed, 0 = pressed) it's a state, not maskable INT_CAUSE_RST_BUTTON = 0x10000 // ResetButtonState (1 = unpressed, 0 = pressed) it's a state, not maskable
}; };
// Internal hardware addresses
enum
{
PI_INTERRUPT_CAUSE = 0x00,
PI_INTERRUPT_MASK = 0x04,
PI_FIFO_BASE = 0x0C,
PI_FIFO_END = 0x10,
PI_FIFO_WPTR = 0x14,
PI_FIFO_RESET = 0x18, // ??? - GXAbortFrame writes to it
PI_RESET_CODE = 0x24,
PI_FLIPPER_REV = 0x2C,
PI_FLIPPER_UNK = 0x30 // BS1 writes 0x0245248A to it - prolly some bootstrap thing
};
extern u32 m_InterruptCause; extern u32 m_InterruptCause;
extern u32 m_InterruptMask; extern u32 m_InterruptMask;