Jit_Paired: ps_sum
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@ -38,43 +38,46 @@ void Jit64::ps_sum(UGeckoInstruction inst)
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int a = inst.FA;
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int a = inst.FA;
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int b = inst.FB;
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int b = inst.FB;
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int c = inst.FC;
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int c = inst.FC;
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fpr.Lock(a, b, c, d);
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OpArg op_a = fpr.R(a);
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RCOpArg Ra = fpr.Use(a, RCMode::Read);
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fpr.BindToRegister(d, d == b || d == c);
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RCOpArg Rb = fpr.Use(b, RCMode::Read);
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RCOpArg Rc = fpr.Use(c, RCMode::Read);
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RCX64Reg Rd = fpr.Bind(d, RCMode::Write);
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RegCache::Realize(Ra, Rb, Rc, Rd);
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X64Reg tmp = XMM1;
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X64Reg tmp = XMM1;
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MOVDDUP(tmp, op_a); // {a.ps0, a.ps0}
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MOVDDUP(tmp, Ra); // {a.ps0, a.ps0}
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ADDPD(tmp, fpr.R(b)); // {a.ps0 + b.ps0, a.ps0 + b.ps1}
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ADDPD(tmp, Rb); // {a.ps0 + b.ps0, a.ps0 + b.ps1}
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switch (inst.SUBOP5)
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switch (inst.SUBOP5)
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{
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{
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case 10: // ps_sum0: {a.ps0 + b.ps1, c.ps1}
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case 10: // ps_sum0: {a.ps0 + b.ps1, c.ps1}
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UNPCKHPD(tmp, fpr.R(c));
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UNPCKHPD(tmp, Rc);
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break;
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break;
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case 11: // ps_sum1: {c.ps0, a.ps0 + b.ps1}
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case 11: // ps_sum1: {c.ps0, a.ps0 + b.ps1}
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if (fpr.R(c).IsSimpleReg())
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if (Rc.IsSimpleReg())
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{
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{
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if (cpu_info.bSSE4_1)
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if (cpu_info.bSSE4_1)
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{
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{
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BLENDPD(tmp, fpr.R(c), 1);
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BLENDPD(tmp, Rc, 1);
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}
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}
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else
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else
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{
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{
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MOVAPD(XMM0, fpr.R(c));
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MOVAPD(XMM0, Rc);
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SHUFPD(XMM0, R(tmp), 2);
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SHUFPD(XMM0, R(tmp), 2);
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tmp = XMM0;
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tmp = XMM0;
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}
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}
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}
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}
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else
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else
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{
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{
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MOVLPD(tmp, fpr.R(c));
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MOVLPD(tmp, Rc);
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}
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}
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break;
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break;
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default:
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default:
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PanicAlert("ps_sum WTF!!!");
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PanicAlert("ps_sum WTF!!!");
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}
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}
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HandleNaNs(inst, fpr.RX(d), tmp, tmp == XMM1 ? XMM0 : XMM1);
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HandleNaNs(inst, Rd, tmp, tmp == XMM1 ? XMM0 : XMM1);
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ForceSinglePrecision(fpr.RX(d), fpr.R(d));
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ForceSinglePrecision(Rd, Rd);
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SetFPRFIfNeeded(fpr.RX(d));
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SetFPRFIfNeeded(Rd);
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fpr.UnlockAll();
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}
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}
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void Jit64::ps_muls(UGeckoInstruction inst)
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void Jit64::ps_muls(UGeckoInstruction inst)
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