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docs/DSP: fix opcode operations 

some did not reflect the correct PC increments, other had their registers
mixed up.
LSNM was misspelled as LSMN.
This commit is contained in:
BhaaL 2018-04-13 20:00:22 +02:00
parent facd1dca12
commit 1419e7e5b2
1 changed files with 21 additions and 21 deletions
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42
docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex
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@ -990,7 +990,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
\begin{DSPOpcodeOperation} \begin{DSPOpcodeOperation}
$acD.hm += #I $acD.hm += #I
FLAGS($acD) FLAGS($acD)
$pc++ $pc += 2
\end{DSPOpcodeOperation} \end{DSPOpcodeOperation}
\end{DSPOpcode} \end{DSPOpcode}
@ -1118,7 +1118,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
ELSE ELSE
$sr.LZ = 0 $sr.LZ = 0
ENDIF ENDIF
$pc++ $pc += 2
\end{DSPOpcodeOperation} \end{DSPOpcodeOperation}
\end{DSPOpcode} \end{DSPOpcode}
@ -1144,7 +1144,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
ELSE ELSE
$sr.LZ = 0 $sr.LZ = 0
ENDIF ENDIF
$pc++ $pc += 2
\end{DSPOpcodeOperation} \end{DSPOpcodeOperation}
\end{DSPOpcode} \end{DSPOpcode}
@ -1165,7 +1165,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
\begin{DSPOpcodeOperation} \begin{DSPOpcodeOperation}
$acD.m &= #I $acD.m &= #I
FLAGS($acD) FLAGS($acD)
$pc++ $pc += 2
\end{DSPOpcodeOperation} \end{DSPOpcodeOperation}
\end{DSPOpcode} \end{DSPOpcode}
@ -1270,7 +1270,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
$st0 = $pc + 2 $st0 = $pc + 2
$st2 = addrA $st2 = addrA
$st3 = $R $st3 = $R
$pc + 2 $pc += 2
// On real hardware, the below does not happen, // On real hardware, the below does not happen,
// this opcode only sets stack registers // this opcode only sets stack registers
@ -1306,7 +1306,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
$st0 = $pc + 2 $st0 = $pc + 2
$st2 = addrA $st2 = addrA
$st3 = I $st3 = I
$pc + 2 $pc += 2
// On real hardware, the below does not happen, // On real hardware, the below does not happen,
// this opcode only sets stack registers // this opcode only sets stack registers
@ -1499,7 +1499,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
\begin{DSPOpcodeOperation} \begin{DSPOpcodeOperation}
res = ($acD.hm - I) | $acD.l res = ($acD.hm - I) | $acD.l
FLAGS(res) FLAGS(res)
$pc++ $pc += 2
\end{DSPOpcodeOperation} \end{DSPOpcodeOperation}
\end{DSPOpcode} \end{DSPOpcode}
@ -2039,7 +2039,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
\begin{DSPOpcodeOperation} \begin{DSPOpcodeOperation}
$(0x18+D) = MEM[M] $(0x18+D) = MEM[M]
$pc += 2 $pc++
\end{DSPOpcodeOperation} \end{DSPOpcodeOperation}
\end{DSPOpcode} \end{DSPOpcode}
@ -2821,7 +2821,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
\begin{DSPOpcodeOperation} \begin{DSPOpcodeOperation}
$acD.m |= #I $acD.m |= #I
FLAGS($acD) FLAGS($acD)
$pc++ $pc += 2
\end{DSPOpcodeOperation} \end{DSPOpcodeOperation}
\end{DSPOpcode} \end{DSPOpcode}
@ -3088,7 +3088,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
\begin{DSPOpcodeOperation} \begin{DSPOpcodeOperation}
MEM[M] = $(0x18+S) MEM[M] = $(0x18+S)
$pc += 2 $pc++
\end{DSPOpcodeOperation} \end{DSPOpcodeOperation}
\end{DSPOpcode} \end{DSPOpcode}
@ -3227,7 +3227,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
\begin{DSPOpcodeOperation} \begin{DSPOpcodeOperation}
$acD.m ^= #I $acD.m ^= #I
FLAGS($acD) FLAGS($acD)
$pc++ $pc += 2
\end{DSPOpcodeOperation} \end{DSPOpcodeOperation}
\end{DSPOpcode} \end{DSPOpcode}
@ -3384,13 +3384,13 @@ allow extending (8 lower bits of opcode not used by opcode). Extended opcodes do
\end{DSPOpcodeOperation} \end{DSPOpcodeOperation}
\end{DSPOpcode} \end{DSPOpcode}
\begin{DSPOpcode}{'LSMN} \begin{DSPOpcode}{'LSNM}
\begin{DSPOpcodeBytefield}{16} \begin{DSPOpcodeBytefield}{16}
\monobitbox{4}{xxxx} & \monobitbox{4}{xxxx} & \monobitbox{4}{10dd} & \monobitbox{4}{110s} \monobitbox{4}{xxxx} & \monobitbox{4}{xxxx} & \monobitbox{4}{10dd} & \monobitbox{4}{110s}
\end{DSPOpcodeBytefield} \end{DSPOpcodeBytefield}
\begin{DSPOpcodeFormat} \begin{DSPOpcodeFormat}
'LSMN $(0x18+D), $acS.m 'LSNM $(0x18+D), $acS.m
\end{DSPOpcodeFormat} \end{DSPOpcodeFormat}
\begin{DSPOpcodeDescription} \begin{DSPOpcodeDescription}
@ -3503,8 +3503,8 @@ allow extending (8 lower bits of opcode not used by opcode). Extended opcodes do
\end{DSPOpcodeDescription} \end{DSPOpcodeDescription}
\begin{DSPOpcodeOperation} \begin{DSPOpcodeOperation}
$(0x18+D) = MEM[$ar0] $(0x18+D) = MEM[$ar3]
MEM[$ar3] = $acS.m MEM[$ar0] = $acS.m
$ar0++ $ar0++
$ar3++ $ar3++
\end{DSPOpcodeOperation} \end{DSPOpcodeOperation}
@ -3526,8 +3526,8 @@ allow extending (8 lower bits of opcode not used by opcode). Extended opcodes do
\end{DSPOpcodeDescription} \end{DSPOpcodeDescription}
\begin{DSPOpcodeOperation} \begin{DSPOpcodeOperation}
$(0x18+D) = MEM[$ar0] $(0x18+D) = MEM[$ar3]
MEM[$ar3] = $acS.m MEM[$ar0] = $acS.m
$ar0++ $ar0++
$ar3 += $ix3 $ar3 += $ix3
\end{DSPOpcodeOperation} \end{DSPOpcodeOperation}
@ -3550,8 +3550,8 @@ allow extending (8 lower bits of opcode not used by opcode). Extended opcodes do
\end{DSPOpcodeDescription} \end{DSPOpcodeDescription}
\begin{DSPOpcodeOperation} \begin{DSPOpcodeOperation}
$(0x18+D) = MEM[$ar0] $(0x18+D) = MEM[$ar3]
MEM[$ar3] = $acS.m MEM[$ar0] = $acS.m
$ar0 += $ix0 $ar0 += $ix0
$ar3 += $ix3 $ar3 += $ix3
\end{DSPOpcodeOperation} \end{DSPOpcodeOperation}
@ -3573,8 +3573,8 @@ allow extending (8 lower bits of opcode not used by opcode). Extended opcodes do
\end{DSPOpcodeDescription} \end{DSPOpcodeDescription}
\begin{DSPOpcodeOperation} \begin{DSPOpcodeOperation}
$(0x18+D) = MEM[$ar0] $(0x18+D) = MEM[$ar3]
MEM[$ar3] = $acS.m MEM[$ar0] = $acS.m
$ar0 += $ix0 $ar0 += $ix0
$ar3++ $ar3++
\end{DSPOpcodeOperation} \end{DSPOpcodeOperation}