Merge pull request #12107 from MikeIsAStar/retrieve-page-table-information-from-data-cache
Retrieve page table information from the data cache
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commit
10c5da6f62
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@ -1387,8 +1387,8 @@ void MMU::InvalidateTLBEntry(u32 address)
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}
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// Page Address Translation
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MMU::TranslateAddressResult MMU::TranslatePageAddress(const EffectiveAddress address,
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const XCheckTLBFlag flag, bool* wi)
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template <const XCheckTLBFlag flag>
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MMU::TranslateAddressResult MMU::TranslatePageAddress(const EffectiveAddress address, bool* wi)
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{
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// TLB cache
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// This catches 99%+ of lookups in practice, so the actual page table entry code below doesn't
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@ -1441,11 +1441,11 @@ MMU::TranslateAddressResult MMU::TranslatePageAddress(const EffectiveAddress add
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for (int i = 0; i < 8; i++, pteg_addr += 8)
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{
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const u32 pteg = m_memory.Read_U32(pteg_addr);
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const u32 pteg = ReadFromHardware<flag, u32, true>(pteg_addr);
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if (pte1.Hex == pteg)
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{
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UPTE_Hi pte2(m_memory.Read_U32(pteg_addr + 4));
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UPTE_Hi pte2(ReadFromHardware<flag, u32, true>(pteg_addr + 4));
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// set the access bits
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switch (flag)
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@ -1643,7 +1643,7 @@ MMU::TranslateAddressResult MMU::TranslateAddress(u32 address)
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if (TranslateBatAddress(IsOpcodeFlag(flag) ? m_ibat_table : m_dbat_table, &address, &wi))
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return TranslateAddressResult{TranslateAddressResultEnum::BAT_TRANSLATED, address, wi};
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return TranslatePageAddress(EffectiveAddress{address}, flag, &wi);
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return TranslatePageAddress<flag>(EffectiveAddress{address}, &wi);
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}
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std::optional<u32> MMU::GetTranslatedAddress(u32 address)
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@ -292,8 +292,8 @@ private:
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template <const XCheckTLBFlag flag>
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TranslateAddressResult TranslateAddress(u32 address);
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TranslateAddressResult TranslatePageAddress(const EffectiveAddress address,
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const XCheckTLBFlag flag, bool* wi);
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template <const XCheckTLBFlag flag>
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TranslateAddressResult TranslatePageAddress(const EffectiveAddress address, bool* wi);
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void GenerateDSIException(u32 effective_address, bool write);
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void GenerateISIException(u32 effective_address);
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