[AArch64] Implement ZFreeze cache
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@ -165,6 +165,18 @@ int VertexLoaderARM64::ReadVertex(u64 attribute, int format, int count_in, int c
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m_float_emit.ST1(32, 1, coords, EncodeRegTo64(scratch2_reg));
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m_float_emit.ST1(32, 1, coords, EncodeRegTo64(scratch2_reg));
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}
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}
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// Z-Freeze
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if (native_format == &m_native_vtx_decl.position)
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{
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CMP(count_reg, 3);
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FixupBranch dont_store = B(CC_GT);
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MOVI2R(EncodeRegTo64(scratch2_reg), (u64)VertexLoaderManager::position_cache);
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ORR(scratch1_reg, WSP, count_reg, ArithOption(count_reg, ST_LSL, 4));
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ADD(EncodeRegTo64(scratch1_reg), EncodeRegTo64(scratch1_reg), EncodeRegTo64(scratch2_reg));
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m_float_emit.STUR(write_size, coords, EncodeRegTo64(scratch1_reg), -16);
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SetJumpTarget(dont_store);
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}
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native_format->components = count_out;
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native_format->components = count_out;
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native_format->enable = true;
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native_format->enable = true;
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native_format->offset = m_dst_ofs;
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native_format->offset = m_dst_ofs;
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@ -342,6 +354,14 @@ void VertexLoaderARM64::GenerateVertexLoader()
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LDRB(INDEX_UNSIGNED, scratch1_reg, src_reg, m_src_ofs);
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LDRB(INDEX_UNSIGNED, scratch1_reg, src_reg, m_src_ofs);
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AND(scratch1_reg, scratch1_reg, 0, 5);
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AND(scratch1_reg, scratch1_reg, 0, 5);
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STR(INDEX_UNSIGNED, scratch1_reg, dst_reg, m_dst_ofs);
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STR(INDEX_UNSIGNED, scratch1_reg, dst_reg, m_dst_ofs);
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// Z-Freeze
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CMP(count_reg, 3);
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FixupBranch dont_store = B(CC_GT);
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MOVI2R(EncodeRegTo64(scratch2_reg), (u64)VertexLoaderManager::position_matrix_index - sizeof(u32));
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STR(INDEX_UNSIGNED, scratch1_reg, EncodeRegTo64(scratch2_reg), 0);
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SetJumpTarget(dont_store);
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m_native_components |= VB_HAS_POSMTXIDX;
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m_native_components |= VB_HAS_POSMTXIDX;
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m_native_vtx_decl.posmtx.components = 4;
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m_native_vtx_decl.posmtx.components = 4;
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m_native_vtx_decl.posmtx.enable = true;
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m_native_vtx_decl.posmtx.enable = true;
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