DSP doc adding + dsp table ext changes
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2963 8ced0084-cf51-0410-be5f-012b33b47a6e
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nakeee
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1380497eae
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@ -220,8 +220,9 @@ const DSPOPCTemplate opcodes[] =
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{"M0", 0x8b00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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// These guys probably change the precision or range of some operations.
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// The question is which. 16-bit mode vs 40-bit mode sounds plausible for SET40/SET16.
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// Maybe Set15 makes the dsp drop the top bit from all calculations or something? Or clamp?
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// The question is which. 16-bit mode vs 40-bit mode sounds plausible for
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// SET40/SET16. Maybe Set15 makes the dsp drop the top bit from all
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// calculations or something? Or clamp?
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// SET15/CLR15 is commonly used around MULXAC in Zeldas.
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// SET16 is done around complicated loops with many madds etc.
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{"CLR15", 0x8c00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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@ -313,30 +314,37 @@ const DSPOPCTemplate cw =
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const DSPOPCTemplate opcodes_ext[] =
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{
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{"L", 0x0040, 0x00c4, nop, nop, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LN", 0x0044, 0x00c4, nop, nop, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"DR", 0x0004, 0x00fc, DSPInterpreter::Ext::dr, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"IR", 0x0008, 0x00fc, DSPInterpreter::Ext::ir, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"NR", 0x000c, 0x00fc, DSPInterpreter::Ext::nr, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"MV", 0x0010, 0x00f0, DSPInterpreter::Ext::mv, nop, 1, 2, {{P_REG18, 1, 0, 2, 0x000c}, {P_REG1C, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"S", 0x0020, 0x00e4, DSPInterpreter::Ext::s, nop, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, NULL, NULL,},
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{"SN", 0x0024, 0x00e4, DSPInterpreter::Ext::sn, nop, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, NULL, NULL,},
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{"L", 0x0040, 0x00c4, DSPInterpreter::Ext::l, nop, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LN", 0x0044, 0x00c4, DSPInterpreter::Ext::ln, nop, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LS", 0x0080, 0x00ce, nop, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, NULL, NULL,},
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{"LSN", 0x0084, 0x00ce, nop, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, NULL, NULL,},
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{"LSM", 0x0088, 0x00ce, nop, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, NULL, NULL,},
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{"LSNM", 0x008c, 0x00ce, nop, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, NULL, NULL,},
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{"SL", 0x0082, 0x00ce, nop, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, NULL, NULL,},
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{"LSN", 0x0084, 0x00ce, nop, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, NULL, NULL,},
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{"SLN", 0x0086, 0x00ce, nop, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, NULL, NULL,},
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{"LSM", 0x0088, 0x00ce, nop, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, NULL, NULL,},
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{"SLM", 0x008a, 0x00ce, nop, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, NULL, NULL,},
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{"LSNM", 0x008c, 0x00ce, nop, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, NULL, NULL,},
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{"SLNM", 0x008e, 0x00ce, nop, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, NULL, NULL,},
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{"S", 0x0020, 0x00e4, nop, nop, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, NULL, NULL,},
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{"SN", 0x0024, 0x00e4, nop, nop, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, NULL, NULL,},
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{"LDX", 0x00c0, 0x00cf, nop, nop, 1, 3, {{P_REG18, 1, 0, 4, 0x0010}, {P_REG1A, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, NULL, NULL,},
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/* FIXME: what are the LDX functions for? they have the same opcode as LD ones but different mask
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`{"LDX", 0x00c0, 0x00cf, nop, nop, 1, 3, {{P_REG18, 1, 0, 4, 0x0010}, {P_REG1A, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, NULL, NULL,},
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{"LDXN", 0x00c4, 0x00cf, nop, nop, 1, 3, {{P_REG18, 1, 0, 4, 0x0010}, {P_REG1A, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, NULL, NULL,},
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{"LDXM", 0x00c8, 0x00cf, nop, nop, 1, 3, {{P_REG18, 1, 0, 4, 0x0010}, {P_REG1A, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, NULL, NULL,},
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{"LDXNM", 0x00cc, 0x00cf, nop, nop, 1, 3, {{P_REG18, 1, 0, 4, 0x0010}, {P_REG1A, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, NULL, NULL,},
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{"LD", 0x00c0, 0x00cc, nop, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LDN", 0x00c4, 0x00cc, nop, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LDM", 0x00c8, 0x00cc, nop, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LDNM", 0x00cc, 0x00cc, nop, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"MV", 0x0010, 0x00f0, nop, nop, 1, 2, {{P_REG18, 1, 0, 2, 0x000c}, {P_REG1C, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"DR", 0x0004, 0x00fc, nop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"IR", 0x0008, 0x00fc, nop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"NR", 0x000c, 0x00fc, nop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LDXNM", 0x00cc, 0x00cf, nop, nop, 1, 3, {{P_REG18, 1, 0, 4, 0x0010}, {P_REG1A, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, NULL, NULL,},*/
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{"LD", 0x00c0, 0x00cc, DSPInterpreter::Ext::ld, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LDN", 0x00c4, 0x00cc, DSPInterpreter::Ext::ldn, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LDM", 0x00c8, 0x00cc, DSPInterpreter::Ext::ldm, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LDNM", 0x00cc, 0x00cc, DSPInterpreter::Ext::ldnm, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"XXX", 0x0000, 0x0000, nop, nop, 1, 1, {{P_VAL, 1, 0, 0, 0x00ff}}, NULL, NULL,},
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};
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@ -393,14 +401,14 @@ const u32 pdlabels_size = sizeof(pdlabels) / sizeof(pdlabel_t);
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const pdlabel_t regnames[] =
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{
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{0x00, "AR0", "Register 00",},
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{0x01, "AR1", "Register 01",},
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{0x02, "AR2", "Register 02",},
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{0x03, "AR3", "Register 03",},
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{0x04, "IX0", "Register 04",},
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{0x05, "IX1", "Register 05",},
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{0x06, "IX2", "Register 06",},
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{0x07, "IX3", "Register 07",},
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{0x00, "AR0", "Addr Reg 00",},
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{0x01, "AR1", "Addr Reg 01",},
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{0x02, "AR2", "Addr Reg 02",},
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{0x03, "AR3", "Addr Reg 03",},
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{0x04, "IX0", "Index Reg 1(04)",},
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{0x05, "IX1", "Index Reg 2(05)",},
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{0x06, "IX2", "Index Reg 3(06)",},
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{0x07, "IX3", "Indec Reg 4(07)",},
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{0x08, "R08", "Register 08",},
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{0x09, "R09", "Register 09",},
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{0x0a, "R10", "Register 10",},
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@ -421,10 +429,10 @@ const pdlabel_t regnames[] =
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{0x19, "AX1.L", "Extra Accu L 1",},
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{0x1a, "AX0.H", "Extra Accu H 0",},
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{0x1b, "AX1.H", "Extra Accu H 1",},
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{0x1c, "AC0.L", "Register 28",},
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{0x1d, "AC1.L", "Register 29",},
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{0x1e, "AC0.M", "Register 00",},
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{0x1f, "AC1.M", "Register 00",},
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{0x1c, "AC0.L", "Accu Low 0",},
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{0x1d, "AC1.L", "Accu Low 1",},
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{0x1e, "AC0.M", "Accu Mid 0",},
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{0x1f, "AC1.M", "Accu Mid 1",},
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// To resolve special names.
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{0x20, "ACC0", "Accu Full 0",},
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@ -132,60 +132,60 @@ void ln(const UDSPInstruction& opc)
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}
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// Not in duddie's doc
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// LD
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// xxxx xxxxx 11dd 00ss
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// LD $ax0.d $ax1.r @$arS
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// xxxx xxxx 11dr 00ss
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void ld(const UDSPInstruction& opc)
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{
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u8 dreg1 = (((opc.hex >> 5) & 0x1) << 1) + DSP_REG_AXL0;
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u8 dreg2 = (((opc.hex >> 4) & 0x1) << 1) + DSP_REG_AXL1;
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u8 dreg = (((opc.hex >> 5) & 0x1) << 1) + DSP_REG_AXL0;
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u8 rreg = (((opc.hex >> 4) & 0x1) << 1) + DSP_REG_AXL1;
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u8 sreg = opc.hex & 0x3;
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g_dsp.r[dreg1] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[dreg2] = dsp_dmem_read(g_dsp.r[DSP_REG_AR3]);
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g_dsp.r[dreg] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[rreg] = dsp_dmem_read(g_dsp.r[DSP_REG_AR3]);
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g_dsp.r[sreg]++;
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g_dsp.r[DSP_REG_AR3]++;
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}
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// Not in duddie's doc
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// LDN
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// xxxx xxxxx
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// LDN $ax0.d $ax1.r @$arS
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// xxxx xxxx 11dr 01ss
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void ldn(const UDSPInstruction& opc)
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{
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u8 dreg1 = (((opc.hex >> 5) & 0x1) << 1) + DSP_REG_AXL0;
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u8 dreg2 = (((opc.hex >> 4) & 0x1) << 1) + DSP_REG_AXL1;
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u8 dreg = (((opc.hex >> 5) & 0x1) << 1) + DSP_REG_AXL0;
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u8 rreg = (((opc.hex >> 4) & 0x1) << 1) + DSP_REG_AXL1;
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u8 sreg = opc.hex & 0x3;
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g_dsp.r[dreg1] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[dreg2] = dsp_dmem_read(g_dsp.r[DSP_REG_AR3]);
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g_dsp.r[dreg] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[rreg] = dsp_dmem_read(g_dsp.r[DSP_REG_AR3]);
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g_dsp.r[sreg] += g_dsp.r[sreg + DSP_REG_IX0];
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g_dsp.r[DSP_REG_AR3]++;
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}
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// Not in duddie's doc
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// LDM
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// xxxx xxxxx
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// LDM $ax0.d $ax1.r @$arS
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// xxxx xxxx 11dr 10ss
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void ldm(const UDSPInstruction& opc)
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{
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u8 dreg1 = (((opc.hex >> 5) & 0x1) << 1) + DSP_REG_AXL0;
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u8 dreg2 = (((opc.hex >> 4) & 0x1) << 1) + DSP_REG_AXL1;
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u8 dreg = (((opc.hex >> 5) & 0x1) << 1) + DSP_REG_AXL0;
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u8 rreg = (((opc.hex >> 4) & 0x1) << 1) + DSP_REG_AXL1;
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u8 sreg = opc.hex & 0x3;
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g_dsp.r[dreg1] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[dreg2] = dsp_dmem_read(g_dsp.r[DSP_REG_AR3]);
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g_dsp.r[dreg] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[rreg] = dsp_dmem_read(g_dsp.r[DSP_REG_AR3]);
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g_dsp.r[sreg]++;
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g_dsp.r[DSP_REG_AR3] += g_dsp.r[DSP_REG_IX3];
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}
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// Not in duddie's doc
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// LDNM
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// xxxx xxxxx
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// LDNM $ax0.d $ax1.r @$arS
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// xxxx xxxx 11dr 11ss
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void ldnm(const UDSPInstruction& opc)
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{
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u8 dreg1 = (((opc.hex >> 5) & 0x1) << 1) + DSP_REG_AXL0;
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u8 dreg2 = (((opc.hex >> 4) & 0x1) << 1) + DSP_REG_AXL1;
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u8 dreg = (((opc.hex >> 5) & 0x1) << 1) + DSP_REG_AXL0;
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u8 rreg = (((opc.hex >> 4) & 0x1) << 1) + DSP_REG_AXL1;
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u8 sreg = opc.hex & 0x3;
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g_dsp.r[dreg1] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[dreg2] = dsp_dmem_read(g_dsp.r[DSP_REG_AR3]);
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g_dsp.r[dreg] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[rreg] = dsp_dmem_read(g_dsp.r[DSP_REG_AR3]);
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g_dsp.r[sreg] += g_dsp.r[sreg + DSP_REG_IX0];
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g_dsp.r[DSP_REG_AR3] += g_dsp.r[DSP_REG_IX3];
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@ -37,5 +37,36 @@
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void dsp_op_ext_ops_pro(const UDSPInstruction& opc); // run any prologs
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void dsp_op_ext_ops_epi(const UDSPInstruction& opc); // run any epilogs
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namespace DSPInterpreter
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{
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namespace Ext
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{
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void l(const UDSPInstruction& opc);
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void ln(const UDSPInstruction& opc);
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void ls(const UDSPInstruction& opc);
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void lsn(const UDSPInstruction& opc);
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void lsm(const UDSPInstruction& opc);
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void lsnm(const UDSPInstruction& opc);
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void sl(const UDSPInstruction& opc);
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void sln(const UDSPInstruction& opc);
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void slm(const UDSPInstruction& opc);
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void slnm(const UDSPInstruction& opc);
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void s(const UDSPInstruction& opc);
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void sn(const UDSPInstruction& opc);
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void ldx(const UDSPInstruction& opc);
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void ldxn(const UDSPInstruction& opc);
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void ldxm(const UDSPInstruction& opc);
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void ldxnm(const UDSPInstruction& opc);
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void ld(const UDSPInstruction& opc);
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void ldn(const UDSPInstruction& opc);
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void ldm(const UDSPInstruction& opc);
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void ldnm(const UDSPInstruction& opc);
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void mv(const UDSPInstruction& opc);
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void dr(const UDSPInstruction& opc);
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void ir(const UDSPInstruction& opc);
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void nr(const UDSPInstruction& opc);
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} // end namespace Ext
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} // end namespace DSPinterpeter
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#endif
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