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JitArm64: Track singles in paired fp_logic.

This commit is contained in:
degasus 2016-02-11 11:02:25 +01:00
parent 003288a886
commit 0efdd5cacd
1 changed files with 12 additions and 6 deletions
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18
Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
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@ -105,18 +105,24 @@ void JitArm64::fp_logic(UGeckoInstruction inst)
if (op10 == 72 && b == d)
return;
bool is_single = fpr.IsSingle(b);
if (packed)
{
ARM64Reg VB = fpr.R(b, REG_REG);
ARM64Reg VD = fpr.RW(d, REG_REG);
RegType type = is_single ? REG_REG_SINGLE : REG_REG;
u8 size = is_single ? 32 : 64;
ARM64Reg (*reg_encoder)(ARM64Reg) = is_single ? EncodeRegToDouble : EncodeRegToQuad;
ARM64Reg VB = reg_encoder(fpr.R(b, type));
ARM64Reg VD = reg_encoder(fpr.RW(d, type));
switch (op10)
{
case 40: m_float_emit.FNEG(64, VD, VB); break;
case 40: m_float_emit.FNEG(size, VD, VB); break;
case 72: m_float_emit.ORR(VD, VB, VB); break;
case 136: m_float_emit.FABS(64, VD, VB);
m_float_emit.FNEG(64, VD, VD); break;
case 264: m_float_emit.FABS(64, VD, VB); break;
case 136: m_float_emit.FABS(size, VD, VB);
m_float_emit.FNEG(size, VD, VD); break;
case 264: m_float_emit.FABS(size, VD, VB); break;
default: _assert_msg_(DYNA_REC, 0, "fp_logic"); break;
}
}