From 0ebc510e6f997dcac30ccbfb7b873e3b097c7d41 Mon Sep 17 00:00:00 2001 From: JosJuice Date: Sat, 9 Jul 2022 21:19:25 +0200 Subject: [PATCH] JitArm64: Pass 32-bit temp GPR to WriteConditionalExceptionExit If a 64-bit register is passed to WriteConditionalExceptionExit, the LDR instruction in it will read too much data. This seems to be harmless right now, but causes problem in one of my PRs. --- .../Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp index 7914f0c371..a88543e995 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp @@ -109,7 +109,7 @@ void JitArm64::psq_lXX(UGeckoInstruction inst) LDR(EncodeRegTo64(type_reg), ARM64Reg::X30, ArithOption(EncodeRegTo64(type_reg), true)); BLR(EncodeRegTo64(type_reg)); - WriteConditionalExceptionExit(EXCEPTION_DSI, ARM64Reg::X30, ARM64Reg::Q1); + WriteConditionalExceptionExit(EXCEPTION_DSI, ARM64Reg::W30, ARM64Reg::Q1); m_float_emit.ORR(EncodeRegToDouble(VS), ARM64Reg::D0, ARM64Reg::D0); } @@ -261,7 +261,7 @@ void JitArm64::psq_stXX(UGeckoInstruction inst) LDR(EncodeRegTo64(type_reg), ARM64Reg::X30, ArithOption(EncodeRegTo64(type_reg), true)); BLR(EncodeRegTo64(type_reg)); - WriteConditionalExceptionExit(EXCEPTION_DSI, ARM64Reg::X30, ARM64Reg::Q1); + WriteConditionalExceptionExit(EXCEPTION_DSI, ARM64Reg::W30, ARM64Reg::Q1); } if (update && !early_update)