MMU: Sort physical access by common access pattern.
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@ -203,6 +203,20 @@ static T ReadFromHardware(u32 em_address)
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// TODO: Make sure these are safe for unaligned addresses.
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// TODO: Make sure these are safe for unaligned addresses.
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if ((em_address & 0xF8000000) == 0x00000000)
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{
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// Handle RAM; the masking intentionally discards bits (essentially creating
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// mirrors of memory).
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// TODO: Only the first REALRAM_SIZE is supposed to be backed by actual memory.
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return bswap((*(const T*)&Memory::m_pRAM[em_address & Memory::RAM_MASK]));
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}
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if (Memory::m_pEXRAM && (em_address >> 28) == 0x1 &&
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(em_address & 0x0FFFFFFF) < Memory::EXRAM_SIZE)
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{
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return bswap((*(const T*)&Memory::m_pEXRAM[em_address & 0x0FFFFFFF]));
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}
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// Locked L1 technically doesn't have a fixed address, but games all use 0xE0000000.
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// Locked L1 technically doesn't have a fixed address, but games all use 0xE0000000.
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if ((em_address >> 28) == 0xE && (em_address < (0xE0000000 + Memory::L1_CACHE_SIZE)))
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if ((em_address >> 28) == 0xE && (em_address < (0xE0000000 + Memory::L1_CACHE_SIZE)))
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{
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{
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@ -224,20 +238,6 @@ static T ReadFromHardware(u32 em_address)
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return (T)Memory::mmio_mapping->Read<typename std::make_unsigned<T>::type>(em_address);
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return (T)Memory::mmio_mapping->Read<typename std::make_unsigned<T>::type>(em_address);
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}
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}
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if ((em_address & 0xF8000000) == 0x00000000)
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{
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// Handle RAM; the masking intentionally discards bits (essentially creating
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// mirrors of memory).
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// TODO: Only the first REALRAM_SIZE is supposed to be backed by actual memory.
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return bswap((*(const T*)&Memory::m_pRAM[em_address & Memory::RAM_MASK]));
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}
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if (Memory::m_pEXRAM && (em_address >> 28) == 0x1 &&
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(em_address & 0x0FFFFFFF) < Memory::EXRAM_SIZE)
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{
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return bswap((*(const T*)&Memory::m_pEXRAM[em_address & 0x0FFFFFFF]));
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}
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PanicAlert("Unable to resolve read address %x PC %x", em_address, PC);
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PanicAlert("Unable to resolve read address %x PC %x", em_address, PC);
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return 0;
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return 0;
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}
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}
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@ -285,6 +285,22 @@ static void WriteToHardware(u32 em_address, const T data)
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// TODO: Make sure these are safe for unaligned addresses.
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// TODO: Make sure these are safe for unaligned addresses.
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if ((em_address & 0xF8000000) == 0x00000000)
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{
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// Handle RAM; the masking intentionally discards bits (essentially creating
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// mirrors of memory).
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// TODO: Only the first REALRAM_SIZE is supposed to be backed by actual memory.
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*(T*)&Memory::m_pRAM[em_address & Memory::RAM_MASK] = bswap(data);
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return;
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}
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if (Memory::m_pEXRAM && (em_address >> 28) == 0x1 &&
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(em_address & 0x0FFFFFFF) < Memory::EXRAM_SIZE)
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{
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*(T*)&Memory::m_pEXRAM[em_address & 0x0FFFFFFF] = bswap(data);
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return;
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}
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// Locked L1 technically doesn't have a fixed address, but games all use 0xE0000000.
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// Locked L1 technically doesn't have a fixed address, but games all use 0xE0000000.
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if ((em_address >> 28 == 0xE) && (em_address < (0xE0000000 + Memory::L1_CACHE_SIZE)))
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if ((em_address >> 28 == 0xE) && (em_address < (0xE0000000 + Memory::L1_CACHE_SIZE)))
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{
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{
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@ -337,22 +353,6 @@ static void WriteToHardware(u32 em_address, const T data)
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}
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}
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}
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}
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if ((em_address & 0xF8000000) == 0x00000000)
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{
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// Handle RAM; the masking intentionally discards bits (essentially creating
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// mirrors of memory).
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// TODO: Only the first REALRAM_SIZE is supposed to be backed by actual memory.
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*(T*)&Memory::m_pRAM[em_address & Memory::RAM_MASK] = bswap(data);
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return;
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}
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if (Memory::m_pEXRAM && (em_address >> 28) == 0x1 &&
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(em_address & 0x0FFFFFFF) < Memory::EXRAM_SIZE)
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{
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*(T*)&Memory::m_pEXRAM[em_address & 0x0FFFFFFF] = bswap(data);
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return;
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}
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PanicAlert("Unable to resolve write address %x PC %x", em_address, PC);
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PanicAlert("Unable to resolve write address %x PC %x", em_address, PC);
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return;
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return;
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}
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}
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