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fixes for my previous commits 

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6095 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
Marko Pusljar 2010-08-14 09:07:28 +00:00
parent 5cef906467
commit 0a606d7356
4 changed files with 13 additions and 26 deletions
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2
Source/Core/DSPCore/Src/DSPCore.h
View File

@ -163,7 +163,7 @@
#define SR_INT_ENABLE 0x0200 // Not 100% sure but duddie says so. This should replace the hack, if so.
#define SR_400 0x0400 // unknown
#define SR_EXT_INT_ENABLE 0x0800 // Appears in zelda - seems to disable external interupts
#define SR_ROUNDING_MODE 0x1000 // 0 - convergent rounding, 1 - twos complement rounding (source: motorola DSP56?00FM.pdf-s)
#define SR_1000 0x1000 // unknown
#define SR_MUL_MODIFY 0x2000 // 1 = normal. 0 = x2 (M0, M2)
#define SR_40_MODE_BIT 0x4000 // 0 = "16", 1 = "40" (SET16, SET40) Controls sign extension when loading mid accums.
#define SR_MUL_UNSIGNED 0x8000 // 0 = normal. 1 = unsigned (CLR15, SET15) If set, treats operands as unsigned. Tested with mulx only so far.

10
Source/Core/DSPCore/Src/DSPIntExtOps.cpp
View File

@ -74,12 +74,7 @@ void mv(const UDSPInstruction opc)
u8 sreg = (opc & 0x3) + DSP_REG_ACL0;
u8 dreg = ((opc >> 2) & 0x3);
#if 0 //more tests
if ((sreg >= DSP_REG_ACM0) && (g_dsp.r[DSP_REG_SR] & SR_40_MODE_BIT))
writeToBackLog(0, dreg + DSP_REG_AXL0, ((u16)dsp_get_acc_h(sreg-DSP_REG_ACM0) & 0x0080) ? 0x8000 : 0x7fff);
else
#endif
writeToBackLog(0, dreg + DSP_REG_AXL0, g_dsp.r[sreg]);
writeToBackLog(0, dreg + DSP_REG_AXL0, g_dsp.r[sreg]);
}
// S @$arD, $acS.S
@ -475,7 +470,8 @@ void zeroWriteBackLog()
}
}
//needed for 0x3...
//needed for 0x3... cases when main and extended are modifying the same ACC
//games are not doing that + in motorola (similar dsp) dox this is forbidden to do
//ex. corner case -> 0x3060: main opcode modifies .m, and extended .l -> .l shoudnt be zeroed because of .m write...
void zeroWriteBackLogPreserveAcc(u8 acc)
{

22
Source/Core/DSPCore/Src/DSPIntUtil.h
View File

@ -214,15 +214,10 @@ inline s64 dsp_get_long_prod_round_prodl()
{
s64 prod = dsp_get_long_prod();
if (g_dsp.r[DSP_REG_SR] & SR_ROUNDING_MODE)
if (prod & 0x10000)
prod = (prod + 0x8000) & ~0xffff;
else
{
if (prod & 0x10000)
prod = (prod + 0x8000) & ~0xffff;
else
prod = (prod + 0x7fff) & ~0xffff;
}
else
prod = (prod + 0x7fff) & ~0xffff;
return prod;
}
@ -280,15 +275,10 @@ inline s64 dsp_convert_long_acc(s64 val) // s64 -> s40
inline s64 dsp_round_long_acc(s64 val)
{
if (g_dsp.r[DSP_REG_SR] & SR_ROUNDING_MODE)
if (val & 0x10000)
val = (val + 0x8000) & ~0xffff;
else
{
if (val & 0x10000)
val = (val + 0x8000) & ~0xffff;
else
val = (val + 0x7fff) & ~0xffff;
}
else
val = (val + 0x7fff) & ~0xffff;
return val;
}

5
Source/DSPSpy/dspregs.h
View File

@ -17,7 +17,6 @@
#ifndef _DSPREGS_H
#define _DSPREGS_H
#endif
#define DSP_REG_AR0 0x00 // address registers
#define DSP_REG_AR1 0x01
@ -60,4 +59,6 @@
#define DSP_REG_ACM0 0x1e // Mid accumulator
#define DSP_REG_ACM1 0x1f
#define DSP_REG_ACH0 0x10 // Sign extended 8 bit register 0
#define DSP_REG_ACH1 0x11 // Sign extended 8 bit register 1
#define DSP_REG_ACH1 0x11 // Sign extended 8 bit register 1
#endif