JitArm64: Merge ps_mergeXX.

This commit is contained in:
degasus 2016-02-11 00:13:59 +01:00
parent 1b6d9dfc4e
commit 09af32c063
3 changed files with 35 additions and 66 deletions

View File

@ -151,10 +151,7 @@ public:
void ps_abs(UGeckoInstruction inst);
void ps_madd(UGeckoInstruction inst);
void ps_maddsX(UGeckoInstruction inst);
void ps_merge00(UGeckoInstruction inst);
void ps_merge01(UGeckoInstruction inst);
void ps_merge10(UGeckoInstruction inst);
void ps_merge11(UGeckoInstruction inst);
void ps_mergeXX(UGeckoInstruction inst);
void ps_mr(UGeckoInstruction inst);
void ps_msub(UGeckoInstruction inst);
void ps_muls0(UGeckoInstruction inst);

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@ -78,7 +78,7 @@ void JitArm64::ps_maddsX(UGeckoInstruction inst)
fpr.Unlock(V0);
}
void JitArm64::ps_merge00(UGeckoInstruction inst)
void JitArm64::ps_mergeXX(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITPairedOff);
@ -90,65 +90,37 @@ void JitArm64::ps_merge00(UGeckoInstruction inst)
ARM64Reg VB = fpr.R(b, REG_REG);
ARM64Reg VD = fpr.RW(d, REG_REG);
m_float_emit.TRN1(64, VD, VA, VB);
}
void JitArm64::ps_merge01(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITPairedOff);
FALLBACK_IF(inst.Rc);
u32 a = inst.FA, b = inst.FB, d = inst.FD;
ARM64Reg VA = fpr.R(a, REG_REG);
ARM64Reg VB = fpr.R(b, REG_REG);
ARM64Reg VD = fpr.RW(d, REG_REG);
m_float_emit.INS(64, VD, 0, VA, 0);
m_float_emit.INS(64, VD, 1, VB, 1);
}
void JitArm64::ps_merge10(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITPairedOff);
FALLBACK_IF(inst.Rc);
u32 a = inst.FA, b = inst.FB, d = inst.FD;
ARM64Reg VA = fpr.R(a, REG_REG);
ARM64Reg VB = fpr.R(b, REG_REG);
ARM64Reg VD = fpr.RW(d, REG_REG);
if (d != a && d != b)
switch (inst.SUBOP10)
{
m_float_emit.INS(64, VD, 0, VA, 1);
m_float_emit.INS(64, VD, 1, VB, 0);
case 528: //00
m_float_emit.TRN1(64, VD, VA, VB);
break;
case 560: //01
m_float_emit.INS(64, VD, 0, VA, 0);
m_float_emit.INS(64, VD, 1, VB, 1);
break;
case 592: //10
if (d != a && d != b)
{
m_float_emit.INS(64, VD, 0, VA, 1);
m_float_emit.INS(64, VD, 1, VB, 0);
}
else
{
ARM64Reg V0 = fpr.GetReg();
m_float_emit.INS(64, V0, 0, VA, 1);
m_float_emit.INS(64, V0, 1, VB, 0);
m_float_emit.ORR(VD, V0, V0);
fpr.Unlock(V0);
}
break;
case 624: //11
m_float_emit.TRN2(64, VD, VA, VB);
break;
default:
_assert_msg_(DYNA_REC, 0, "ps_merge - invalid op");
break;
}
else
{
ARM64Reg V0 = fpr.GetReg();
m_float_emit.INS(64, V0, 0, VA, 1);
m_float_emit.INS(64, V0, 1, VB, 0);
m_float_emit.ORR(VD, V0, V0);
fpr.Unlock(V0);
}
}
void JitArm64::ps_merge11(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITPairedOff);
FALLBACK_IF(inst.Rc);
u32 a = inst.FA, b = inst.FB, d = inst.FD;
ARM64Reg VA = fpr.R(a, REG_REG);
ARM64Reg VB = fpr.R(b, REG_REG);
ARM64Reg VD = fpr.RW(d, REG_REG);
m_float_emit.TRN2(64, VD, VA, VB);
}
void JitArm64::ps_mr(UGeckoInstruction inst)

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@ -110,10 +110,10 @@ static GekkoOPTemplate table4[] =
{64, &JitArm64::FallBackToInterpreter}, // ps_cmpu1
{72, &JitArm64::ps_mr}, // ps_mr
{96, &JitArm64::FallBackToInterpreter}, // ps_cmpo1
{528, &JitArm64::ps_merge00}, // ps_merge00
{560, &JitArm64::ps_merge01}, // ps_merge01
{592, &JitArm64::ps_merge10}, // ps_merge10
{624, &JitArm64::ps_merge11}, // ps_merge11
{528, &JitArm64::ps_mergeXX}, // ps_merge00
{560, &JitArm64::ps_mergeXX}, // ps_merge01
{592, &JitArm64::ps_mergeXX}, // ps_merge10
{624, &JitArm64::ps_mergeXX}, // ps_merge11
{1014, &JitArm64::FallBackToInterpreter}, // dcbz_l
};