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JitArm64: Don't assume fastmem arena is available

This commit is contained in:
OatmealDome 2020-06-29 00:42:56 -04:00
parent 2e8d1dd1db
commit 089ffb9ef4
2 changed files with 5 additions and 5 deletions
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6
Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp
View File

@ -121,7 +121,7 @@ void JitArm64::SafeLoadToReg(u32 dest, s32 addr, s32 offsetReg, u32 flags, s32 o
if (is_immediate)
mmio_address = PowerPC::IsOptimizableMMIOAccess(imm_addr, access_size);
if (is_immediate && PowerPC::IsOptimizableRAMAddress(imm_addr))
if (jo.fastmem_arena && is_immediate && PowerPC::IsOptimizableRAMAddress(imm_addr))
{
EmitBackpatchRoutine(flags, true, false, dest_reg, XA, BitSet32(0), BitSet32(0));
}
@ -256,7 +256,7 @@ void JitArm64::SafeStoreFromReg(s32 dest, u32 value, s32 regOffset, u32 flags, s
STR(INDEX_UNSIGNED, X0, PPC_REG, PPCSTATE_OFF(gather_pipe_ptr));
js.fifoBytesSinceCheck += accessSize >> 3;
}
else if (is_immediate && PowerPC::IsOptimizableRAMAddress(imm_addr))
else if (jo.fastmem_arena && is_immediate && PowerPC::IsOptimizableRAMAddress(imm_addr))
{
MOVI2R(XA, imm_addr);
EmitBackpatchRoutine(flags, true, false, RS, XA, BitSet32(0), BitSet32(0));
@ -599,7 +599,7 @@ void JitArm64::dcbz(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff);
FALLBACK_IF(jo.memcheck);
FALLBACK_IF(jo.memcheck || !jo.fastmem_arena);
FALLBACK_IF(SConfig::GetInstance().bLowDCBZHack);
int a = inst.RA, b = inst.RB;

4
Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp
View File

@ -167,7 +167,7 @@ void JitArm64::lfXX(UGeckoInstruction inst)
fprs_in_use[0] = 0; // Q0
fprs_in_use[VD - Q0] = 0;
if (is_immediate && PowerPC::IsOptimizableRAMAddress(imm_addr))
if (jo.fastmem_arena && is_immediate && PowerPC::IsOptimizableRAMAddress(imm_addr))
{
EmitBackpatchRoutine(flags, true, false, VD, XA, BitSet32(0), BitSet32(0));
}
@ -384,7 +384,7 @@ void JitArm64::stfXX(UGeckoInstruction inst)
MOVI2R(gpr.R(a), imm_addr);
}
}
else if (PowerPC::IsOptimizableRAMAddress(imm_addr))
else if (jo.fastmem_arena && PowerPC::IsOptimizableRAMAddress(imm_addr))
{
EmitBackpatchRoutine(flags, true, false, V0, XA, BitSet32(0), BitSet32(0));
}