commit
0674e344c4
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@ -1447,8 +1447,10 @@ void XEmitter::WriteFMA4Op(u8 op, X64Reg dest, X64Reg regOp1, X64Reg regOp2, con
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void XEmitter::WriteBMIOp(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, const OpArg& arg, int extrabytes)
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{
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CheckFlags();
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if (arg.IsImm())
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PanicAlert("BMI1/2 instructions don't support immediate operands.");
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if (size != 32 && size != 64)
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PanicAlert("VEX GPR instructions only support 32-bit and 64-bit modes!");
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PanicAlert("BMI1/2 instructions only support 32-bit and 64-bit modes!");
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int W = size == 64;
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WriteVEXOp(opPrefix, op, regOp1, regOp2, arg, W, extrabytes);
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}
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@ -676,7 +676,11 @@ void Jit64::boolX(UGeckoInstruction inst)
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}
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else if (inst.SUBOP10 == 60) // andcx
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{
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if (a == b)
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if (cpu_info.bBMI1 && gpr.R(b).IsSimpleReg() && !gpr.R(s).IsImm())
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{
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ANDN(32, gpr.RX(a), gpr.RX(b), gpr.R(s));
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}
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else if (a == b)
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{
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NOT(32, gpr.R(a));
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AND(32, gpr.R(a), operand);
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@ -745,9 +749,16 @@ void Jit64::boolX(UGeckoInstruction inst)
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}
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else if (inst.SUBOP10 == 60) // andcx
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{
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MOV(32, gpr.R(a), gpr.R(b));
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NOT(32, gpr.R(a));
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AND(32, gpr.R(a), gpr.R(s));
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if (cpu_info.bBMI1 && gpr.R(b).IsSimpleReg() && !gpr.R(s).IsImm())
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{
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ANDN(32, gpr.RX(a), gpr.RX(b), gpr.R(s));
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}
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else
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{
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MOV(32, gpr.R(a), gpr.R(b));
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NOT(32, gpr.R(a));
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AND(32, gpr.R(a), gpr.R(s));
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}
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}
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else if (inst.SUBOP10 == 444) // orx
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{
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