ShuriZma
/
dolphin
mirror of https://github.com/dolphin-emu/dolphin.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

DSPSpy/Base: Clean up trailing whitespace

This commit is contained in:
Léo Lam 2017-09-19 19:14:08 +02:00
parent 8ebdd62f45
commit 05cdbccc38
1 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
Source/DSPSpy/tests/dsp_base.inc
View File

@ -106,7 +106,7 @@ MEM_LO: equ 0x0f7F
jmp start_of_test jmp start_of_test
; This is where we jump when we're done testing, see above. ; This is where we jump when we're done testing, see above.
; We just fall into a loop, playing dead until someone resets the DSP. ; We just fall into a loop, playing dead until someone resets the DSP.
end_of_test: end_of_test:
nop nop
jmp end_of_test jmp end_of_test
@ -156,7 +156,7 @@ irq:
si @DIRQ, #0x0001 si @DIRQ, #0x0001
halt ; Through some magic this allows us to properly ack the exception in dspspy halt ; Through some magic this allows us to properly ack the exception in dspspy
;rti ; allow dumping of ucodes which cause exceptions...probably not safe at all ;rti ; allow dumping of ucodes which cause exceptions...probably not safe at all
; DMA:s the current state of the registers back to the PowerPC. To do this, ; DMA:s the current state of the registers back to the PowerPC. To do this,
; it must write the contents of all regs to DRAM. ; it must write the contents of all regs to DRAM.
; Unfortunately, this loop uses ar0 so it's best to use AR1 and friends for testing ; Unfortunately, this loop uses ar0 so it's best to use AR1 and friends for testing
@ -216,13 +216,13 @@ send_back:
dma_copy: dma_copy:
mrr $ax0.l, $ac1.m mrr $ax0.l, $ac1.m
; Wait for the CPU to send us a mail. ; Wait for the CPU to send us a mail.
call 0x807e call 0x807e
si @DMBH, #0x8888 si @DMBH, #0x8888
si @DMBL, #0xfeeb si @DMBL, #0xfeeb
si @DIRQ, #0x0001 si @DIRQ, #0x0001
; wait for the CPU to recieve our response before we execute the next op ; wait for the CPU to recieve our response before we execute the next op
call 0x8078 call 0x8078
andi $ac0.m, #0x7fff andi $ac0.m, #0x7fff
lrs $ac1.m, @CMBL lrs $ac1.m, @CMBL
@ -261,14 +261,14 @@ dma_copy:
lrri $ac0.m, @$ar0 lrri $ac0.m, @$ar0
lrri $ac1.m, @$ar0 lrri $ac1.m, @$ar0
lr $ar0, @REGS_BASE lr $ar0, @REGS_BASE
ret ; from send_back ret ; from send_back
; If you are in set40 mode, use this instead of send_back if you want to stay ; If you are in set40 mode, use this instead of send_back if you want to stay
; in set40 mode. ; in set40 mode.
send_back_40: send_back_40:
set16 set16
call send_back call send_back
set40 set40
ret ret