Jit64: optimize ps_sum
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@ -156,24 +156,40 @@ void Jit64::ps_sum(UGeckoInstruction inst)
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int b = inst.FB;
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int c = inst.FC;
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fpr.Lock(a, b, c, d);
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OpArg op_a = fpr.R(a);
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fpr.BindToRegister(d, false);
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X64Reg tmp = d == b || d == c ? XMM0 : fpr.RX(d);
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MOVDDUP(tmp, op_a); // {a.ps0, a.ps0}
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ADDPD(tmp, fpr.R(b)); // {a.ps0 + b.ps0, a.ps0 + b.ps1}
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switch (inst.SUBOP5)
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{
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case 10:
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MOVDDUP(XMM0, fpr.R(a)); // {a.ps0, a.ps0}
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ADDPD(XMM0, fpr.R(b)); // {a.ps0 + b.ps0, a.ps0 + b.ps1}
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UNPCKHPD(XMM0, fpr.R(c)); // {a.ps0 + b.ps1, c.ps1}
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case 10: // ps_sum0
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UNPCKHPD(tmp, fpr.R(c)); // {a.ps0 + b.ps1, c.ps1}
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break;
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case 11:
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MOVDDUP(XMM1, fpr.R(a)); // {a.ps0, a.ps0}
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ADDPD(XMM1, fpr.R(b)); // {a.ps0 + b.ps0, a.ps0 + b.ps1}
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MOVAPD(XMM0, fpr.R(c));
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SHUFPD(XMM0, R(XMM1), 2); // {c.ps0, a.ps0 + b.ps1}
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case 11: // ps_sum1
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// {c.ps0, a.ps0 + b.ps1}
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if (fpr.R(c).IsSimpleReg())
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{
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if (cpu_info.bSSE4_1)
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{
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BLENDPD(tmp, fpr.R(c), 1);
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}
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else
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{
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MOVAPD(XMM1, fpr.R(c));
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SHUFPD(XMM1, R(tmp), 2);
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tmp = XMM1;
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}
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}
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else
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{
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MOVLPD(tmp, fpr.R(c));
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}
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break;
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default:
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PanicAlert("ps_sum WTF!!!");
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}
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fpr.BindToRegister(d, false);
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ForceSinglePrecision(fpr.RX(d), R(XMM0));
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ForceSinglePrecision(fpr.RX(d), R(tmp));
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SetFPRFIfNeeded(fpr.RX(d));
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fpr.UnlockAll();
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}
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@ -192,10 +208,10 @@ void Jit64::ps_muls(UGeckoInstruction inst)
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fpr.Lock(a, c, d);
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switch (inst.SUBOP5)
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{
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case 12:
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case 12: // ps_muls0
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MOVDDUP(XMM0, fpr.R(c));
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break;
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case 13:
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case 13: // ps_muls1
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avx_op(&XEmitter::VSHUFPD, &XEmitter::SHUFPD, XMM0, fpr.R(c), fpr.R(c), 3);
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break;
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default:
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