Interpreter_SystemRegisters: Check processor privilege level in mfspr and mtspr
If a program executing in user mode tries to write to any SPRs other than XER, LR, or CTR registers, then a program exception occurs. Similarly this also applies for reading SPRs as well, however the upper and lower timebase halves can also be read (but not written to).
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@ -194,9 +194,13 @@ void Interpreter::mfspr(UGeckoInstruction inst)
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{
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{
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const u32 index = ((inst.SPR & 0x1F) << 5) + ((inst.SPR >> 5) & 0x1F);
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const u32 index = ((inst.SPR & 0x1F) << 5) + ((inst.SPR >> 5) & 0x1F);
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// TODO - check processor privilege level - many of these require privilege
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// XER, LR, CTR, and timebase halves are the only ones available in user mode.
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// XER LR CTR are the only ones available in user mode, time base can be read too.
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if (MSR.PR && index != SPR_XER && index != SPR_LR && index != SPR_CTR && index != SPR_TL &&
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// GameCube games always run in superuser mode, but hey....
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index != SPR_TU)
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{
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PowerPC::ppcState.Exceptions |= EXCEPTION_PROGRAM;
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return;
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}
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switch (index)
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switch (index)
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{
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{
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@ -237,13 +241,17 @@ void Interpreter::mfspr(UGeckoInstruction inst)
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void Interpreter::mtspr(UGeckoInstruction inst)
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void Interpreter::mtspr(UGeckoInstruction inst)
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{
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{
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const u32 index = (inst.SPRU << 5) | (inst.SPRL & 0x1F);
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const u32 index = (inst.SPRU << 5) | (inst.SPRL & 0x1F);
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// XER, LR, and CTR are the only ones available to be written to in user mode
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if (MSR.PR && index != SPR_XER && index != SPR_LR && index != SPR_CTR)
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{
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PowerPC::ppcState.Exceptions |= EXCEPTION_PROGRAM;
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return;
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}
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const u32 old_value = rSPR(index);
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const u32 old_value = rSPR(index);
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rSPR(index) = rGPR[inst.RD];
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rSPR(index) = rGPR[inst.RD];
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// TODO - check processor privilege level - many of these require privilege
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// XER LR CTR are the only ones available in user mode, time base can be read too.
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// GameCube games always run in superuser mode, but hey....
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// Our DMA emulation is highly inaccurate - instead of properly emulating the queue
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// Our DMA emulation is highly inaccurate - instead of properly emulating the queue
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// and so on, we simply make all DMA:s complete instantaneously.
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// and so on, we simply make all DMA:s complete instantaneously.
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