MMU: Remove now-unused defines
Now that we're using register unions where applicable, we can remove these defines, since they're now unused.
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Lioncash
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ee40b640d3
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029aff0741
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@ -1134,40 +1134,6 @@ TranslateResult JitCache_TranslateAddress(u32 address)
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#define PPC_EXC_DSISR_PAGE (1 << 30)
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#define PPC_EXC_DSISR_PROT (1 << 27)
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#define PPC_EXC_DSISR_STORE (1 << 25)
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#define SDR1_HTABORG(v) (((v) >> 16) & 0xffff)
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#define SDR1_HTABMASK(v) ((v)&0x1ff)
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#define SDR1_PAGETABLE_BASE(v) ((v)&0xffff)
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#define SR_T (1 << 31)
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#define SR_Ks (1 << 30)
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#define SR_Kp (1 << 29)
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#define SR_N (1 << 28)
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#define SR_VSID(v) ((v)&0xffffff)
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#define SR_BUID(v) (((v) >> 20) & 0x1ff)
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#define SR_CNTRL_SPEC(v) ((v)&0xfffff)
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#define EA_SR(v) (((v) >> 28) & 0xf)
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#define EA_PageIndex(v) (((v) >> 12) & 0xffff)
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#define EA_Offset(v) ((v)&0xfff)
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#define EA_API(v) (((v) >> 22) & 0x3f)
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#define PA_RPN(v) (((v) >> 12) & 0xfffff)
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#define PA_Offset(v) ((v)&0xfff)
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#define PTE1_V (1 << 31)
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#define PTE1_VSID(v) (((v) >> 7) & 0xffffff)
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#define PTE1_H (1 << 6)
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#define PTE1_API(v) ((v)&0x3f)
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#define PTE2_RPN(v) ((v)&0xfffff000)
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#define PTE2_R (1 << 8)
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#define PTE2_C (1 << 7)
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#define PTE2_WIMG(v) (((v) >> 3) & 0xf)
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#define PTE2_PP(v) ((v)&3)
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static void GenerateDSIException(u32 effective_address, bool write)
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{
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// DSI exceptions are only supported in MMU mode.
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@ -1178,14 +1144,17 @@ static void GenerateDSIException(u32 effective_address, bool write)
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return;
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}
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if (effective_address)
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PowerPC::ppcState.spr[SPR_DSISR] = PPC_EXC_DSISR_PAGE | PPC_EXC_DSISR_STORE;
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constexpr u32 dsisr_page = 1U << 30;
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constexpr u32 dsisr_store = 1U << 25;
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if (effective_address != 0)
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ppcState.spr[SPR_DSISR] = dsisr_page | dsisr_store;
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else
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PowerPC::ppcState.spr[SPR_DSISR] = PPC_EXC_DSISR_PAGE;
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ppcState.spr[SPR_DSISR] = dsisr_page;
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PowerPC::ppcState.spr[SPR_DAR] = effective_address;
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ppcState.spr[SPR_DAR] = effective_address;
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PowerPC::ppcState.Exceptions |= EXCEPTION_DSI;
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ppcState.Exceptions |= EXCEPTION_DSI;
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}
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static void GenerateISIException(u32 effective_address)
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@ -1301,22 +1270,35 @@ void InvalidateTLBEntry(u32 address)
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ppcState.tlb[1][entry_index].Invalidate();
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}
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union EffectiveAddress
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{
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BitField<0, 12, u32> offset;
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BitField<12, 16, u32> page_index;
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BitField<22, 6, u32> API;
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BitField<28, 4, u32> SR;
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u32 Hex = 0;
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EffectiveAddress() = default;
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explicit EffectiveAddress(u32 address) : Hex{address} {}
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};
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// Page Address Translation
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static TranslateAddressResult TranslatePageAddress(const u32 address, const XCheckTLBFlag flag,
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bool* wi)
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static TranslateAddressResult TranslatePageAddress(const EffectiveAddress address,
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const XCheckTLBFlag flag, bool* wi)
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{
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// TLB cache
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// This catches 99%+ of lookups in practice, so the actual page table entry code below doesn't
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// benefit much from optimization.
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u32 translated_address = 0;
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const TLBLookupResult res = LookupTLBPageAddress(flag, address, &translated_address, wi);
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const TLBLookupResult res = LookupTLBPageAddress(flag, address.Hex, &translated_address, wi);
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if (res == TLBLookupResult::Found)
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{
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return TranslateAddressResult{TranslateAddressResultEnum::PAGE_TABLE_TRANSLATED,
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translated_address};
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}
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const auto sr = UReg_SR{ppcState.sr[EA_SR(address)]};
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const auto sr = UReg_SR{ppcState.sr[address.SR]};
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if (sr.T != 0)
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return TranslateAddressResult{TranslateAddressResultEnum::DIRECT_STORE_SEGMENT, 0};
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@ -1329,10 +1311,10 @@ static TranslateAddressResult TranslatePageAddress(const u32 address, const XChe
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return TranslateAddressResult{TranslateAddressResultEnum::PAGE_FAULT, 0};
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}
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const u32 offset = EA_Offset(address); // 12 bit
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const u32 page_index = EA_PageIndex(address); // 16 bit
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const u32 offset = address.offset; // 12 bit
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const u32 page_index = address.page_index; // 16 bit
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const u32 VSID = sr.VSID; // 24 bit
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const u32 api = EA_API(address); // 6 bit (part of page_index)
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const u32 api = address.API; // 6 bit (part of page_index)
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// hash function no 1 "xor" .360
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u32 hash = (VSID ^ page_index);
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@ -1387,7 +1369,7 @@ static TranslateAddressResult TranslatePageAddress(const u32 address, const XChe
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// We already updated the TLB entry if this was caused by a C bit.
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if (res != TLBLookupResult::UpdateC)
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UpdateTLBEntry(flag, pte2, address);
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UpdateTLBEntry(flag, pte2, address.Hex);
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*wi = (pte2.WIMG & 0b1100) != 0;
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@ -1558,7 +1540,7 @@ static TranslateAddressResult TranslateAddress(u32 address)
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if (TranslateBatAddess(IsOpcodeFlag(flag) ? ibat_table : dbat_table, &address, &wi))
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return TranslateAddressResult{TranslateAddressResultEnum::BAT_TRANSLATED, address, wi};
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return TranslatePageAddress(address, flag, &wi);
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return TranslatePageAddress(EffectiveAddress{address}, flag, &wi);
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}
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std::optional<u32> GetTranslatedAddress(u32 address)
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