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Jit_Integer: Handle NOP case for oris as well 

Like ori, this can also be used as a NOP under the same conditions.
This commit is contained in:
Lioncash 2018-03-22 15:34:47 -04:00
parent 42fce74f39
commit 007f9e5309
2 changed files with 15 additions and 10 deletions
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13
Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
View File

@ -305,17 +305,20 @@ void Jit64::reg_imm(UGeckoInstruction inst)
regimmop(d, a, false, (u32)inst.SIMM_16 << 16, Add, &XEmitter::ADD); regimmop(d, a, false, (u32)inst.SIMM_16 << 16, Add, &XEmitter::ADD);
break; break;
case 24: // ori case 24: // ori
if (a == s && inst.UIMM == 0) // check for nop case 25: // oris
{
// check for nop
if (a == s && inst.UIMM == 0)
{ {
// Make the nop visible in the generated code. not much use but interesting if we see one. // Make the nop visible in the generated code. not much use but interesting if we see one.
NOP(); NOP();
return; return;
} }
regimmop(a, s, true, inst.UIMM, Or, &XEmitter::OR);
break; const u32 immediate = inst.OPCD == 24 ? inst.UIMM : inst.UIMM << 16;
case 25: // oris regimmop(a, s, true, immediate, Or, &XEmitter::OR);
regimmop(a, s, true, inst.UIMM << 16, Or, &XEmitter::OR, false);
break; break;
}
case 28: // andi case 28: // andi
regimmop(a, s, true, inst.UIMM, And, &XEmitter::AND, true); regimmop(a, s, true, inst.UIMM, And, &XEmitter::AND, true);
break; break;

10
Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp
View File

@ -122,17 +122,19 @@ void JitArm64::arith_imm(UGeckoInstruction inst)
switch (inst.OPCD) switch (inst.OPCD)
{ {
case 24: // ori case 24: // ori
case 25: // oris
{
// check for nop // check for nop
if (a == s && inst.UIMM == 0) if (a == s && inst.UIMM == 0)
{ {
// NOP // NOP
return; return;
} }
reg_imm(a, s, inst.UIMM, BitOR, &ARM64XEmitter::ORRI2R);
break; const u32 immediate = inst.OPCD == 24 ? inst.UIMM : inst.UIMM << 16;
case 25: // oris reg_imm(a, s, immediate, BitOR, &ARM64XEmitter::ORRI2R);
reg_imm(a, s, inst.UIMM << 16, BitOR, &ARM64XEmitter::ORRI2R);
break; break;
}
case 28: // andi case 28: // andi
reg_imm(a, s, inst.UIMM, BitAND, &ARM64XEmitter::ANDI2R, true); reg_imm(a, s, inst.UIMM, BitAND, &ARM64XEmitter::ANDI2R, true);
break; break;