2021-08-15 00:36:55 +00:00
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incdir "tests"
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include "dsp_base.inc"
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; Tests the behavior of SI, SRS, and LRS when CR is changed
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; Register that is writable but with contents that doesn't matter (COEF_A1_0)
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TEST_REG: equ 0xFFA0 ; 0xFF00 (not writable)
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; This is separate because SRS and SI currently require value 0..7f or ff80..ffff,
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; though the actual behavior doesn't match that
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TEST_ADDR: equ 0xFFA0 ; 0x0000
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; Memory addresses
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TEST_MEM: equ 0x00A0 ; 0x0000
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TEST_MEM_2: equ 0x01A0 ; 0x0100
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2021-08-15 22:26:03 +00:00
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test_main:
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2021-08-15 00:36:55 +00:00
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LRI $AC0.L, #0xf00f
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SR @TEST_REG, $AC0.L
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SR @TEST_MEM, $AC0.L
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SR @TEST_MEM_2, $AC0.L
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CALL send_regs
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; Observed: writes to TEST_REG
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SI @TEST_ADDR, #0xf11f
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CALL send_regs
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LRI $AC0.L, #0xf22f
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; Observed: writes to TEST_REG
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SRS @TEST_ADDR, $AC0.L
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CALL send_regs
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LRI $CR, #0x0000
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; Observed: still writes to TEST_REG
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SI @TEST_ADDR, #0xf33f
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CALL send_regs
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LRI $AC0.L, #0xf44f
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; Observed: writes to TEST_MEM
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SRS @TEST_ADDR, $AC0.L
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CALL send_regs
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LRI $CR, #0x0001
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; Observed: still writes to TEST_REG
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SI @TEST_ADDR, #0xf55f
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CALL send_regs
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LRI $AC0.L, #0xf66f
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; Observed: writes to TEST_MEM_2
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SRS @TEST_ADDR, $AC0.L
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CALL send_regs
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; At this point, TEST_REG should be f55f, TEST_MEM should be f44f,
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; and TEST_MEM_2 should be f66f. Test the behavior of LRS.
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; Changes to prod.l are for display only.
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LRI $CR, #0x00ff
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LRI $prod.l, #0xf55f
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LRS $AC0.L, @TEST_ADDR
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CALL send_regs
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LRI $CR, #0x0000
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LRI $prod.l, #0xf44f
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LRS $AC0.L, @TEST_ADDR
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CALL send_regs
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LRI $CR, #0x0001
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LRI $prod.l, #0xf66f
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LRS $AC0.L, @TEST_ADDR
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CALL send_regs
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; We're done, DO NOT DELETE THIS LINE
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JMP end_of_test
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send_regs:
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; For display purposes only
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LRI $prod.m1, #TEST_REG
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LRI $prod.h, #TEST_MEM
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LRI $prod.m2, #TEST_MEM_2
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; Actual registers
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LR $AC1.L, @TEST_REG
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LR $AC0.M, @TEST_MEM
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LR $AC1.M, @TEST_MEM_2
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CALL send_back
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RET
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