99 lines
2.9 KiB
C
99 lines
2.9 KiB
C
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#ifndef __PROCESSOR_H__
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#define __PROCESSOR_H__
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#include <gctypes.h>
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#define __stringify(rn) #rn
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#define ATTRIBUTE_ALIGN(v) __attribute__((aligned(v)))
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#define ppcsync() asm volatile("sc")
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#define ppchalt() ({ \
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asm volatile("sync"); \
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while(1) { \
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asm volatile("nop"); \
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asm volatile("li 3,0"); \
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asm volatile("nop"); \
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} \
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})
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#define mfdcr(_rn) ({register u32 _rval; \
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asm volatile("mfdcr %0," __stringify(_rn) \
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: "=r" (_rval)); _rval;})
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#define mtdcr(rn, val) asm volatile("mtdcr " __stringify(rn) ",%0" : : "r" (val))
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#define mfmsr() ({register u32 _rval; \
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asm volatile("mfmsr %0" : "=r" (_rval)); _rval;})
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#define mtmsr(val) asm volatile("mtmsr %0" : : "r" (val))
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#define mfdec() ({register u32 _rval; \
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asm volatile("mfdec %0" : "=r" (_rval)); _rval;})
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#define mtdec(_val) asm volatile("mtdec %0" : : "r" (_val))
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#define mfspr(_rn) ({register u32 _rval; \
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asm volatile("mfspr %0," __stringify(_rn) \
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: "=r" (_rval)); _rval;})
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#define mtspr(_rn, _val) asm volatile("mtspr " __stringify(_rn) ",%0" : : "r" (_val))
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#define mfwpar() mfspr(921)
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#define mtwpar(_val) mtspr(921,_val)
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#define mfmmcr0() mfspr(952)
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#define mtmmcr0(_val) mtspr(952,_val)
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#define mfmmcr1() mfspr(956)
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#define mtmmcr1(_val) mtspr(956,_val)
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#define mfpmc1() mfspr(953)
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#define mtpmc1(_val) mtspr(953,_val)
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#define mfpmc2() mfspr(954)
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#define mtpmc2(_val) mtspr(954,_val)
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#define mfpmc3() mfspr(957)
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#define mtpmc3(_val) mtspr(957,_val)
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#define mfpmc4() mfspr(958)
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#define mtpmc4(_val) mtspr(958,_val)
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#define cntlzw(_val) ({register u32 _rval; \
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asm volatile("cntlzw %0, %1" : "=r"((_rval)) : "r"((_val))); _rval;})
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#define _CPU_MSR_GET( _msr_value ) \
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do { \
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_msr_value = 0; \
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asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
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} while (0)
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#define _CPU_MSR_SET( _msr_value ) \
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{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
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#define _CPU_ISR_Enable() \
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{ register u32 _val = 0; \
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asm volatile ("mfmsr %0; ori %0,%0,0x8000; mtmsr %0" : \
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"=&r" (_val) : "0" (_val));\
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}
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#define _CPU_ISR_Disable( _isr_cookie ) \
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{ register u32 _disable_mask = MSR_EE; \
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_isr_cookie = 0; \
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asm volatile ( \
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"mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
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"=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
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"0" ((_isr_cookie)), "1" ((_disable_mask)) \
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); \
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}
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#define _CPU_ISR_Restore( _isr_cookie ) \
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{ \
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asm volatile ( "mtmsr %0" : \
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"=r" ((_isr_cookie)) : \
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"0" ((_isr_cookie))); \
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}
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#define _CPU_ISR_Flash( _isr_cookie ) \
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{ register u32 _disable_mask = MSR_EE; \
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asm volatile ( \
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"mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
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"=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
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"0" ((_isr_cookie)), "1" ((_disable_mask)) \
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); \
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}
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#endif
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