543 lines
17 KiB
C
543 lines
17 KiB
C
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// Copyright (C) 2003-2008 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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#ifndef _DOLPHIN_INTEL_CODEGEN
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#define _DOLPHIN_INTEL_CODEGEN
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#include "Common.h"
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namespace Gen
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{
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enum X64Reg
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{
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EAX = 0, EBX = 3, ECX = 1, EDX = 2,
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ESI = 6, EDI = 7, EBP = 5, ESP = 4,
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RAX = 0, RBX = 3, RCX = 1, RDX = 2,
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RSI = 6, RDI = 7, RBP = 5, RSP = 4,
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R8 = 8, R9 = 9, R10 = 10,R11 = 11,
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R12 = 12,R13 = 13,R14 = 14,R15 = 15,
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AL = 0, BL = 3, CL = 1, DL = 2,
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AH = 4, BH = 7, CH = 5, DH = 6,
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AX = 0, BX = 3, CX = 1, DX = 2,
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SI = 6, DI = 7, BP = 5, SP = 4,
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XMM0=0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15,
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INVALID_REG = 0xFFFFFFFF
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};
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enum CCFlags
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{
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CC_O = 0,
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CC_NO = 1,
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CC_B = 2, CC_C = 2, CC_NAE = 2,
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CC_NB = 3, CC_NC = 3, CC_AE = 3,
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CC_Z = 4, CC_E = 4,
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CC_NZ = 5, CC_NE = 5,
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CC_BE = 6, CC_NA = 6,
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CC_NBE = 7, CC_A = 7,
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CC_S = 8,
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CC_NS = 9,
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CC_P = 0xA, CC_PE = 0xA,
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CC_NP = 0xB, CC_PO = 0xB,
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CC_L = 0xC, CC_NGE = 0xC,
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CC_NL = 0xD, CC_GE = 0xD,
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CC_LE = 0xE, CC_NG = 0xE,
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CC_NLE = 0xF, CC_G = 0xF
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};
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enum
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{
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NUMGPRs = 16,
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NUMXMMs = 16,
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};
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enum
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{
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SCALE_NONE = 0,
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SCALE_1 = 1,
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SCALE_2 = 2,
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SCALE_4 = 4,
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SCALE_8 = 8,
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SCALE_ATREG = 16,
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SCALE_RIP = 0xFF,
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SCALE_IMM8 = 0xF0,
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SCALE_IMM16 = 0xF1,
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SCALE_IMM32 = 0xF2,
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SCALE_IMM64 = 0xF3,
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};
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void SetCodePtr(u8 *ptr);
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void ReserveCodeSpace(int bytes);
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const u8 *AlignCode4();
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const u8 *AlignCode16();
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const u8 *AlignCodePage();
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const u8 *GetCodePtr();
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u8 *GetWritableCodePtr();
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enum NormalOp {
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nrmADD,
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nrmADC,
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nrmSUB,
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nrmSBB,
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nrmAND,
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nrmOR ,
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nrmXOR,
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nrmMOV,
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nrmTEST,
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nrmCMP,
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nrmXCHG,
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};
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// Make the generation routine examine which direction to go
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// probably has to be a static
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// RIP addressing does not benefit from micro op fusion on Core arch
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struct OpArg
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{
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OpArg() {} //dummy op arg, used for storage
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OpArg(u64 _offset, int _scale, X64Reg rmReg = RAX, X64Reg scaledReg = RAX)
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{
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operandReg = 0;
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scale = (u8)_scale;
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offsetOrBaseReg = (u8)rmReg;
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indexReg = (u8)scaledReg;
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//if scale == 0 never mind offseting
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offset = _offset;
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}
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void WriteRex(bool op64, int customOp = -1) const;
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void WriteRest(int extraBytes=0, X64Reg operandReg=(X64Reg)0xFF) const;
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void WriteSingleByteOp(u8 op, X64Reg operandReg, int bits);
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//This one is public - must be written to
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u64 offset; //use RIP-relative as much as possible - avoid 64-bit immediates at all costs
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u8 operandReg;
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void WriteNormalOp(bool toRM, NormalOp op, const OpArg &operand, int bits) const;
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bool IsImm() const {return scale == SCALE_IMM8 || scale == SCALE_IMM16 || scale == SCALE_IMM32 || scale == SCALE_IMM64;}
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bool IsSimpleReg() const {return scale == SCALE_NONE;}
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bool CanDoOpWith(OpArg &other) const
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{
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if (IsSimpleReg()) return true;
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if (!IsSimpleReg() && !other.IsSimpleReg() && !other.IsImm()) return false;
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return true;
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}
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int GetImmBits() const
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{
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switch (scale)
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{
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case SCALE_IMM8: return 8;
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case SCALE_IMM16: return 16;
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case SCALE_IMM32: return 32;
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case SCALE_IMM64: return 64;
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default: return -1;
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}
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}
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X64Reg GetSimpleReg() const
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{
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if (scale == SCALE_NONE)
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return (X64Reg)offsetOrBaseReg;
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else
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return INVALID_REG;
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}
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private:
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u8 scale;
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u8 offsetOrBaseReg;
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u8 indexReg;
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};
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inline OpArg M(void *ptr) {return OpArg((u64)ptr, (int)SCALE_RIP);}
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inline OpArg R(X64Reg value) {return OpArg(0, SCALE_NONE, value);}
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inline OpArg MatR(X64Reg value) {return OpArg(0, SCALE_ATREG, value);}
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inline OpArg MDisp(X64Reg value, int offset) {
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return OpArg((u32)offset, SCALE_ATREG, value); }
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inline OpArg MComplex(X64Reg base, X64Reg scaled, int scale, int offset)
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{
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return OpArg(offset, scale, base, scaled);
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}
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inline OpArg Imm8 (u8 imm) {return OpArg(imm, SCALE_IMM8);}
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inline OpArg Imm16(u16 imm) {return OpArg(imm, SCALE_IMM16);} //rarely used
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inline OpArg Imm32(u32 imm) {return OpArg(imm, SCALE_IMM32);}
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inline OpArg Imm64(u64 imm) {return OpArg(imm, SCALE_IMM64);}
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#ifdef _M_X64
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inline OpArg ImmPtr(void* imm) {return Imm64((u64)imm);}
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#else
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inline OpArg ImmPtr(void* imm) {return Imm32((u32)imm);}
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#endif
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void INT3();
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void NOP(int count = 1); //nop padding - TODO: fast nop slides, for amd and intel (check their manuals)
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void PAUSE();
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void RET();
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void STC();
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void CLC();
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void CMC();
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void PUSH(X64Reg reg);
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void POP(X64Reg reg);
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void PUSH(int bits, const OpArg ®);
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void POP(int bits, const OpArg ®);
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void PUSHF();
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void POPF();
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typedef const u8* JumpTarget;
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struct FixupBranch
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{
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u8 *ptr;
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int type; //0 = 8bit 1 = 32bit
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};
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FixupBranch J(bool force5bytes = false);
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void JMP(const u8 * addr, bool force5Bytes = false);
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void JMP(OpArg arg);
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void JMPptr(const OpArg &arg);
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void JMPself(); //infinite loop!
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void CALL(void *fnptr);
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void CALLptr(OpArg arg);
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FixupBranch J_CC(CCFlags conditionCode, bool force5bytes = false);
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void J_CC(CCFlags conditionCode, JumpTarget target);
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void J_CC(CCFlags conditionCode, const u8 * addr, bool force5Bytes = false);
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void SetJumpTarget(const FixupBranch &branch);
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//WARNING - INC and DEC slow on Intel Core, but not on AMD, since it creates
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//false flags dependencies because they only update a subset of the flags
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// ector - I hereby BAN inc and dec due to their horribleness :P
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// void INC(int bits, OpArg arg);
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// void DEC(int bits, OpArg arg);
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void SETcc(CCFlags flag, OpArg dest);
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// Note: CMOV brings small if any benefit on current cpus, unfortunately.
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void CMOVcc(int bits, X64Reg dest, OpArg src, CCFlags flag);
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void LFENCE();
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void MFENCE();
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void SFENCE();
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void BSF(int bits, X64Reg dest, OpArg src); //bottom bit to top bit
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void BSR(int bits, X64Reg dest, OpArg src); //top bit to bottom bit
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//These two can not be executed on early Intel 64-bit CPU:s, only on AMD!
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void LAHF(); // 3 cycle vector path
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void SAHF(); // direct path fast
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//Looking for one of these? It's BANNED!! Some instructions are slow on modern CPU
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//LOOP, LOOPNE, LOOPE, ENTER, LEAVE, XLAT, REP MOVSB/MOVSD, REP SCASD + other string instr.,
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//Actually REP MOVSD could be useful :P
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void MOVNTI(int bits, OpArg dest, X64Reg src);
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void MUL(int bits, OpArg src); //UNSIGNED
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void DIV(int bits, OpArg src);
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void IMUL(int bits, OpArg src); //SIGNED
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void IDIV(int bits, OpArg src);
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//TODO: alternate IMUL forms
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void NEG(int bits, OpArg src);
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void NOT(int bits, OpArg src);
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void ROL(int bits, OpArg dest, OpArg shift);
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void ROR(int bits, OpArg dest, OpArg shift);
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void RCL(int bits, OpArg dest, OpArg shift);
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void RCR(int bits, OpArg dest, OpArg shift);
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void SHL(int bits, OpArg dest, OpArg shift);
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void SHR(int bits, OpArg dest, OpArg shift);
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void SAR(int bits, OpArg dest, OpArg shift);
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void CWD(int bits = 16);
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inline void CDQ() {CWD(32);}
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inline void CQO() {CWD(64);}
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void CBW(int bits = 8);
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inline void CWDE() {CBW(16);}
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inline void CDQE() {CBW(32);}
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void LEA(int bits, X64Reg dest, OpArg src);
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enum PrefetchLevel
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{
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PF_NTA, //Non-temporal (data used once and only once)
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PF_T0, //All cache levels
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PF_T1, //Levels 2+ (aliased to T0 on AMD)
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PF_T2, //Levels 3+ (aliased to T0 on AMD)
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};
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void PREFETCH(PrefetchLevel level, OpArg arg);
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void ADD (int bits, const OpArg &a1, const OpArg &a2);
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void ADC (int bits, const OpArg &a1, const OpArg &a2);
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void SUB (int bits, const OpArg &a1, const OpArg &a2);
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void SBB (int bits, const OpArg &a1, const OpArg &a2);
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void AND (int bits, const OpArg &a1, const OpArg &a2);
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void OR (int bits, const OpArg &a1, const OpArg &a2);
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void XOR (int bits, const OpArg &a1, const OpArg &a2);
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void MOV (int bits, const OpArg &a1, const OpArg &a2);
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void TEST(int bits, const OpArg &a1, const OpArg &a2);
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void CMP (int bits, const OpArg &a1, const OpArg &a2);
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// XCHG is SLOW and should be avoided.
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//void XCHG(int bits, const OpArg &a1, const OpArg &a2);
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void XCHG_AHAL();
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void BSWAP(int bits, X64Reg reg);
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void MOVSX(int dbits, int sbits, X64Reg dest, OpArg src); //auto uses MOVSXD if necessary
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void MOVZX(int dbits, int sbits, X64Reg dest, OpArg src);
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enum SSECompare
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{
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EQ = 0,
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LT,
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LE,
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UNORD,
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NEQ,
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NLT,
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NLE,
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ORD,
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};
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//SSE2
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// WARNING - These two take 11-13 cycles and are VectorPath! (AMD64)
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void STMXCSR(OpArg memloc);
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void LDMXCSR(OpArg memloc);
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//Regular SSE instructions
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void ADDSS(X64Reg regOp, OpArg arg);
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void ADDSD(X64Reg regOp, OpArg arg);
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void SUBSS(X64Reg regOp, OpArg arg);
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void SUBSD(X64Reg regOp, OpArg arg);
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void CMPSS(X64Reg regOp, OpArg arg, u8 compare);
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void CMPSD(X64Reg regOp, OpArg arg, u8 compare);
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void ANDSS(X64Reg regOp, OpArg arg);
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void ANDSD(X64Reg regOp, OpArg arg);
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void ANDNSS(X64Reg regOp, OpArg arg);
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void ANDNSD(X64Reg regOp, OpArg arg);
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void ORSS(X64Reg regOp, OpArg arg);
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void ORSD(X64Reg regOp, OpArg arg);
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void XORSS(X64Reg regOp, OpArg arg);
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void XORSD(X64Reg regOp, OpArg arg);
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void MULSS(X64Reg regOp, OpArg arg);
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void MULSD(X64Reg regOp, OpArg arg);
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void DIVSS(X64Reg regOp, OpArg arg);
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void DIVSD(X64Reg regOp, OpArg arg);
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void MINSS(X64Reg regOp, OpArg arg);
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void MINSD(X64Reg regOp, OpArg arg);
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void MAXSS(X64Reg regOp, OpArg arg);
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void MAXSD(X64Reg regOp, OpArg arg);
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void SQRTSS(X64Reg regOp, OpArg arg);
|
||
|
|
void SQRTSD(X64Reg regOp, OpArg arg);
|
||
|
|
void RSQRTSS(X64Reg regOp, OpArg arg);
|
||
|
|
void RSQRTSD(X64Reg regOp, OpArg arg);
|
||
|
|
|
||
|
|
void COMISS(X64Reg regOp, OpArg arg);
|
||
|
|
void COMISD(X64Reg regOp, OpArg arg);
|
||
|
|
|
||
|
|
void ADDPS(X64Reg regOp, OpArg arg);
|
||
|
|
void ADDPD(X64Reg regOp, OpArg arg);
|
||
|
|
void SUBPS(X64Reg regOp, OpArg arg);
|
||
|
|
void SUBPD(X64Reg regOp, OpArg arg);
|
||
|
|
void CMPPS(X64Reg regOp, OpArg arg, u8 compare);
|
||
|
|
void CMPPD(X64Reg regOp, OpArg arg, u8 compare);
|
||
|
|
void ANDPS(X64Reg regOp, OpArg arg);
|
||
|
|
void ANDPD(X64Reg regOp, OpArg arg);
|
||
|
|
void ANDNPS(X64Reg regOp, OpArg arg);
|
||
|
|
void ANDNPD(X64Reg regOp, OpArg arg);
|
||
|
|
void ORPS(X64Reg regOp, OpArg arg);
|
||
|
|
void ORPD(X64Reg regOp, OpArg arg);
|
||
|
|
void XORPS(X64Reg regOp, OpArg arg);
|
||
|
|
void XORPD(X64Reg regOp, OpArg arg);
|
||
|
|
void MULPS(X64Reg regOp, OpArg arg);
|
||
|
|
void MULPD(X64Reg regOp, OpArg arg);
|
||
|
|
void DIVPS(X64Reg regOp, OpArg arg);
|
||
|
|
void DIVPD(X64Reg regOp, OpArg arg);
|
||
|
|
void MINPS(X64Reg regOp, OpArg arg);
|
||
|
|
void MINPD(X64Reg regOp, OpArg arg);
|
||
|
|
void MAXPS(X64Reg regOp, OpArg arg);
|
||
|
|
void MAXPD(X64Reg regOp, OpArg arg);
|
||
|
|
void SQRTPS(X64Reg regOp, OpArg arg);
|
||
|
|
void SQRTPD(X64Reg regOp, OpArg arg);
|
||
|
|
void RSQRTPS(X64Reg regOp, OpArg arg);
|
||
|
|
void RSQRTPD(X64Reg regOp, OpArg arg);
|
||
|
|
void SHUFPS(X64Reg regOp, OpArg arg, u8 shuffle);
|
||
|
|
void SHUFPD(X64Reg regOp, OpArg arg, u8 shuffle);
|
||
|
|
|
||
|
|
void MOVDDUP(X64Reg regOp, OpArg arg);
|
||
|
|
|
||
|
|
void COMISS(X64Reg regOp, OpArg arg);
|
||
|
|
void COMISD(X64Reg regOp, OpArg arg);
|
||
|
|
void UCOMISS(X64Reg regOp, OpArg arg);
|
||
|
|
void UCOMISD(X64Reg regOp, OpArg arg);
|
||
|
|
|
||
|
|
void MOVAPS(X64Reg regOp, OpArg arg);
|
||
|
|
void MOVAPD(X64Reg regOp, OpArg arg);
|
||
|
|
void MOVAPS(OpArg arg, X64Reg regOp);
|
||
|
|
void MOVAPD(OpArg arg, X64Reg regOp);
|
||
|
|
|
||
|
|
void MOVUPS(X64Reg regOp, OpArg arg);
|
||
|
|
void MOVUPD(X64Reg regOp, OpArg arg);
|
||
|
|
void MOVUPS(OpArg arg, X64Reg regOp);
|
||
|
|
void MOVUPD(OpArg arg, X64Reg regOp);
|
||
|
|
|
||
|
|
void MOVSS(X64Reg regOp, OpArg arg);
|
||
|
|
void MOVSD(X64Reg regOp, OpArg arg);
|
||
|
|
void MOVSS(OpArg arg, X64Reg regOp);
|
||
|
|
void MOVSD(OpArg arg, X64Reg regOp);
|
||
|
|
|
||
|
|
void MOVMSKPS(X64Reg dest, OpArg arg);
|
||
|
|
void MOVMSKPD(X64Reg dest, OpArg arg);
|
||
|
|
|
||
|
|
void MOVD_xmm(X64Reg dest, const OpArg &arg);
|
||
|
|
void MOVQ_xmm(X64Reg dest, const OpArg &arg);
|
||
|
|
void MOVD_xmm(const OpArg &arg, X64Reg src);
|
||
|
|
void MOVQ_xmm(const OpArg &arg, X64Reg src);
|
||
|
|
|
||
|
|
void MASKMOVDQU(X64Reg dest, X64Reg src);
|
||
|
|
void LDDQU(X64Reg dest, OpArg src);
|
||
|
|
|
||
|
|
void UNPCKLPD(X64Reg dest, OpArg src);
|
||
|
|
void UNPCKHPD(X64Reg dest, OpArg src);
|
||
|
|
|
||
|
|
void CVTPS2PD(X64Reg dest, OpArg src);
|
||
|
|
void CVTPD2PS(X64Reg dest, OpArg src);
|
||
|
|
void CVTSS2SD(X64Reg dest, OpArg src);
|
||
|
|
void CVTSD2SS(X64Reg dest, OpArg src);
|
||
|
|
void CVTSD2SI(X64Reg dest, OpArg src);
|
||
|
|
void CVTDQ2PD(X64Reg regOp, OpArg arg);
|
||
|
|
void CVTPD2DQ(X64Reg regOp, OpArg arg);
|
||
|
|
void CVTDQ2PS(X64Reg regOp, const OpArg &arg);
|
||
|
|
|
||
|
|
//Integer SSE instructions
|
||
|
|
void PACKSSDW(X64Reg dest, OpArg arg);
|
||
|
|
void PACKSSWB(X64Reg dest, OpArg arg);
|
||
|
|
//void PACKUSDW(X64Reg dest, OpArg arg);
|
||
|
|
void PACKUSWB(X64Reg dest, OpArg arg);
|
||
|
|
|
||
|
|
void PUNPCKLBW(X64Reg dest, const OpArg &arg);
|
||
|
|
void PUNPCKLWD(X64Reg dest, const OpArg &arg);
|
||
|
|
void PUNPCKLDQ(X64Reg dest, const OpArg &arg);
|
||
|
|
|
||
|
|
void PSRAD(X64Reg dest, int shift);
|
||
|
|
|
||
|
|
void PAND(X64Reg dest, OpArg arg);
|
||
|
|
void PANDN(X64Reg dest, OpArg arg);
|
||
|
|
void PXOR(X64Reg dest, OpArg arg);
|
||
|
|
void POR(X64Reg dest, OpArg arg);
|
||
|
|
|
||
|
|
void PADDB(X64Reg dest, OpArg arg);
|
||
|
|
void PADDW(X64Reg dest, OpArg arg);
|
||
|
|
void PADDD(X64Reg dest, OpArg arg);
|
||
|
|
void PADDQ(X64Reg dest, OpArg arg);
|
||
|
|
|
||
|
|
void PADDSB(X64Reg dest, OpArg arg);
|
||
|
|
void PADDSW(X64Reg dest, OpArg arg);
|
||
|
|
void PADDUSB(X64Reg dest, OpArg arg);
|
||
|
|
void PADDUSW(X64Reg dest, OpArg arg);
|
||
|
|
|
||
|
|
void PSUBB(X64Reg dest, OpArg arg);
|
||
|
|
void PSUBW(X64Reg dest, OpArg arg);
|
||
|
|
void PSUBD(X64Reg dest, OpArg arg);
|
||
|
|
void PSUBQ(X64Reg dest, OpArg arg);
|
||
|
|
|
||
|
|
void PSUBSB(X64Reg dest, OpArg arg);
|
||
|
|
void PSUBSW(X64Reg dest, OpArg arg);
|
||
|
|
void PSUBUSB(X64Reg dest, OpArg arg);
|
||
|
|
void PSUBUSW(X64Reg dest, OpArg arg);
|
||
|
|
|
||
|
|
void PAVGB(X64Reg dest, OpArg arg);
|
||
|
|
void PAVGW(X64Reg dest, OpArg arg);
|
||
|
|
|
||
|
|
void PCMPEQB(X64Reg dest, OpArg arg);
|
||
|
|
void PCMPEQW(X64Reg dest, OpArg arg);
|
||
|
|
void PCMPEQD(X64Reg dest, OpArg arg);
|
||
|
|
|
||
|
|
void PCMPGTB(X64Reg dest, OpArg arg);
|
||
|
|
void PCMPGTW(X64Reg dest, OpArg arg);
|
||
|
|
void PCMPGTD(X64Reg dest, OpArg arg);
|
||
|
|
|
||
|
|
void PEXTRW(X64Reg dest, OpArg arg, u8 subreg);
|
||
|
|
void PINSRW(X64Reg dest, OpArg arg, u8 subreg);
|
||
|
|
|
||
|
|
void PMADDWD(X64Reg dest, OpArg arg);
|
||
|
|
void PSADBW(X64Reg dest, OpArg arg);
|
||
|
|
|
||
|
|
void PMAXSW(X64Reg dest, OpArg arg);
|
||
|
|
void PMAXUB(X64Reg dest, OpArg arg);
|
||
|
|
void PMINSW(X64Reg dest, OpArg arg);
|
||
|
|
void PMINUB(X64Reg dest, OpArg arg);
|
||
|
|
|
||
|
|
void PMOVMSKB(X64Reg dest, OpArg arg);
|
||
|
|
|
||
|
|
|
||
|
|
namespace Util
|
||
|
|
{
|
||
|
|
// Sets up a __cdecl function.
|
||
|
|
// Only x64 really needs the parameter.
|
||
|
|
void EmitPrologue(int maxCallParams);
|
||
|
|
void EmitEpilogue(int maxCallParams);
|
||
|
|
}
|
||
|
|
|
||
|
|
void CallCdeclFunction3(void* fnptr, u32 arg0, u32 arg1, u32 arg2);
|
||
|
|
void CallCdeclFunction4(void* fnptr, u32 arg0, u32 arg1, u32 arg2, u32 arg3);
|
||
|
|
void CallCdeclFunction5(void* fnptr, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4);
|
||
|
|
void CallCdeclFunction6(void* fnptr, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4, u32 arg5);
|
||
|
|
|
||
|
|
#if defined(_M_IX86) || !defined(_WIN32)
|
||
|
|
|
||
|
|
#define CallCdeclFunction3_I(a,b,c,d) CallCdeclFunction3((void *)(a), (b), (c), (d))
|
||
|
|
#define CallCdeclFunction4_I(a,b,c,d,e) CallCdeclFunction4((void *)(a), (b), (c), (d), (e))
|
||
|
|
#define CallCdeclFunction5_I(a,b,c,d,e,f) CallCdeclFunction5((void *)(a), (b), (c), (d), (e), (f))
|
||
|
|
#define CallCdeclFunction6_I(a,b,c,d,e,f,g) CallCdeclFunction6((void *)(a), (b), (c), (d), (e), (f), (g))
|
||
|
|
|
||
|
|
#define DECLARE_IMPORT(x)
|
||
|
|
|
||
|
|
#else
|
||
|
|
|
||
|
|
// Comments from VertexLoader.cpp about these horrors:
|
||
|
|
|
||
|
|
// This is a horrible hack that is necessary in 64-bit mode because Opengl32.dll is based way, way above the 32-bit
|
||
|
|
// address space that is within reach of a CALL, and just doing &fn gives us these high uncallable addresses. So we
|
||
|
|
// want to grab the function pointers from the import table instead.
|
||
|
|
|
||
|
|
void ___CallCdeclImport3(void* impptr, u32 arg0, u32 arg1, u32 arg2);
|
||
|
|
void ___CallCdeclImport4(void* impptr, u32 arg0, u32 arg1, u32 arg2, u32 arg3);
|
||
|
|
void ___CallCdeclImport5(void* impptr, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4);
|
||
|
|
void ___CallCdeclImport6(void* impptr, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4, u32 arg5);
|
||
|
|
|
||
|
|
#define CallCdeclFunction3_I(a,b,c,d) ___CallCdeclImport3(&__imp_##a,b,c,d)
|
||
|
|
#define CallCdeclFunction4_I(a,b,c,d,e) ___CallCdeclImport4(&__imp_##a,b,c,d,e)
|
||
|
|
#define CallCdeclFunction5_I(a,b,c,d,e,f) ___CallCdeclImport5(&__imp_##a,b,c,d,e,f)
|
||
|
|
#define CallCdeclFunction6_I(a,b,c,d,e,f,g) ___CallCdeclImport6(&__imp_##a,b,c,d,e,f,g)
|
||
|
|
|
||
|
|
#define DECLARE_IMPORT(x) extern "C" void *__imp_##x
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|