From ed419e6a3a2476a36fbc6130356ed33d5f6d18c2 Mon Sep 17 00:00:00 2001 From: mtabachenko Date: Sat, 24 Apr 2010 13:37:29 +0000 Subject: [PATCH] core: - a lot work on fix CPU emulation but not finished yet. Report to bugtracker if it break something. --- desmume/src/arm_instructions.cpp | 1996 ++++++++++------------------ desmume/src/armcpu.h | 44 + desmume/src/common.cpp | 14 - desmume/src/common.h | 27 +- desmume/src/thumb_instructions.cpp | 65 +- 5 files changed, 819 insertions(+), 1327 deletions(-) diff --git a/desmume/src/arm_instructions.cpp b/desmume/src/arm_instructions.cpp index 28c674d8d..9c9837467 100644 --- a/desmume/src/arm_instructions.cpp +++ b/desmume/src/arm_instructions.cpp @@ -27,6 +27,7 @@ // - Check LDMxx2/STMxx2 (those opcodes that act on User mode registers instead // of current ones) +//#define UNTESTEDOPCODEDEBUG #include "cp15.h" #include "debug.h" #include "MMU.h" @@ -43,7 +44,7 @@ //----------------------------------------------------------------------------- #define LSL_IMM \ - shift_op = cpu->R[REG_POS(i,0)]<<((i>>7)&0x1F); + u32 shift_op = cpu->R[REG_POS(i,0)]<<((i>>7)&0x1F); #define S_LSL_IMM \ u32 shift_op = ((i>>7)&0x1F); \ @@ -53,7 +54,7 @@ else \ { \ c = BIT_N(cpu->R[REG_POS(i,0)], 32-shift_op); \ - shift_op = cpu->R[REG_POS(i,0)]<<((i>>7)&0x1F); \ + shift_op = cpu->R[REG_POS(i,0)]<>7)&0x1F); \ + u32 shift_op = ((i>>7)&0x1F); \ if(shift_op!=0) \ shift_op = cpu->R[REG_POS(i,0)]>>shift_op; @@ -137,11 +138,11 @@ } #define ASR_IMM \ - shift_op = ((i>>7)&0x1F); \ + u32 shift_op = ((i>>7)&0x1F); \ if(shift_op==0) \ shift_op=BIT31(cpu->R[REG_POS(i,0)])*0xFFFFFFFF; \ else \ - shift_op = (u32)(((s32)(cpu->R[REG_POS(i,0)]))>>shift_op); + shift_op = (u32)((s32)cpu->R[REG_POS(i,0)]>>shift_op); #define S_ASR_IMM \ u32 shift_op = ((i>>7)&0x1F); \ @@ -154,7 +155,7 @@ else \ { \ c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1); \ - shift_op = (u32)(((s32)(cpu->R[REG_POS(i,0)]))>>shift_op); \ + shift_op = (u32)((s32)cpu->R[REG_POS(i,0)]>>shift_op); \ } #define ASR_REG \ @@ -163,7 +164,7 @@ shift_op=cpu->R[REG_POS(i,0)]; \ else \ if(shift_op<32) \ - shift_op = (u32)(((s32)(cpu->R[REG_POS(i,0)]))>>shift_op); \ + shift_op = (u32)((s32)cpu->R[REG_POS(i,0)]>>shift_op); \ else \ shift_op=BIT31(cpu->R[REG_POS(i,0)])*0xFFFFFFFF; @@ -176,7 +177,7 @@ if(shift_op<32) \ { \ c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1); \ - shift_op = (u32)(((s32)(cpu->R[REG_POS(i,0)]))>>shift_op); \ + shift_op = (u32)((s32)cpu->R[REG_POS(i,0)]>>shift_op); \ } \ else \ { \ @@ -185,11 +186,10 @@ } #define ROR_IMM \ - shift_op = ((i>>7)&0x1F); \ + u32 shift_op = ((i>>7)&0x1F); \ if(shift_op==0) \ { \ - u32 tmp = cpu->CPSR.bits.C; \ - shift_op = (tmp<<31)|(cpu->R[REG_POS(i,0)]>>1); \ + shift_op = ((u32)cpu->CPSR.bits.C<<31)|(cpu->R[REG_POS(i,0)]>>1); \ } \ else \ shift_op = ROR(cpu->R[REG_POS(i,0)],shift_op); @@ -199,8 +199,7 @@ u32 c = cpu->CPSR.bits.C; \ if(shift_op==0) \ { \ - u32 tmp = cpu->CPSR.bits.C; \ - shift_op = (tmp<<31)|(cpu->R[REG_POS(i,0)]>>1); \ + shift_op = ((u32)cpu->CPSR.bits.C<<31)|(cpu->R[REG_POS(i,0)]>>1); \ c = BIT0(cpu->R[REG_POS(i,0)]); \ } \ else \ @@ -232,7 +231,7 @@ else \ { \ c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1); \ - shift_op = ROR(cpu->R[REG_POS(i,0)],(shift_op&0x1F)); \ + shift_op = ROR(cpu->R[REG_POS(i,0)],shift_op); \ } \ } @@ -255,9 +254,8 @@ TEMPLATE static u32 FASTCALL OP_UND(const u32 i) { - LOG("Undefined instruction: %08X from %08X \n", cpu->instruction, cpu->instruct_adr); + INFO("ARM%c: Undefined instruction: 0x%08X (%s) PC=0x%08X. Stopped!!!\n", PROCNUM?'7':'9', cpu->instruction, decodeIntruction(false, cpu->instruction), cpu->instruct_adr); emu_halt(); - LOG("Stopped (OP_UND) \n"); return 1; } @@ -276,19 +274,17 @@ TEMPLATE static u32 FASTCALL OP_UND(const u32 i) return a; #define OP_ANDS(a, b) \ + cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] & shift_op; \ if(REG_POS(i,12)==15) \ { \ - Status_Reg SPSR; \ - cpu->R[15] = cpu->R[REG_POS(i,16)] & shift_op; \ - SPSR = cpu->SPSR; \ + Status_Reg SPSR = cpu->SPSR; \ armcpu_switchMode(cpu, SPSR.bits.mode); \ cpu->CPSR=SPSR; \ cpu->changeCPSR(); \ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1)); \ + cpu->R[15] &= (0xFFFFFFFC|(((u32)cpu->CPSR.bits.T)<<1)); \ cpu->next_instruction = cpu->R[15]; \ return b; \ } \ - cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] & shift_op; \ cpu->CPSR.bits.C = c; \ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \ cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \ @@ -296,7 +292,6 @@ TEMPLATE static u32 FASTCALL OP_UND(const u32 i) TEMPLATE static u32 FASTCALL OP_AND_LSL_IMM(const u32 i) { - u32 shift_op; LSL_IMM; OP_AND(1, 3); } @@ -309,7 +304,6 @@ TEMPLATE static u32 FASTCALL OP_AND_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_AND_LSR_IMM(const u32 i) { - u32 shift_op; LSR_IMM; OP_AND(1, 3); } @@ -322,7 +316,6 @@ TEMPLATE static u32 FASTCALL OP_AND_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_AND_ASR_IMM(const u32 i) { - u32 shift_op; ASR_IMM; OP_AND(1, 3); } @@ -335,7 +328,6 @@ TEMPLATE static u32 FASTCALL OP_AND_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_AND_ROR_IMM(const u32 i) { - u32 shift_op; ROR_IMM; OP_AND(1, 3); } @@ -428,7 +420,7 @@ TEMPLATE static u32 FASTCALL OP_AND_S_IMM_VAL(const u32 i) armcpu_switchMode(cpu, SPSR.bits.mode); \ cpu->CPSR=SPSR; \ cpu->changeCPSR(); \ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1)); \ + cpu->R[15] &= (0xFFFFFFFC|(((u32)cpu->CPSR.bits.T)<<1)); \ cpu->next_instruction = cpu->R[15]; \ return b; \ } \ @@ -439,7 +431,6 @@ TEMPLATE static u32 FASTCALL OP_AND_S_IMM_VAL(const u32 i) TEMPLATE static u32 FASTCALL OP_EOR_LSL_IMM(const u32 i) { - u32 shift_op; LSL_IMM; OP_EOR(1, 3); } @@ -452,7 +443,6 @@ TEMPLATE static u32 FASTCALL OP_EOR_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_EOR_LSR_IMM(const u32 i) { - u32 shift_op; LSR_IMM; OP_EOR(1, 3); } @@ -465,7 +455,6 @@ TEMPLATE static u32 FASTCALL OP_EOR_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_EOR_ASR_IMM(const u32 i) { - u32 shift_op; ASR_IMM; OP_EOR(1, 3); } @@ -478,7 +467,6 @@ TEMPLATE static u32 FASTCALL OP_EOR_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_EOR_ROR_IMM(const u32 i) { - u32 shift_op; ROR_IMM; OP_EOR(1, 3); } @@ -571,19 +559,18 @@ TEMPLATE static u32 FASTCALL OP_EOR_S_IMM_VAL(const u32 i) armcpu_switchMode(cpu, SPSR.bits.mode); \ cpu->CPSR=SPSR; \ cpu->changeCPSR(); \ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1)); \ + cpu->R[15] &= (0xFFFFFFFC|(((u32)cpu->CPSR.bits.T)<<1)); \ cpu->next_instruction = cpu->R[15]; \ return b; \ } \ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \ cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \ - cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]); \ - cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]); \ + cpu->CPSR.bits.C = !BorrowFrom(v, shift_op); \ + cpu->CPSR.bits.V = OverflowFromSUB(cpu->R[REG_POS(i,12)], v, shift_op); \ return a; TEMPLATE static u32 FASTCALL OP_SUB_LSL_IMM(const u32 i) { - u32 shift_op; LSL_IMM; OP_SUB(1, 3); } @@ -596,7 +583,6 @@ TEMPLATE static u32 FASTCALL OP_SUB_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_SUB_LSR_IMM(const u32 i) { - u32 shift_op; LSR_IMM; OP_SUB(1, 3); } @@ -609,7 +595,6 @@ TEMPLATE static u32 FASTCALL OP_SUB_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_SUB_ASR_IMM(const u32 i) { - u32 shift_op; ASR_IMM; OP_SUB(1, 3); } @@ -622,7 +607,6 @@ TEMPLATE static u32 FASTCALL OP_SUB_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_SUB_ROR_IMM(const u32 i) { - u32 shift_op; ROR_IMM; OP_SUB(1, 3); } @@ -643,7 +627,6 @@ TEMPLATE static u32 FASTCALL OP_SUB_IMM_VAL(const u32 i) TEMPLATE static u32 FASTCALL OP_SUB_S_LSL_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; LSL_IMM; OP_SUBS(1, 3); } @@ -658,7 +641,6 @@ TEMPLATE static u32 FASTCALL OP_SUB_S_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_SUB_S_LSR_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; LSR_IMM; OP_SUBS(1, 3); } @@ -673,7 +655,6 @@ TEMPLATE static u32 FASTCALL OP_SUB_S_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_SUB_S_ASR_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; ASR_IMM; OP_SUBS(1, 3); } @@ -688,7 +669,6 @@ TEMPLATE static u32 FASTCALL OP_SUB_S_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_SUB_S_ROR_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; ROR_IMM; OP_SUBS(1, 3); } @@ -728,19 +708,18 @@ TEMPLATE static u32 FASTCALL OP_SUB_S_IMM_VAL(const u32 i) armcpu_switchMode(cpu, SPSR.bits.mode); \ cpu->CPSR=SPSR; \ cpu->changeCPSR(); \ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1)); \ + cpu->R[15] &= (0xFFFFFFFC|(((u32)cpu->CPSR.bits.T)<<1)); \ cpu->next_instruction = cpu->R[15]; \ return b; \ } \ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \ cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \ - cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(shift_op, v, cpu->R[REG_POS(i,12)]); \ - cpu->CPSR.bits.V = SIGNED_UNDERFLOW(shift_op, v, cpu->R[REG_POS(i,12)]); \ + cpu->CPSR.bits.C = !BorrowFrom(shift_op, v); \ + cpu->CPSR.bits.V = OverflowFromSUB(cpu->R[REG_POS(i,12)], shift_op, v); \ return a; TEMPLATE static u32 FASTCALL OP_RSB_LSL_IMM(const u32 i) { - u32 shift_op; LSL_IMM; OP_RSB(1, 3); } @@ -753,7 +732,6 @@ TEMPLATE static u32 FASTCALL OP_RSB_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_RSB_LSR_IMM(const u32 i) { - u32 shift_op; LSR_IMM; OP_RSB(1, 3); } @@ -766,7 +744,6 @@ TEMPLATE static u32 FASTCALL OP_RSB_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_RSB_ASR_IMM(const u32 i) { - u32 shift_op; ASR_IMM; OP_RSB(1, 3); } @@ -779,7 +756,6 @@ TEMPLATE static u32 FASTCALL OP_RSB_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_RSB_ROR_IMM(const u32 i) { - u32 shift_op; ROR_IMM; OP_RSB(1, 3); } @@ -799,7 +775,6 @@ TEMPLATE static u32 FASTCALL OP_RSB_IMM_VAL(const u32 i) TEMPLATE static u32 FASTCALL OP_RSB_S_LSL_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; LSL_IMM; OP_RSBS(1, 3); } @@ -815,7 +790,6 @@ TEMPLATE static u32 FASTCALL OP_RSB_S_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_RSB_S_LSR_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; LSR_IMM; OP_RSBS(1, 3); } @@ -830,7 +804,6 @@ TEMPLATE static u32 FASTCALL OP_RSB_S_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_RSB_S_ASR_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; ASR_IMM; OP_RSBS(1, 3); } @@ -845,7 +818,6 @@ TEMPLATE static u32 FASTCALL OP_RSB_S_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_RSB_S_ROR_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; ROR_IMM; OP_RSBS(1, 3); } @@ -885,19 +857,18 @@ TEMPLATE static u32 FASTCALL OP_RSB_S_IMM_VAL(const u32 i) armcpu_switchMode(cpu, SPSR.bits.mode); \ cpu->CPSR=SPSR; \ cpu->changeCPSR(); \ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1)); \ + cpu->R[15] &= (0xFFFFFFFC|(((u32)cpu->CPSR.bits.T)<<1)); \ cpu->next_instruction = cpu->R[15]; \ return b; \ } \ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \ cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \ - cpu->CPSR.bits.C = UNSIGNED_OVERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]); \ - cpu->CPSR.bits.V = SIGNED_OVERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]); \ + cpu->CPSR.bits.C = CarryFrom(v, shift_op); \ + cpu->CPSR.bits.V = OverflowFromADD(cpu->R[REG_POS(i,12)], v, shift_op); \ return a; TEMPLATE static u32 FASTCALL OP_ADD_LSL_IMM(const u32 i) { - u32 shift_op; LSL_IMM; OP_ADD(1, 3); } @@ -910,7 +881,6 @@ TEMPLATE static u32 FASTCALL OP_ADD_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_ADD_LSR_IMM(const u32 i) { - u32 shift_op; LSR_IMM; OP_ADD(1, 3); } @@ -923,7 +893,6 @@ TEMPLATE static u32 FASTCALL OP_ADD_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_ADD_ASR_IMM(const u32 i) { - u32 shift_op; ASR_IMM; OP_ADD(1, 3); } @@ -936,7 +905,6 @@ TEMPLATE static u32 FASTCALL OP_ADD_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_ADD_ROR_IMM(const u32 i) { - u32 shift_op; ROR_IMM; OP_ADD(1, 3); } @@ -957,7 +925,6 @@ TEMPLATE static u32 FASTCALL OP_ADD_IMM_VAL(const u32 i) TEMPLATE static u32 FASTCALL OP_ADD_S_LSL_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; LSL_IMM; OP_ADDS(1, 3); } @@ -972,7 +939,6 @@ TEMPLATE static u32 FASTCALL OP_ADD_S_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_ADD_S_LSR_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; LSR_IMM; OP_ADDS(1, 3); } @@ -987,7 +953,6 @@ TEMPLATE static u32 FASTCALL OP_ADD_S_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_ADD_S_ASR_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; ASR_IMM; OP_ADDS(1, 3); } @@ -1002,7 +967,6 @@ TEMPLATE static u32 FASTCALL OP_ADD_S_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_ADD_S_ROR_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; ROR_IMM; OP_ADDS(1, 3); } @@ -1024,7 +988,6 @@ TEMPLATE static u32 FASTCALL OP_ADD_S_IMM_VAL(const u32 i) //----------------------------------------------------------------------------- // ADC / ADCS //----------------------------------------------------------------------------- - #define OP_ADC(a, b) \ cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] + shift_op + cpu->CPSR.bits.C; \ if(REG_POS(i,12)==15) \ @@ -1036,28 +999,35 @@ TEMPLATE static u32 FASTCALL OP_ADD_S_IMM_VAL(const u32 i) #define OP_ADCS(a, b) \ { \ - u32 tmp = shift_op + cpu->CPSR.bits.C; \ - cpu->R[REG_POS(i,12)] = v + tmp; \ if(REG_POS(i,12)==15) \ { \ + cpu->R[REG_POS(i,12)] = v + shift_op + cpu->CPSR.bits.C; \ Status_Reg SPSR = cpu->SPSR; \ armcpu_switchMode(cpu, SPSR.bits.mode); \ cpu->CPSR=SPSR; \ cpu->changeCPSR(); \ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1)); \ + cpu->R[15] &= (0xFFFFFFFC|(((u32)cpu->CPSR.bits.T)<<1)); \ cpu->next_instruction = cpu->R[15]; \ return b; \ } \ + if (!cpu->CPSR.bits.C) \ + { \ + cpu->R[REG_POS(i,12)] = v + shift_op; \ + cpu->CPSR.bits.C = cpu->R[REG_POS(i,12)] < v; \ + } \ + else \ + { \ + cpu->R[REG_POS(i,12)] = v + shift_op + 1; \ + cpu->CPSR.bits.C = cpu->R[REG_POS(i,12)] <= v; \ + } \ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \ cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \ - cpu->CPSR.bits.C = UNSIGNED_OVERFLOW(shift_op, (u32) cpu->CPSR.bits.C, tmp) | UNSIGNED_OVERFLOW(v, tmp, cpu->R[REG_POS(i,12)]); \ - cpu->CPSR.bits.V = SIGNED_OVERFLOW(shift_op, (u32) cpu->CPSR.bits.C, tmp) | SIGNED_OVERFLOW(v, tmp, cpu->R[REG_POS(i,12)]); \ + cpu->CPSR.bits.V = (v ^ shift_op ^ -1) & (v ^ cpu->R[REG_POS(i, 12)]) != 0;\ return a; \ } TEMPLATE static u32 FASTCALL OP_ADC_LSL_IMM(const u32 i) { - u32 shift_op; LSL_IMM; OP_ADC(1, 3); } @@ -1070,7 +1040,6 @@ TEMPLATE static u32 FASTCALL OP_ADC_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_ADC_LSR_IMM(const u32 i) { - u32 shift_op; LSR_IMM; OP_ADC(1, 3); } @@ -1083,7 +1052,6 @@ TEMPLATE static u32 FASTCALL OP_ADC_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_ADC_ASR_IMM(const u32 i) { - u32 shift_op; ASR_IMM; OP_ADC(1, 3); } @@ -1096,7 +1064,6 @@ TEMPLATE static u32 FASTCALL OP_ADC_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_ADC_ROR_IMM(const u32 i) { - u32 shift_op; ROR_IMM; OP_ADC(1, 3); } @@ -1117,7 +1084,6 @@ TEMPLATE static u32 FASTCALL OP_ADC_IMM_VAL(const u32 i) TEMPLATE static u32 FASTCALL OP_ADC_S_LSL_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; LSL_IMM; OP_ADCS(1, 3); } @@ -1132,7 +1098,6 @@ TEMPLATE static u32 FASTCALL OP_ADC_S_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_ADC_S_LSR_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; LSR_IMM; OP_ADCS(1, 3); } @@ -1147,7 +1112,6 @@ TEMPLATE static u32 FASTCALL OP_ADC_S_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_ADC_S_ASR_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; ASR_IMM; OP_ADCS(1, 3); } @@ -1162,7 +1126,6 @@ TEMPLATE static u32 FASTCALL OP_ADC_S_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_ADC_S_ROR_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; ROR_IMM; OP_ADCS(1, 3); } @@ -1186,7 +1149,7 @@ TEMPLATE static u32 FASTCALL OP_ADC_S_IMM_VAL(const u32 i) //----------------------------------------------------------------------------- #define OP_SBC(a, b) \ - cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] - shift_op + cpu->CPSR.bits.C - 1; \ + cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] - shift_op - !cpu->CPSR.bits.C; \ if(REG_POS(i,12)==15) \ { \ cpu->next_instruction = cpu->R[15]; \ @@ -1194,31 +1157,37 @@ TEMPLATE static u32 FASTCALL OP_ADC_S_IMM_VAL(const u32 i) } \ return a; -//zero 14-feb-2009 - reverting flag logic to fix zoning bug in ff4 #define OP_SBCS(a, b) \ { \ - u32 tmp = v + cpu->CPSR.bits.C - 1; \ - cpu->R[REG_POS(i,12)] = tmp - shift_op; \ if(REG_POS(i,12)==15) \ { \ + cpu->R[REG_POS(i,12)] = v - shift_op - !cpu->CPSR.bits.C; \ Status_Reg SPSR = cpu->SPSR; \ armcpu_switchMode(cpu, SPSR.bits.mode); \ cpu->CPSR=SPSR; \ cpu->changeCPSR(); \ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1)); \ + cpu->R[15] &= (0xFFFFFFFC|(((u32)cpu->CPSR.bits.T)<<1)); \ cpu->next_instruction = cpu->R[15]; \ return b; \ } \ + if (!cpu->CPSR.bits.C) \ + { \ + cpu->R[REG_POS(i,12)] = v - shift_op - 1; \ + cpu->CPSR.bits.C = v > shift_op; \ + } \ + else \ + { \ + cpu->R[REG_POS(i,12)] = v - shift_op; \ + cpu->CPSR.bits.C = v >= shift_op; \ + } \ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \ cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \ - cpu->CPSR.bits.C = (!UNSIGNED_UNDERFLOW(v, (u32)(!cpu->CPSR.bits.C), tmp)) & (!UNSIGNED_UNDERFLOW(tmp, shift_op, cpu->R[REG_POS(i,12)])); \ - cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, (u32)(!cpu->CPSR.bits.C), tmp) | SIGNED_UNDERFLOW(tmp, shift_op, cpu->R[REG_POS(i,12)]); \ + cpu->CPSR.bits.V = ((v ^ shift_op) & (v ^ cpu->R[REG_POS(i, 12)])) != 0; \ return a; \ } TEMPLATE static u32 FASTCALL OP_SBC_LSL_IMM(const u32 i) { - u32 shift_op; LSL_IMM; OP_SBC(1, 3); } @@ -1231,7 +1200,6 @@ TEMPLATE static u32 FASTCALL OP_SBC_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_SBC_LSR_IMM(const u32 i) { - u32 shift_op; LSR_IMM; OP_SBC(1, 3); } @@ -1244,7 +1212,6 @@ TEMPLATE static u32 FASTCALL OP_SBC_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_SBC_ASR_IMM(const u32 i) { - u32 shift_op; ASR_IMM; OP_SBC(1, 3); } @@ -1257,7 +1224,6 @@ TEMPLATE static u32 FASTCALL OP_SBC_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_SBC_ROR_IMM(const u32 i) { - u32 shift_op; ROR_IMM; OP_SBC(1, 3); } @@ -1278,7 +1244,6 @@ TEMPLATE static u32 FASTCALL OP_SBC_IMM_VAL(const u32 i) TEMPLATE static u32 FASTCALL OP_SBC_S_LSL_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; LSL_IMM; OP_SBCS(1, 3); } @@ -1293,7 +1258,6 @@ TEMPLATE static u32 FASTCALL OP_SBC_S_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_SBC_S_LSR_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; LSR_IMM; OP_SBCS(1, 3); } @@ -1308,7 +1272,6 @@ TEMPLATE static u32 FASTCALL OP_SBC_S_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_SBC_S_ASR_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; ASR_IMM; OP_SBCS(1, 3); } @@ -1323,7 +1286,6 @@ TEMPLATE static u32 FASTCALL OP_SBC_S_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_SBC_S_ROR_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; ROR_IMM; OP_SBCS(1, 3); } @@ -1355,31 +1317,37 @@ TEMPLATE static u32 FASTCALL OP_SBC_S_IMM_VAL(const u32 i) } \ return a; -//zero 14-feb-2009 - reverting flag logic to fix zoning bug in ff4 -#define OP_RSCS(a,b) \ +#define OP_RSCS(a, b) \ { \ - u32 tmp = shift_op + cpu->CPSR.bits.C - 1; \ - cpu->R[REG_POS(i,12)] = tmp - v; \ if(REG_POS(i,12)==15) \ { \ + cpu->R[REG_POS(i,12)] = shift_op - v - !cpu->CPSR.bits.C; \ Status_Reg SPSR = cpu->SPSR; \ armcpu_switchMode(cpu, SPSR.bits.mode); \ cpu->CPSR=SPSR; \ cpu->changeCPSR(); \ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1)); \ + cpu->R[15] &= (0xFFFFFFFC|(((u32)cpu->CPSR.bits.T)<<1)); \ cpu->next_instruction = cpu->R[15]; \ return b; \ - } \ + } \ + if (!cpu->CPSR.bits.C) \ + { \ + cpu->R[REG_POS(i,12)] = shift_op - v - 1; \ + cpu->CPSR.bits.C = shift_op > v; \ + } \ + else \ + { \ + cpu->R[REG_POS(i,12)] = shift_op - v; \ + cpu->CPSR.bits.C = shift_op >= v; \ + } \ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \ cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \ - cpu->CPSR.bits.C = (!UNSIGNED_UNDERFLOW(shift_op, (u32)(!cpu->CPSR.bits.C), (u32)tmp)) & (!UNSIGNED_UNDERFLOW(tmp, v, cpu->R[REG_POS(i,12)])); \ - cpu->CPSR.bits.V = SIGNED_UNDERFLOW(shift_op, (u32)(!cpu->CPSR.bits.C), (u32)tmp) | SIGNED_UNDERFLOW(tmp, v, cpu->R[REG_POS(i,12)]); \ + cpu->CPSR.bits.V = ((shift_op ^ shift_op) & (shift_op ^ cpu->R[REG_POS(i, 12)])) != 0; \ return a; \ } TEMPLATE static u32 FASTCALL OP_RSC_LSL_IMM(const u32 i) { - u32 shift_op; LSL_IMM; OP_RSC(1, 3); } @@ -1392,7 +1360,6 @@ TEMPLATE static u32 FASTCALL OP_RSC_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_RSC_LSR_IMM(const u32 i) { - u32 shift_op; LSR_IMM; OP_RSC(1, 3); } @@ -1405,7 +1372,6 @@ TEMPLATE static u32 FASTCALL OP_RSC_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_RSC_ASR_IMM(const u32 i) { - u32 shift_op; ASR_IMM; OP_RSC(1, 3); } @@ -1418,7 +1384,6 @@ TEMPLATE static u32 FASTCALL OP_RSC_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_RSC_ROR_IMM(const u32 i) { - u32 shift_op; ROR_IMM; OP_RSC(1, 3); } @@ -1439,7 +1404,6 @@ TEMPLATE static u32 FASTCALL OP_RSC_IMM_VAL(const u32 i) TEMPLATE static u32 FASTCALL OP_RSC_S_LSL_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; LSL_IMM; OP_RSCS(1,3); } @@ -1454,7 +1418,6 @@ TEMPLATE static u32 FASTCALL OP_RSC_S_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_RSC_S_LSR_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; LSR_IMM; OP_RSCS(1,3); } @@ -1469,7 +1432,6 @@ TEMPLATE static u32 FASTCALL OP_RSC_S_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_RSC_S_ASR_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; ASR_IMM; OP_RSCS(1,3); } @@ -1484,7 +1446,6 @@ TEMPLATE static u32 FASTCALL OP_RSC_S_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_RSC_S_ROR_IMM(const u32 i) { u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; ROR_IMM; OP_RSCS(1,3); } @@ -1509,7 +1470,7 @@ TEMPLATE static u32 FASTCALL OP_RSC_S_IMM_VAL(const u32 i) #define OP_TST(a) \ { \ - unsigned tmp = cpu->R[REG_POS(i,16)] & shift_op; \ + u32 tmp = cpu->R[REG_POS(i,16)] & shift_op; \ cpu->CPSR.bits.C = c; \ cpu->CPSR.bits.N = BIT31(tmp); \ cpu->CPSR.bits.Z = (tmp==0); \ @@ -1646,14 +1607,13 @@ TEMPLATE static u32 FASTCALL OP_TEQ_IMM_VAL(const u32 i) u32 tmp = cpu->R[REG_POS(i,16)] - shift_op; \ cpu->CPSR.bits.N = BIT31(tmp); \ cpu->CPSR.bits.Z = (tmp==0); \ - cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(cpu->R[REG_POS(i,16)], shift_op, tmp); \ - cpu->CPSR.bits.V = SIGNED_UNDERFLOW(cpu->R[REG_POS(i,16)], shift_op, tmp); \ + cpu->CPSR.bits.C = !BorrowFrom(cpu->R[REG_POS(i,16)], shift_op); \ + cpu->CPSR.bits.V = OverflowFromSUB(tmp, cpu->R[REG_POS(i,16)], shift_op); \ return a; \ } TEMPLATE static u32 FASTCALL OP_CMP_LSL_IMM(const u32 i) { - u32 shift_op; LSL_IMM; OP_CMP(1); } @@ -1666,7 +1626,6 @@ TEMPLATE static u32 FASTCALL OP_CMP_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_CMP_LSR_IMM(const u32 i) { - u32 shift_op; LSR_IMM; OP_CMP(1); } @@ -1679,7 +1638,6 @@ TEMPLATE static u32 FASTCALL OP_CMP_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_CMP_ASR_IMM(const u32 i) { - u32 shift_op; ASR_IMM; OP_CMP(1); } @@ -1692,7 +1650,6 @@ TEMPLATE static u32 FASTCALL OP_CMP_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_CMP_ROR_IMM(const u32 i) { - u32 shift_op; ROR_IMM; OP_CMP(1); } @@ -1718,14 +1675,13 @@ TEMPLATE static u32 FASTCALL OP_CMP_IMM_VAL(const u32 i) u32 tmp = cpu->R[REG_POS(i,16)] + shift_op; \ cpu->CPSR.bits.N = BIT31(tmp); \ cpu->CPSR.bits.Z = (tmp==0); \ - cpu->CPSR.bits.C = UNSIGNED_OVERFLOW(cpu->R[REG_POS(i,16)], shift_op, tmp); \ - cpu->CPSR.bits.V = SIGNED_OVERFLOW(cpu->R[REG_POS(i,16)], shift_op, tmp); \ + cpu->CPSR.bits.C = CarryFrom(cpu->R[REG_POS(i,16)], shift_op); \ + cpu->CPSR.bits.V = OverflowFromADD(tmp, cpu->R[REG_POS(i,16)], shift_op); \ return a; \ } TEMPLATE static u32 FASTCALL OP_CMN_LSL_IMM(const u32 i) { - u32 shift_op; LSL_IMM; OP_CMN(1); } @@ -1738,7 +1694,6 @@ TEMPLATE static u32 FASTCALL OP_CMN_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_CMN_LSR_IMM(const u32 i) { - u32 shift_op; LSR_IMM; OP_CMN(1); } @@ -1751,7 +1706,6 @@ TEMPLATE static u32 FASTCALL OP_CMN_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_CMN_ASR_IMM(const u32 i) { - u32 shift_op; ASR_IMM; OP_CMN(1); } @@ -1764,7 +1718,6 @@ TEMPLATE static u32 FASTCALL OP_CMN_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_CMN_ROR_IMM(const u32 i) { - u32 shift_op; ROR_IMM; OP_CMN(1); } @@ -1803,7 +1756,7 @@ TEMPLATE static u32 FASTCALL OP_CMN_IMM_VAL(const u32 i) armcpu_switchMode(cpu, SPSR.bits.mode); \ cpu->CPSR=SPSR; \ cpu->changeCPSR(); \ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1)); \ + cpu->R[15] &= (0xFFFFFFFC|(((u32)cpu->CPSR.bits.T)<<1)); \ cpu->next_instruction = cpu->R[15]; \ return b; \ } \ @@ -1815,7 +1768,6 @@ TEMPLATE static u32 FASTCALL OP_CMN_IMM_VAL(const u32 i) TEMPLATE static u32 FASTCALL OP_ORR_LSL_IMM(const u32 i) { - u32 shift_op; LSL_IMM; OP_ORR(1, 3); } @@ -1828,7 +1780,6 @@ TEMPLATE static u32 FASTCALL OP_ORR_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_ORR_LSR_IMM(const u32 i) { - u32 shift_op; LSR_IMM; OP_ORR(1, 3); } @@ -1841,7 +1792,6 @@ TEMPLATE static u32 FASTCALL OP_ORR_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_ORR_ASR_IMM(const u32 i) { - u32 shift_op; ASR_IMM; OP_ORR(1, 3); } @@ -1854,7 +1804,6 @@ TEMPLATE static u32 FASTCALL OP_ORR_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_ORR_ROR_IMM(const u32 i) { - u32 shift_op; ROR_IMM; OP_ORR(1, 3); } @@ -1941,13 +1890,13 @@ TEMPLATE static u32 FASTCALL OP_ORR_S_IMM_VAL(const u32 i) #define OP_MOVS(a, b) \ cpu->R[REG_POS(i,12)] = shift_op; \ - if(BIT20(i) && REG_POS(i,12)==15) \ + if(REG_POS(i,12)==15) \ { \ Status_Reg SPSR = cpu->SPSR; \ armcpu_switchMode(cpu, SPSR.bits.mode); \ cpu->CPSR=SPSR; \ cpu->changeCPSR(); \ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1)); \ + cpu->R[15] &= (0xFFFFFFFC|(((u32)cpu->CPSR.bits.T)<<1)); \ cpu->next_instruction = cpu->R[15]; \ return b; \ } \ @@ -1958,7 +1907,6 @@ TEMPLATE static u32 FASTCALL OP_ORR_S_IMM_VAL(const u32 i) TEMPLATE static u32 FASTCALL OP_MOV_LSL_IMM(const u32 i) { - u32 shift_op; LSL_IMM; OP_MOV(1,3); } @@ -1966,13 +1914,12 @@ TEMPLATE static u32 FASTCALL OP_MOV_LSL_IMM(const u32 i) TEMPLATE static u32 FASTCALL OP_MOV_LSL_REG(const u32 i) { LSL_REG; - if (REG_POS(i,0) == 15) shift_op += 4; + if (REG_POS(i,0) == 15) shift_op += 4; OP_MOV(2,4); } TEMPLATE static u32 FASTCALL OP_MOV_LSR_IMM(const u32 i) { - u32 shift_op; LSR_IMM; OP_MOV(1,3); } @@ -1980,13 +1927,12 @@ TEMPLATE static u32 FASTCALL OP_MOV_LSR_IMM(const u32 i) TEMPLATE static u32 FASTCALL OP_MOV_LSR_REG(const u32 i) { LSR_REG; - if (REG_POS(i,0) == 15) shift_op += 4; + if (REG_POS(i,0) == 15) shift_op += 4; OP_MOV(2,4); } TEMPLATE static u32 FASTCALL OP_MOV_ASR_IMM(const u32 i) { - u32 shift_op; ASR_IMM; OP_MOV(1,3); } @@ -1999,7 +1945,6 @@ TEMPLATE static u32 FASTCALL OP_MOV_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_MOV_ROR_IMM(const u32 i) { - u32 shift_op; ROR_IMM; OP_MOV(1,3); } @@ -2026,7 +1971,7 @@ TEMPLATE static u32 FASTCALL OP_MOV_S_LSL_IMM(const u32 i) TEMPLATE static u32 FASTCALL OP_MOV_S_LSL_REG(const u32 i) { S_LSL_REG; - if (REG_POS(i,0) == 15) shift_op += 4; + if (REG_POS(i,0) == 15) shift_op += 4; OP_MOVS(2,4); } @@ -2039,7 +1984,7 @@ TEMPLATE static u32 FASTCALL OP_MOV_S_LSR_IMM(const u32 i) TEMPLATE static u32 FASTCALL OP_MOV_S_LSR_REG(const u32 i) { S_LSR_REG; - if (REG_POS(i,0) == 15) shift_op += 4; + if (REG_POS(i,0) == 15) shift_op += 4; OP_MOVS(2,4); } @@ -2094,7 +2039,7 @@ TEMPLATE static u32 FASTCALL OP_MOV_S_IMM_VAL(const u32 i) armcpu_switchMode(cpu, SPSR.bits.mode); \ cpu->CPSR=SPSR; \ cpu->changeCPSR(); \ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1)); \ + cpu->R[15] &= (0xFFFFFFFC|(((u32)cpu->CPSR.bits.T)<<1)); \ cpu->next_instruction = cpu->R[15]; \ return b; \ } \ @@ -2105,7 +2050,6 @@ TEMPLATE static u32 FASTCALL OP_MOV_S_IMM_VAL(const u32 i) TEMPLATE static u32 FASTCALL OP_BIC_LSL_IMM(const u32 i) { - u32 shift_op; LSL_IMM; OP_BIC(1,3); } @@ -2118,7 +2062,6 @@ TEMPLATE static u32 FASTCALL OP_BIC_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_BIC_LSR_IMM(const u32 i) { - u32 shift_op; LSR_IMM; OP_BIC(1,3); } @@ -2131,7 +2074,6 @@ TEMPLATE static u32 FASTCALL OP_BIC_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_BIC_ASR_IMM(const u32 i) { - u32 shift_op; ASR_IMM; OP_BIC(1,3); } @@ -2144,7 +2086,6 @@ TEMPLATE static u32 FASTCALL OP_BIC_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_BIC_ROR_IMM(const u32 i) { - u32 shift_op; ROR_IMM; OP_BIC(1,3); } @@ -2237,7 +2178,7 @@ TEMPLATE static u32 FASTCALL OP_BIC_S_IMM_VAL(const u32 i) armcpu_switchMode(cpu, SPSR.bits.mode); \ cpu->CPSR=SPSR; \ cpu->changeCPSR(); \ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1)); \ + cpu->R[15] &= (0xFFFFFFFC|(((u32)cpu->CPSR.bits.T)<<1)); \ cpu->next_instruction = cpu->R[15]; \ return b; \ } \ @@ -2248,7 +2189,6 @@ TEMPLATE static u32 FASTCALL OP_BIC_S_IMM_VAL(const u32 i) TEMPLATE static u32 FASTCALL OP_MVN_LSL_IMM(const u32 i) { - u32 shift_op; LSL_IMM; OP_MVN(1,3); } @@ -2261,7 +2201,6 @@ TEMPLATE static u32 FASTCALL OP_MVN_LSL_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_MVN_LSR_IMM(const u32 i) { - u32 shift_op; LSR_IMM; OP_MVN(1,3); } @@ -2274,7 +2213,6 @@ TEMPLATE static u32 FASTCALL OP_MVN_LSR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_MVN_ASR_IMM(const u32 i) { - u32 shift_op; ASR_IMM; OP_MVN(1,3); } @@ -2287,7 +2225,6 @@ TEMPLATE static u32 FASTCALL OP_MVN_ASR_REG(const u32 i) TEMPLATE static u32 FASTCALL OP_MVN_ROR_IMM(const u32 i) { - u32 shift_op; ROR_IMM; OP_MVN(1,3); } @@ -2386,9 +2323,7 @@ TEMPLATE static u32 FASTCALL OP_MUL(const u32 i) TEMPLATE static u32 FASTCALL OP_MLA(const u32 i) { u32 v = cpu->R[REG_POS(i,8)]; - u32 a = cpu->R[REG_POS(i,0)]; - u32 b = cpu->R[REG_POS(i,12)]; - cpu->R[REG_POS(i,16)] = a * v + b; + cpu->R[REG_POS(i,16)] = cpu->R[REG_POS(i,0)] * v + cpu->R[REG_POS(i,12)]; MUL_Mxx_END(2); } @@ -2434,7 +2369,7 @@ TEMPLATE static u32 FASTCALL OP_MLA_S(const u32 i) TEMPLATE static u32 FASTCALL OP_UMULL(const u32 i) { u32 v = cpu->R[REG_POS(i,8)]; - u64 res = (u64)v * (u64)cpu->R[REG_POS(i,0)]; + u64 res = (u64)cpu->R[REG_POS(i,0)] * (u64)v; cpu->R[REG_POS(i,12)] = (u32)res; cpu->R[REG_POS(i,16)] = (u32)(res>>32); @@ -2445,10 +2380,13 @@ TEMPLATE static u32 FASTCALL OP_UMULL(const u32 i) TEMPLATE static u32 FASTCALL OP_UMLAL(const u32 i) { u32 v = cpu->R[REG_POS(i,8)]; - u64 res = (u64)v * (u64)cpu->R[REG_POS(i,0)] + (u64)cpu->R[REG_POS(i,12)]; + u64 res = (u64)cpu->R[REG_POS(i,0)] * (u64)v; - cpu->R[REG_POS(i,12)] = (u32)res; - cpu->R[REG_POS(i,16)] += (u32)(res>>32); + // RdLo = (Rm * Rs)[31:0] + RdLo /* Unsigned multiplication */ + // RdHi = (Rm * Rs)[63:32] + RdHi + CarryFrom((Rm * Rs)[31:0] + RdLo) + u32 tmp = (u32)res; // low + cpu->R[REG_POS(i,16)] = (u32)(res>>32) + cpu->R[REG_POS(i,16)] + CarryFrom(tmp, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,12)] += tmp; MUL_UMxxL_END(3); } @@ -2456,13 +2394,13 @@ TEMPLATE static u32 FASTCALL OP_UMLAL(const u32 i) TEMPLATE static u32 FASTCALL OP_UMULL_S(const u32 i) { u32 v = cpu->R[REG_POS(i,8)]; - u64 res = (u64)v * (u64)cpu->R[REG_POS(i,0)]; + u64 res = ((u64)cpu->R[REG_POS(i,0)] * (u64)v); cpu->R[REG_POS(i,12)] = (u32)res; cpu->R[REG_POS(i,16)] = (u32)(res>>32); cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]); - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0); + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) && (cpu->R[REG_POS(i,12)]==0); MUL_UMxxL_END(2); } @@ -2470,10 +2408,13 @@ TEMPLATE static u32 FASTCALL OP_UMULL_S(const u32 i) TEMPLATE static u32 FASTCALL OP_UMLAL_S(const u32 i) { u32 v = cpu->R[REG_POS(i,8)]; - u64 res = (u64)v * (u64)cpu->R[REG_POS(i,0)] + (u64)cpu->R[REG_POS(i,12)]; + u64 res = (u64)cpu->R[REG_POS(i,0)] * (u64)v; - cpu->R[REG_POS(i,12)] = (u32)res; - cpu->R[REG_POS(i,16)] += (u32)(res>>32); + // RdLo = (Rm * Rs)[31:0] + RdLo /* Unsigned multiplication */ + // RdHi = (Rm * Rs)[63:32] + RdHi + CarryFrom((Rm * Rs)[31:0] + RdLo) + u32 tmp = (u32)res; // low + cpu->R[REG_POS(i,16)] = (u32)(res>>32) + cpu->R[REG_POS(i,16)] + CarryFrom(tmp, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,12)] += tmp; cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]); cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0); @@ -2486,6 +2427,7 @@ TEMPLATE static u32 FASTCALL OP_UMLAL_S(const u32 i) //----------------------------------------------------------------------------- #define MUL_SMxxL_END(c) \ + v &= 0xFFFFFFFF; \ v >>= 8; \ if((v==0)||(v==0xFFFFFF)) \ return c+1; \ @@ -2501,14 +2443,11 @@ TEMPLATE static u32 FASTCALL OP_UMLAL_S(const u32 i) TEMPLATE static u32 FASTCALL OP_SMULL(const u32 i) { s64 v = (s32)cpu->R[REG_POS(i,8)]; - s64 b = (s32)cpu->R[REG_POS(i,0)]; - s64 res = v * b; + s64 res = v * (s64)(s32)cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (u32)(res&0xFFFFFFFF); + cpu->R[REG_POS(i,12)] = (u32)res; cpu->R[REG_POS(i,16)] = (u32)(res>>32); - v &= 0xFFFFFFFF; - MUL_SMxxL_END(2); } @@ -2516,26 +2455,23 @@ TEMPLATE static u32 FASTCALL OP_SMLAL(const u32 i) { s64 v = (s32)cpu->R[REG_POS(i,8)]; - s64 b = (s32)cpu->R[REG_POS(i,0)]; - s64 res = v * b + (u64)cpu->R[REG_POS(i,12)]; + s64 res = v * (s64)(s32)cpu->R[REG_POS(i,0)]; - //LOG("%08X * %08X + %08X%08X \r \n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], cpu->R[REG_POS(i,16)], cpu->R[REG_POS(i,12)]); + //LOG("%08X * %08X + %08X%08X\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], cpu->R[REG_POS(i,16)], cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,12)] = (u32)res; - cpu->R[REG_POS(i,16)] += (u32)(res>>32); + u32 tmp = (u32)res; + cpu->R[REG_POS(i,16)] = (u32)(res>>32) + cpu->R[REG_POS(i,16)] + CarryFrom(tmp, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,12)] += tmp; - //LOG("= %08X%08X %08X%08X \r \n", cpu->R[REG_POS(i,16)], cpu->R[REG_POS(i,12)], res); + //LOG("= %08X%08X %08X%08X\n", cpu->R[REG_POS(i,16)], cpu->R[REG_POS(i,12)], res); - v &= 0xFFFFFFFF; - MUL_SMxxL_END(3); } TEMPLATE static u32 FASTCALL OP_SMULL_S(const u32 i) { s64 v = (s32)cpu->R[REG_POS(i,8)]; - s64 b = (s32)cpu->R[REG_POS(i,0)]; - s64 res = v * b; + s64 res = v * (s64)(s32)cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,12)] = (u32)res; cpu->R[REG_POS(i,16)] = (u32)(res>>32); @@ -2543,25 +2479,21 @@ TEMPLATE static u32 FASTCALL OP_SMULL_S(const u32 i) cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]); cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0); - v &= 0xFFFFFFFF; - MUL_SMxxL_END(2); } TEMPLATE static u32 FASTCALL OP_SMLAL_S(const u32 i) { s64 v = (s32)cpu->R[REG_POS(i,8)]; - s64 b = (s32)cpu->R[REG_POS(i,0)]; - s64 res = v * b + (u64)cpu->R[REG_POS(i,12)]; + s64 res = v * (s64)(s32)cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (u32)res; - cpu->R[REG_POS(i,16)] += (u32)(res>>32); + u32 tmp = (u32)res; + cpu->R[REG_POS(i,16)] = (u32)(res>>32) + cpu->R[REG_POS(i,16)] + CarryFrom(tmp, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,12)] += tmp; cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]); cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0); - v &= 0xFFFFFFFF; - MUL_SMxxL_END(3); } @@ -2572,7 +2504,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAL_S(const u32 i) TEMPLATE static u32 FASTCALL OP_SWP(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)]; - u32 tmp = ROR(READ32(cpu->mem_if->data, adr), ((cpu->R[REG_POS(i,16)]&3)<<3)); + u32 tmp = ROR(READ32(cpu->mem_if->data, adr), (adr & 3)<<3); WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,0)]); cpu->R[REG_POS(i,12)] = tmp; @@ -2691,8 +2623,6 @@ TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_P_REG_OFF(const u32 i) cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - - return MMU_aluMemAccessCycles(3,adr); } @@ -2780,8 +2710,8 @@ TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_M_REG_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_P_IMM_OFF(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,16)] += IMM_OFF; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] += IMM_OFF; return MMU_aluMemAccessCycles(2,adr); } @@ -2789,8 +2719,8 @@ TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_P_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_M_IMM_OFF(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,16)] -= IMM_OFF; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] -= IMM_OFF; return MMU_aluMemAccessCycles(2,adr); } @@ -2798,8 +2728,8 @@ TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_M_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_P_REG_OFF(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; return MMU_aluMemAccessCycles(2,adr); } @@ -2807,8 +2737,8 @@ TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_P_REG_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_M_REG_OFF(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; return MMU_aluMemAccessCycles(2,adr); } @@ -3037,23 +2967,64 @@ TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_M_REG_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_MRS_CPSR(const u32 i) { - cpu->R[REG_POS(cpu->instruction,12)] = cpu->CPSR.val; + cpu->R[REG_POS(i,12)] = cpu->CPSR.val; return 1; } TEMPLATE static u32 FASTCALL OP_MRS_SPSR(const u32 i) { - cpu->R[REG_POS(cpu->instruction,12)] = cpu->SPSR.val; + cpu->R[REG_POS(i,12)] = cpu->SPSR.val; return 1; } +#define v4_UNALLOC_MASK 0x0FFFFF00 +#define v4_USER_MASK 0xF0000000 +#define v4_PRIV_MASK 0x0000000F +#define v4_STATE_MASK 0x00000020 +#define v5_UNALLOC_MASK 0x07FFFF00 +#define v5_USER_MASK 0xF8000000 +#define v5_PRIV_MASK 0x0000000F +#define v5_STATE_MASK 0x00000020 TEMPLATE static u32 FASTCALL OP_MSR_CPSR(const u32 i) { u32 operand = cpu->R[REG_POS(i,0)]; - + +#if 0 + // TODO + u32 mask = 0; + u32 byte_mask = (BIT16(i)?0x000000FF:0x00000000) | + (BIT17(i)?0x0000FF00:0x00000000) | + (BIT18(i)?0x00FF0000:0x00000000) | + (BIT19(i)?0xFF000000:0x00000000); + + if (PROCNUM == 0) + { + if ((operand & v5_UNALLOC_MASK) != 0) printf("ARM9: MSR_CPSR_REG UNPREDICTABLE UNALLOC (operand %08X)\n", operand); + if (cpu->CPSR.bits.mode != USR) // Privileged mode + { + if ((operand & v5_STATE_MASK) != 0) printf("ARM9: MSR_CPSR_REG UNPREDICTABLE STATE (operand %08X)\n", operand); + mask = byte_mask & (v5_USER_MASK | v5_PRIV_MASK); + } + else + mask = byte_mask & v5_USER_MASK; + } + else + { + if ((operand & v4_UNALLOC_MASK) != 0) printf("ARM7: MSR_CPSR_REG UNPREDICTABLE UNALLOC (operand %08X)\n", operand); + if(cpu->CPSR.bits.mode != USR) // Privileged mode + { + if ((operand & v4_STATE_MASK) != 0) printf("ARM7: MSR_CPSR_REG UNPREDICTABLE STATE (operand %08X)\n", operand); + mask = byte_mask & (v4_USER_MASK | v4_PRIV_MASK); + } + else + mask = byte_mask & v4_USER_MASK; + } + cpu->CPSR.val = ((cpu->CPSR.val & (~mask)) | (operand & mask)); + if (BIT16(i)) armcpu_switchMode(cpu, cpu->CPSR.bits.mode); +#else if(cpu->CPSR.bits.mode!=USR) { if(BIT16(i)) @@ -3070,6 +3041,7 @@ TEMPLATE static u32 FASTCALL OP_MSR_CPSR(const u32 i) cpu->CPSR.val = (cpu->CPSR.val & 0x00FFFFFF) | (operand & 0xFF000000); cpu->changeCPSR(); +#endif return 1; } @@ -3077,20 +3049,43 @@ TEMPLATE static u32 FASTCALL OP_MSR_CPSR(const u32 i) TEMPLATE static u32 FASTCALL OP_MSR_SPSR(const u32 i) { u32 operand = cpu->R[REG_POS(i,0)]; - + +#if 0 + // TODO + u32 mask = 0; + u32 byte_mask = (BIT16(i)?0x000000FF:0x00000000) | + (BIT17(i)?0x0000FF00:0x00000000) | + (BIT18(i)?0x00FF0000:0x00000000) | + (BIT19(i)?0xFF000000:0x00000000); + + if (PROCNUM == 0) + { + if ((operand & v5_UNALLOC_MASK) != 0) printf("ARM9: MSR_SPSR_REG UNPREDICTABLE UNALLOC (operand %08X)\n", operand); + // if CurrentModeHasSPSR + mask = byte_mask & (v5_USER_MASK | v5_PRIV_MASK | v5_STATE_MASK); + } + else + { + if ((operand & v4_UNALLOC_MASK) != 0) printf("ARM7: MSR_SPSR_REG UNPREDICTABLE UNALLOC (operand %08X)\n", operand); + // if CurrentModeHasSPSR + mask = byte_mask & (v4_USER_MASK | v4_PRIV_MASK | v4_STATE_MASK); + } + cpu->SPSR.val = ((cpu->SPSR.val & (~mask)) | (operand & mask)); +#else if(cpu->CPSR.bits.mode!=USR) { if(BIT16(i)) { - cpu->SPSR.val = (cpu->SPSR.val & 0xFFFFFF00) | (operand & 0XFF); + cpu->SPSR.val = (cpu->SPSR.val & 0xFFFFFF00) | (operand & 0xFF); } if(BIT17(i)) - cpu->SPSR.val = (cpu->SPSR.val & 0xFFFF00FF) | (operand & 0XFF00); + cpu->SPSR.val = (cpu->SPSR.val & 0xFFFF00FF) | (operand & 0xFF00); if(BIT18(i)) - cpu->SPSR.val = (cpu->SPSR.val & 0xFF00FFFF) | (operand & 0XFF0000); + cpu->SPSR.val = (cpu->SPSR.val & 0xFF00FFFF) | (operand & 0xFF0000); } if(BIT19(i)) - cpu->SPSR.val = (cpu->SPSR.val & 0x00FFFFFF) | (operand & 0XFF000000); + cpu->SPSR.val = (cpu->SPSR.val & 0x00FFFFFF) | (operand & 0xFF000000); +#endif return 1; } @@ -3098,26 +3093,60 @@ TEMPLATE static u32 FASTCALL OP_MSR_SPSR(const u32 i) TEMPLATE static u32 FASTCALL OP_MSR_CPSR_IMM_VAL(const u32 i) { IMM_VALUE; + +#if 0 + // TODO + u32 operand = shift_op; + u32 mask = 0; + u32 byte_mask = (BIT16(i)?0x000000FF:0x00000000) | + (BIT17(i)?0x0000FF00:0x00000000) | + (BIT18(i)?0x00FF0000:0x00000000) | + (BIT19(i)?0xFF000000:0x00000000); + if (PROCNUM == 0) + { + if ((operand & v5_UNALLOC_MASK) != 0) printf("ARM9: MSR_CPSR_IMM UNPREDICTABLE UNALLOC (operand %08X)\n", operand); + if (cpu->CPSR.bits.mode != USR) // Privileged mode + { + if ((operand & v5_STATE_MASK) != 0) printf("ARM9: MSR_CPSR_IMM UNPREDICTABLE STATE (operand %08X)\n", operand); + mask = byte_mask & (v5_USER_MASK | v5_PRIV_MASK); + } + else + mask = byte_mask & v5_USER_MASK; + } + else + { + if ((operand & v4_UNALLOC_MASK) != 0) printf("ARM7: MSR_CPSR_IMM UNPREDICTABLE UNALLOC (operand %08X)\n", operand); + if(cpu->CPSR.bits.mode != USR) // Privileged mode + { + if ((operand & v4_STATE_MASK) != 0) printf("ARM7: MSR_CPSR_IMM UNPREDICTABLE STATE (operand %08X)\n", operand); + mask = byte_mask & (v4_USER_MASK | v4_PRIV_MASK); + } + else + mask = byte_mask & v4_USER_MASK; + } + cpu->CPSR.val = ((cpu->CPSR.val & (~mask)) | (operand & mask)); + if (BIT16(i)) armcpu_switchMode(cpu, cpu->CPSR.bits.mode); +#else if(cpu->CPSR.bits.mode!=USR) { if(BIT16(i)) { armcpu_switchMode(cpu, shift_op & 0x1F); - cpu->CPSR.val = (cpu->CPSR.val & 0xFFFFFF00) | (shift_op & 0XFF); + cpu->CPSR.val = (cpu->CPSR.val & 0xFFFFFF00) | (shift_op & 0xFF); } if(BIT17(i)) - cpu->CPSR.val = (cpu->CPSR.val & 0xFFFF00FF) | (shift_op & 0XFF00); + cpu->CPSR.val = (cpu->CPSR.val & 0xFFFF00FF) | (shift_op & 0xFF00); if(BIT18(i)) - cpu->CPSR.val = (cpu->CPSR.val & 0xFF00FFFF) | (shift_op & 0XFF0000); + cpu->CPSR.val = (cpu->CPSR.val & 0xFF00FFFF) | (shift_op & 0xFF0000); } if(BIT19(i)) { - //cpu->CPSR.val = (cpu->CPSR.val & 0xFF000000) | (shift_op & 0XFF000000); + //cpu->CPSR.val = (cpu->CPSR.val & 0xFF000000) | (shift_op & 0xFF000000); cpu->CPSR.val = (cpu->CPSR.val & 0x00FFFFFF) | (shift_op & 0xFF000000); } - cpu->changeCPSR(); +#endif return 1; } @@ -3126,21 +3155,47 @@ TEMPLATE static u32 FASTCALL OP_MSR_SPSR_IMM_VAL(const u32 i) { IMM_VALUE; +#if 0 + // TODO + u32 operand = shift_op; + u32 mask = 0; + u32 byte_mask = (BIT16(i)?0x000000FF:0x00000000) | + (BIT17(i)?0x0000FF00:0x00000000) | + (BIT18(i)?0x00FF0000:0x00000000) | + (BIT19(i)?0xFF000000:0x00000000); + + if (PROCNUM == 0) + { + if ((operand & v5_UNALLOC_MASK) != 0) printf("ARM9: MSR_SPSR_IMM UNPREDICTABLE UNALLOC (operand %08X)\n", operand); + // if CurrentModeHasSPSR + mask = byte_mask & (v5_USER_MASK | v5_PRIV_MASK | v5_STATE_MASK); + } + else + { + if ((operand & v4_UNALLOC_MASK) != 0) printf("ARM7: MSR_SPSR_IMM UNPREDICTABLE UNALLOC (operand %08X)\n", operand); + // if CurrentModeHasSPSR + mask = byte_mask & (v4_USER_MASK | v4_PRIV_MASK | v4_STATE_MASK); + } + cpu->SPSR.val = ((cpu->SPSR.val & (~mask)) | (operand & mask)); +#else if(cpu->CPSR.bits.mode!=USR) { if(BIT16(i)) { - cpu->SPSR.val = (cpu->SPSR.val & 0xFFFFFF00) | (shift_op & 0XFF); + cpu->SPSR.val = (cpu->SPSR.val & 0xFFFFFF00) | (shift_op & 0xFF); } if(BIT17(i)) - cpu->SPSR.val = (cpu->SPSR.val & 0xFFFF00FF) | (shift_op & 0XFF00); + cpu->SPSR.val = (cpu->SPSR.val & 0xFFFF00FF) | (shift_op & 0xFF00); if(BIT18(i)) - cpu->SPSR.val = (cpu->SPSR.val & 0xFF00FFFF) | (shift_op & 0XFF0000); + cpu->SPSR.val = (cpu->SPSR.val & 0xFF00FFFF) | (shift_op & 0xFF0000); } if(BIT19(i)) - cpu->SPSR.val = (cpu->SPSR.val & 0xFF000000) | (shift_op & 0XFF000000); + { + cpu->SPSR.val = (cpu->SPSR.val & 0xFF000000) | (shift_op & 0xFF000000); + } cpu->changeCPSR(); +#endif return 1; } @@ -3151,40 +3206,42 @@ TEMPLATE static u32 FASTCALL OP_MSR_SPSR_IMM_VAL(const u32 i) TEMPLATE static u32 FASTCALL OP_BX(const u32 i) { - u32 tmp = cpu->R[REG_POS(cpu->instruction, 0)]; + u32 tmp = cpu->R[REG_POS(i, 0)]; + if (REG_POS(i, 0) == 15) + { + printf("ARM%c: BX using PC as operand\n", PROCNUM?'7':'9'); + //emu_halt(); + } cpu->CPSR.bits.T = BIT0(tmp); - //zeromus has a little concern about these. shouldnt they be 0xFFFFFFFC? - //can someone refute this or prove it? - cpu->R[15] = tmp & 0xFFFFFFFE; + cpu->R[15] = tmp & (0xFFFFFFFC|(cpu->CPSR.bits.T<<1)); cpu->next_instruction = cpu->R[15]; return 3; } TEMPLATE static u32 FASTCALL OP_BLX_REG(const u32 i) { - u32 tmp = cpu->R[REG_POS(cpu->instruction, 0)]; + u32 tmp = cpu->R[REG_POS(i, 0)]; cpu->R[14] = cpu->next_instruction; cpu->CPSR.bits.T = BIT0(tmp); - //zeromus has a little concern about these. shouldnt they be 0xFFFFFFFC? - //can someone refute this or prove it? - cpu->R[15] = tmp & 0xFFFFFFFE; + cpu->R[15] = tmp & (0xFFFFFFFC|(cpu->CPSR.bits.T<<1)); cpu->next_instruction = cpu->R[15]; return 3; } -#define SIGNEXTEND_24(i) (((s32)((i)<<8))>>8) +#define SIGNEXTEND_24(i) (((s32)i<<8)>>8) TEMPLATE static u32 FASTCALL OP_B(const u32 i) { - u32 off = SIGNEXTEND_24(cpu->instruction); - if(CONDITION(cpu->instruction)==0xF) + u32 off = SIGNEXTEND_24(i); + if(CONDITION(i)==0xF) { cpu->R[14] = cpu->next_instruction; cpu->CPSR.bits.T = 1; } cpu->R[15] += (off<<2); + cpu->R[15] &= (0xFFFFFFFC|(cpu->CPSR.bits.T<<1)); cpu->next_instruction = cpu->R[15]; return 3; @@ -3192,14 +3249,15 @@ TEMPLATE static u32 FASTCALL OP_B(const u32 i) TEMPLATE static u32 FASTCALL OP_BL(const u32 i) { - u32 off = SIGNEXTEND_24(cpu->instruction); - if(CONDITION(cpu->instruction)==0xF) + u32 off = SIGNEXTEND_24(i); + if(CONDITION(i)==0xF) { cpu->CPSR.bits.T = 1; cpu->R[15] += 2; } cpu->R[14] = cpu->next_instruction; cpu->R[15] += (off<<2); + cpu->R[15] &= (0xFFFFFFFC|(cpu->CPSR.bits.T<<1)); cpu->next_instruction = cpu->R[15]; return 3; @@ -3222,7 +3280,7 @@ TEMPLATE static u32 FASTCALL OP_CLZ(const u32 i) { u32 Rm = cpu->R[REG_POS(i,0)]; u32 pos; - + if(Rm==0) { cpu->R[REG_POS(i,12)]=32; @@ -3244,7 +3302,7 @@ TEMPLATE static u32 FASTCALL OP_CLZ(const u32 i) CLZ_TAB[(Rm>>20)&0xF] + CLZ_TAB[(Rm>>24)&0xF] + CLZ_TAB[(Rm>>28)&0xF]; - + cpu->R[REG_POS(i,12)]=32 - pos; return 2; @@ -3258,7 +3316,7 @@ TEMPLATE static u32 FASTCALL OP_QADD(const u32 i) { u32 res = cpu->R[REG_POS(i,16)]+cpu->R[REG_POS(i,0)]; - LOG("spe add \r \n"); + //LOG("spe add\n"); if(SIGNED_OVERFLOW(cpu->R[REG_POS(i,16)],cpu->R[REG_POS(i,0)], res)) { cpu->CPSR.bits.Q=1; @@ -3268,7 +3326,7 @@ TEMPLATE static u32 FASTCALL OP_QADD(const u32 i) cpu->R[REG_POS(i,12)]=res; if(REG_POS(i,12)==15) { - cpu->R[15] &= 0XFFFFFFFC; + cpu->R[15] &= 0xFFFFFFFC; cpu->next_instruction = cpu->R[15]; return 3; } @@ -3279,7 +3337,7 @@ TEMPLATE static u32 FASTCALL OP_QSUB(const u32 i) { u32 res = cpu->R[REG_POS(i,0)]-cpu->R[REG_POS(i,16)]; - LOG("spe add \r \n"); + //LOG("spe add\n"); if(SIGNED_UNDERFLOW(cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,16)], res)) { cpu->CPSR.bits.Q=1; @@ -3289,7 +3347,7 @@ TEMPLATE static u32 FASTCALL OP_QSUB(const u32 i) cpu->R[REG_POS(i,12)]=res; if(REG_POS(i,12)==15) { - cpu->R[15] &= 0XFFFFFFFC; + cpu->R[15] &= 0xFFFFFFFC; cpu->next_instruction = cpu->R[15]; return 3; } @@ -3302,7 +3360,7 @@ TEMPLATE static u32 FASTCALL OP_QDADD(const u32 i) u32 res; - LOG("spe add \r \n"); + //LOG("spe add\n"); if(BIT31(cpu->R[REG_POS(i,16)])!=BIT31(mul)) { cpu->CPSR.bits.Q=1; @@ -3319,7 +3377,7 @@ TEMPLATE static u32 FASTCALL OP_QDADD(const u32 i) cpu->R[REG_POS(i,12)]=res; if(REG_POS(i,12)==15) { - cpu->R[15] &= 0XFFFFFFFC; + cpu->R[15] &= 0xFFFFFFFC; cpu->next_instruction = cpu->R[15]; return 3; } @@ -3332,7 +3390,7 @@ TEMPLATE static u32 FASTCALL OP_QDSUB(const u32 i) u32 res; - LOG("spe add \r \n"); + //LOG("spe add\n"); if(BIT31(cpu->R[REG_POS(i,16)])!=BIT31(mul)) { cpu->CPSR.bits.Q=1; @@ -3349,7 +3407,7 @@ TEMPLATE static u32 FASTCALL OP_QDSUB(const u32 i) cpu->R[REG_POS(i,12)]=res; if(REG_POS(i,12)==15) { - cpu->R[15] &= 0XFFFFFFFC; + cpu->R[15] &= 0xFFFFFFFC; cpu->next_instruction = cpu->R[15]; return 3; } @@ -3365,7 +3423,8 @@ TEMPLATE static u32 FASTCALL OP_QDSUB(const u32 i) TEMPLATE static u32 FASTCALL OP_SMUL_B_B(const u32 i) { - + // checked + //INFO("SMUL_B_B\n"); cpu->R[REG_POS(i,16)] = (u32)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); return 2; @@ -3373,7 +3432,7 @@ TEMPLATE static u32 FASTCALL OP_SMUL_B_B(const u32 i) TEMPLATE static u32 FASTCALL OP_SMUL_B_T(const u32 i) { - + //INFO("SMUL_B_T\n"); cpu->R[REG_POS(i,16)] = (u32)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); return 2; @@ -3381,7 +3440,7 @@ TEMPLATE static u32 FASTCALL OP_SMUL_B_T(const u32 i) TEMPLATE static u32 FASTCALL OP_SMUL_T_B(const u32 i) { - + //INFO("SMUL_T_B\n"); cpu->R[REG_POS(i,16)] = (u32)(HWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); return 2; @@ -3389,7 +3448,7 @@ TEMPLATE static u32 FASTCALL OP_SMUL_T_B(const u32 i) TEMPLATE static u32 FASTCALL OP_SMUL_T_T(const u32 i) { - + //INFO("SMUL_T_T\n"); cpu->R[REG_POS(i,16)] = (u32)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); return 2; @@ -3401,14 +3460,12 @@ TEMPLATE static u32 FASTCALL OP_SMUL_T_T(const u32 i) TEMPLATE static u32 FASTCALL OP_SMLA_B_B(const u32 i) { - u32 tmp = (u32)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); - u32 a = cpu->R[REG_POS(i,12)]; + u32 tmp = (u32)((s16)cpu->R[REG_POS(i,0)]* (s16)cpu->R[REG_POS(i,8)]); - //LOG("SMLABB %08X * %08X + %08X = %08X \r \n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a); - cpu->R[REG_POS(i,16)] = tmp + a; - - if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)])) - cpu->CPSR.bits.Q = 1; + cpu->R[REG_POS(i,16)] = tmp + cpu->R[REG_POS(i,12)]; + + cpu->CPSR.bits.Q = OverflowFromADD(cpu->R[REG_POS(i,16)], tmp, cpu->R[REG_POS(i,12)]); + //INFO("SMLABB %08X * %08X + %08X = %08X\n", (s16)cpu->R[REG_POS(i,0)], (s16)cpu->R[REG_POS(i,8)], cpu->R[REG_POS(i,12)], (s32)cpu->R[REG_POS(i,16)]); return 2; } @@ -3417,8 +3474,8 @@ TEMPLATE static u32 FASTCALL OP_SMLA_B_T(const u32 i) { u32 tmp = (u32)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); u32 a = cpu->R[REG_POS(i,12)]; - - //LOG("SMLABT %08X * %08X + %08X = %08X \r \n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a); + + //INFO("SMLABT %08X * %08X + %08X = %08X\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a); cpu->R[REG_POS(i,16)] = tmp + a; if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)])) @@ -3432,7 +3489,7 @@ TEMPLATE static u32 FASTCALL OP_SMLA_T_B(const u32 i) u32 tmp = (u32)(HWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); u32 a = cpu->R[REG_POS(i,12)]; - //LOG("SMLATB %08X * %08X + %08X = %08X \r \n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a); + //INFO("SMLATB %08X * %08X + %08X = %08X\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a); cpu->R[REG_POS(i,16)] = tmp + a; if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)])) @@ -3446,7 +3503,7 @@ TEMPLATE static u32 FASTCALL OP_SMLA_T_T(const u32 i) u32 tmp = (u32)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); u32 a = cpu->R[REG_POS(i,12)]; - //LOG("SMLATT %08X * %08X + %08X = %08X \r \n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a); + //INFO("SMLATT %08X * %08X + %08X = %08X\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a); cpu->R[REG_POS(i,16)] = tmp + a; if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)])) @@ -3464,7 +3521,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAL_B_B(const u32 i) s64 tmp = (s64)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); u64 res = (u64)tmp + cpu->R[REG_POS(i,12)]; - LOG("SMLALBB %08X * %08X + %08X%08X = %08X%08X \r \n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + (res + ((tmp<0)*0xFFFFFFFF))), (int)(u32) res); + //INFO("SMLALBB %08X * %08X + %08X%08X = %08X%08X\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + (res + ((tmp<0)*0xFFFFFFFF))), (int)(u32) res); cpu->R[REG_POS(i,12)] = (u32) res; cpu->R[REG_POS(i,16)] += (res + ((tmp<0)*0xFFFFFFFF)); @@ -3477,7 +3534,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAL_B_T(const u32 i) s64 tmp = (s64)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); u64 res = (u64)tmp + cpu->R[REG_POS(i,12)]; - LOG("SMLALBT %08X * %08X + %08X%08X = %08X%08X \r \n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(u32) res); + //INFO("SMLALBT %08X * %08X + %08X%08X = %08X%08X\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(u32) res); cpu->R[REG_POS(i,12)] = (u32) res; cpu->R[REG_POS(i,16)] += res + ((tmp<0)*0xFFFFFFFF); @@ -3490,7 +3547,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAL_T_B(const u32 i) s64 tmp = (s64)(HWORD(cpu->R[REG_POS(i,0)])* (s64)LWORD(cpu->R[REG_POS(i,8)])); u64 res = (u64)tmp + cpu->R[REG_POS(i,12)]; - LOG("SMLALTB %08X * %08X + %08X%08X = %08X%08X \r \n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(u32) res); + //INFO("SMLALTB %08X * %08X + %08X%08X = %08X%08X\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(u32) res); cpu->R[REG_POS(i,12)] = (u32) res; cpu->R[REG_POS(i,16)] += res + ((tmp<0)*0xFFFFFFFF); @@ -3503,7 +3560,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAL_T_T(const u32 i) s64 tmp = (s64)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); u64 res = (u64)tmp + cpu->R[REG_POS(i,12)]; - LOG("SMLALTT %08X * %08X + %08X%08X = %08X%08X \r \n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(u32) res); + //INFO("SMLALTT %08X * %08X + %08X%08X = %08X%08X\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(u32) res); cpu->R[REG_POS(i,12)] = (u32) res; cpu->R[REG_POS(i,16)] += res + ((tmp<0)*0xFFFFFFFF); @@ -3519,7 +3576,7 @@ TEMPLATE static u32 FASTCALL OP_SMULW_B(const u32 i) { s64 tmp = (s64)LWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); - //LOG("SMULWB %08X * %08X = %08X \r \n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], ((tmp>>16)&0xFFFFFFFF); + //INFO("SMULWB %08X * %08X = %08X\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], ((tmp>>16)&0xFFFFFFFF)); cpu->R[REG_POS(i,16)] = ((tmp>>16)&0xFFFFFFFF); @@ -3530,7 +3587,7 @@ TEMPLATE static u32 FASTCALL OP_SMULW_T(const u32 i) { s64 tmp = (s64)HWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); - //LOG("SMULWT %08X * %08X = %08X \r \n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], ((tmp>>16)&0xFFFFFFFF)); + //INFO("SMULWT %08X * %08X = %08X\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], ((tmp>>16)&0xFFFFFFFF)); cpu->R[REG_POS(i,16)] = ((tmp>>16)&0xFFFFFFFF); @@ -3546,7 +3603,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAW_B(const u32 i) s64 tmp = (s64)LWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); u32 a = cpu->R[REG_POS(i,12)]; - //LOG("SMLAWB %08X * %08X + %08X = %08X \r \n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, (tmp>>16) + a); + //INFO("SMLAWB %08X * %08X + %08X = %08X\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, (tmp>>16) + a); tmp = (tmp>>16); @@ -3563,7 +3620,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAW_T(const u32 i) s64 tmp = (s64)HWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); u32 a = cpu->R[REG_POS(i,12)]; - //LOG("SMLAWT %08X * %08X + %08X = %08X \r \n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, ((tmp>>16)&0xFFFFFFFF) + a); + //INFO("SMLAWT %08X * %08X + %08X = %08X\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, ((tmp>>16)&0xFFFFFFFF) + a); tmp = ((tmp>>16)&0xFFFFFFFF); cpu->R[REG_POS(i,16)] = tmp + a; @@ -3577,753 +3634,264 @@ TEMPLATE static u32 FASTCALL OP_SMLAW_T(const u32 i) //----------------------------------------------------------------------------- // LDR //----------------------------------------------------------------------------- +#define OP_LDR(a, b) \ + cpu->R[REG_POS(i,12)] = ROR(READ32(cpu->mem_if->data, adr), 8*(adr&3)); \ + \ + if(REG_POS(i,12)==15) \ + { \ + if (PROCNUM == 0) \ + { \ + cpu->CPSR.bits.T = BIT0(cpu->R[15]); \ + cpu->R[15] &= 0xFFFFFFFE; \ + } \ + else \ + { \ + cpu->R[15] &= 0xFFFFFFFC; \ + } \ + cpu->next_instruction = cpu->R[15]; \ + return MMU_aluMemAccessCycles(b,adr); \ + } \ + \ + return MMU_aluMemAccessCycles(a,adr); + +// PRE +#define OP_LDR_W(a, b) \ + cpu->R[REG_POS(i,16)] = adr;\ + cpu->R[REG_POS(i,12)] = ROR(READ32(cpu->mem_if->data, adr), 8*(adr&3)); \ + \ + if(REG_POS(i,12)==15) \ + { \ + if (PROCNUM == 0) \ + { \ + cpu->CPSR.bits.T = BIT0(cpu->R[15]); \ + cpu->R[15] &= 0xFFFFFFFE; \ + } \ + else \ + { \ + cpu->R[15] &= 0xFFFFFFFC; \ + } \ + cpu->next_instruction = cpu->R[15]; \ + return MMU_aluMemAccessCycles(b,adr); \ + } \ + \ + return MMU_aluMemAccessCycles(a,adr); + +// POST +#define OP_LDR_W2(a, b, c) \ + u32 adr = cpu->R[REG_POS(i,16)]; \ + cpu->R[REG_POS(i,16)] = adr + c;\ + cpu->R[REG_POS(i,12)] = ROR(READ32(cpu->mem_if->data, adr), 8*(adr&3)); \ + \ + if(REG_POS(i,12)==15) \ + { \ + if (PROCNUM == 0) \ + { \ + cpu->CPSR.bits.T = BIT0(cpu->R[15]); \ + cpu->R[15] &= 0xFFFFFFFE; \ + } \ + else \ + { \ + cpu->R[15] &= 0xFFFFFFFC; \ + } \ + cpu->next_instruction = cpu->R[15]; \ + return MMU_aluMemAccessCycles(b,adr); \ + } \ + \ + return MMU_aluMemAccessCycles(a,adr); + TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - u32 val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,12)] = val; - return MMU_aluMemAccessCycles(3,adr); + OP_LDR(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - u32 val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + OP_LDR(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; + OP_LDR(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; + OP_LDR(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; + OP_LDR(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; + OP_LDR(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; + OP_LDR(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; + OP_LDR(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr; - INFO("OP_LDR_P_ROR_IMM_OFF\n"); - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; + OP_LDR(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr; - - return MMU_aluMemAccessCycles(3,adr); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; + OP_LDR(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_PREIND(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - u32 val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + OP_LDR_W(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF_PREIND(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - u32 val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - - return MMU_aluMemAccessCycles(3,adr); + OP_LDR_W(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - - return MMU_aluMemAccessCycles(3,adr); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; + OP_LDR_W(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - - return MMU_aluMemAccessCycles(3,adr); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; + OP_LDR_W(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - - return MMU_aluMemAccessCycles(3,adr); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; + OP_LDR_W(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - - return MMU_aluMemAccessCycles(3,adr); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; + OP_LDR_W(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - - return MMU_aluMemAccessCycles(3,adr); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; + OP_LDR_W(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - - return MMU_aluMemAccessCycles(3,adr); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; + OP_LDR_W(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - - return MMU_aluMemAccessCycles(3,adr); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; + OP_LDR_W(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; + OP_LDR_W(3, 5); } TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND(const u32 i) { - u32 adr = cpu->R[REG_POS(i,16)]; - u32 val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + OP_LDR_W2(3, 5, IMM_OFF_12); } -//------------------------------------------------------------ - TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF_POSTIND(const u32 i) { - u32 adr = cpu->R[REG_POS(i,16)]; - u32 val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + OP_LDR_W2(3, 5, -IMM_OFF_12); } TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr + shift_op; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + LSL_IMM; + OP_LDR_W2(3, 5, shift_op); } TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr - shift_op; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + LSL_IMM; + OP_LDR_W2(3, 5, -shift_op); } TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr + shift_op; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + OP_LDR_W2(3, 5, shift_op); } TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr - shift_op; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + OP_LDR_W2(3, 5, -shift_op); } TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr + shift_op; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + OP_LDR_W2(3, 5, shift_op); } TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr - shift_op; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + OP_LDR_W2(3, 5, -shift_op); } TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr + shift_op; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + OP_LDR_W2(3, 5, shift_op); } TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ32(cpu->mem_if->data, adr); - - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr - shift_op; - return MMU_aluMemAccessCycles(5,adr); - } - - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; - - return MMU_aluMemAccessCycles(3,adr); + OP_LDR_W2(3, 5, -shift_op); } //----------------------------------------------------------------------------- @@ -4333,8 +3901,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_POSTIND(const u32 i) TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - u32 val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } @@ -4342,115 +3909,79 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_LDRB_M_IMM_OFF(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - u32 val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr);; return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; + cpu->R[REG_POS(i,12)] = READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - INFO("OP_LDRB_P_ROR_IMM_OFF\n"); - cpu->R[REG_POS(i,16)] = adr; + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr; + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } @@ -4458,11 +3989,8 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF_PREIND(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - u32 val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } @@ -4470,125 +3998,88 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF_PREIND(const u32 i) TEMPLATE static u32 FASTCALL OP_LDRB_M_IMM_OFF_PREIND(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - u32 val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr);; return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ8(cpu->mem_if->data, adr); - + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ8(cpu->mem_if->data, adr); - + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ8(cpu->mem_if->data, adr); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ8(cpu->mem_if->data, adr); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ8(cpu->mem_if->data, adr); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ8(cpu->mem_if->data, adr); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ8(cpu->mem_if->data, adr); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ8(cpu->mem_if->data, adr); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } @@ -4596,9 +4087,8 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_PREIND(const u32 i) TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF_POSTIND(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)]; - u32 val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } @@ -4606,121 +4096,88 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF_POSTIND(const u32 i) TEMPLATE static u32 FASTCALL OP_LDRB_M_IMM_OFF_POSTIND(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)]; - u32 val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); + u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); + u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); + u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); + u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); + u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); + u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); + u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 val; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); + u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = (u32)READ8(cpu->mem_if->data, adr); return MMU_aluMemAccessCycles(3,adr); } @@ -4734,8 +4191,6 @@ TEMPLATE static u32 FASTCALL OP_STR_P_IMM_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); -// emu_halt(); - return MMU_aluMemAccessCycles(2,adr); } @@ -4749,10 +4204,8 @@ TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF(const u32 i) { - u32 adr; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); @@ -4760,10 +4213,8 @@ TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF(const u32 i) { - u32 adr; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); @@ -4771,10 +4222,8 @@ TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF(const u32 i) { - u32 adr; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); @@ -4782,10 +4231,8 @@ TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF(const u32 i) { - u32 adr; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); @@ -4793,10 +4240,8 @@ TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF(const u32 i) { - u32 adr; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); @@ -4804,10 +4249,8 @@ TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF(const u32 i) { - u32 adr; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); @@ -4815,25 +4258,18 @@ TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF(const u32 i) { - u32 adr; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - INFO("OP_STR_P_ROR_IMM_OFF\n"); - cpu->R[REG_POS(i,16)] = adr; return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF(const u32 i) { - u32 adr; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; return MMU_aluMemAccessCycles(2,adr); } @@ -4841,8 +4277,8 @@ TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STR_P_IMM_OFF_PREIND(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } @@ -4850,104 +4286,88 @@ TEMPLATE static u32 FASTCALL OP_STR_P_IMM_OFF_PREIND(const u32 i) TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF_PREIND(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; cpu->R[REG_POS(i,16)] = adr; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; cpu->R[REG_POS(i,16)] = adr; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; cpu->R[REG_POS(i,16)] = adr; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; cpu->R[REG_POS(i,16)] = adr; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; cpu->R[REG_POS(i,16)] = adr; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; cpu->R[REG_POS(i,16)] = adr; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; cpu->R[REG_POS(i,16)] = adr; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; cpu->R[REG_POS(i,16)] = adr; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } @@ -4972,10 +4392,8 @@ TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF_POSTIND(const u32 i) TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; + u32 adr = cpu->R[REG_POS(i,16)]; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; @@ -4984,10 +4402,8 @@ TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_POSTIND(const u32 i) TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; + u32 adr = cpu->R[REG_POS(i,16)]; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; @@ -4996,10 +4412,8 @@ TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_POSTIND(const u32 i) TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; + u32 adr = cpu->R[REG_POS(i,16)]; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; @@ -5008,10 +4422,8 @@ TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_POSTIND(const u32 i) TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; + u32 adr = cpu->R[REG_POS(i,16)]; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; @@ -5020,10 +4432,8 @@ TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_POSTIND(const u32 i) TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; + u32 adr = cpu->R[REG_POS(i,16)]; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; @@ -5032,10 +4442,8 @@ TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_POSTIND(const u32 i) TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; + u32 adr = cpu->R[REG_POS(i,16)]; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; @@ -5044,10 +4452,8 @@ TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_POSTIND(const u32 i) TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; + u32 adr = cpu->R[REG_POS(i,16)]; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; @@ -5056,10 +4462,8 @@ TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_POSTIND(const u32 i) TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; + u32 adr = cpu->R[REG_POS(i,16)]; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; @@ -5088,10 +4492,8 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF(const u32 i) { - u32 adr; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); @@ -5099,10 +4501,8 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF(const u32 i) { - u32 adr; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); @@ -5110,10 +4510,8 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF(const u32 i) { - u32 adr; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); @@ -5121,10 +4519,8 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF(const u32 i) { - u32 adr; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); @@ -5132,10 +4528,8 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF(const u32 i) { - u32 adr; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); @@ -5143,10 +4537,8 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF(const u32 i) { - u32 adr; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); @@ -5154,10 +4546,8 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF(const u32 i) { - u32 adr; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); @@ -5165,10 +4555,8 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF(const u32 i) { - u32 adr; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); @@ -5177,8 +4565,8 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STRB_P_IMM_OFF_PREIND(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - WRITE8(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } @@ -5186,104 +4574,88 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_IMM_OFF_PREIND(const u32 i) TEMPLATE static u32 FASTCALL OP_STRB_M_IMM_OFF_PREIND(const u32 i) { u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; cpu->R[REG_POS(i,16)] = adr; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; cpu->R[REG_POS(i,16)] = adr; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; cpu->R[REG_POS(i,16)] = adr; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; cpu->R[REG_POS(i,16)] = adr; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; cpu->R[REG_POS(i,16)] = adr; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; cpu->R[REG_POS(i,16)] = adr; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + u32 adr = cpu->R[REG_POS(i,16)] + shift_op; cpu->R[REG_POS(i,16)] = adr; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_PREIND(const u32 i) { - u32 adr; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + u32 adr = cpu->R[REG_POS(i,16)] - shift_op; cpu->R[REG_POS(i,16)] = adr; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return MMU_aluMemAccessCycles(2,adr); } @@ -5308,10 +4680,8 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_IMM_OFF_POSTIND(const u32 i) TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; + u32 adr = cpu->R[REG_POS(i,16)]; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; @@ -5320,10 +4690,8 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_POSTIND(const u32 i) TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 shift_op; LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; + u32 adr = cpu->R[REG_POS(i,16)]; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; @@ -5332,10 +4700,8 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_POSTIND(const u32 i) TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; + u32 adr = cpu->R[REG_POS(i,16)]; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; @@ -5344,10 +4710,8 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_POSTIND(const u32 i) TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 shift_op; LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; + u32 adr = cpu->R[REG_POS(i,16)]; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; @@ -5356,10 +4720,8 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_POSTIND(const u32 i) TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; + u32 adr = cpu->R[REG_POS(i,16)]; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; @@ -5368,10 +4730,8 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_POSTIND(const u32 i) TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 shift_op; ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; + u32 adr = cpu->R[REG_POS(i,16)]; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; @@ -5380,10 +4740,8 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_POSTIND(const u32 i) TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; + u32 adr = cpu->R[REG_POS(i,16)]; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; @@ -5392,10 +4750,8 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_POSTIND(const u32 i) TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) { - u32 adr; - u32 shift_op; ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; + u32 adr = cpu->R[REG_POS(i,16)]; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; @@ -5460,8 +4816,28 @@ TEMPLATE static u32 FASTCALL OP_LDMIA(const u32 i) if(BIT15(i)) { u32 tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR.bits.T = BIT0(tmp); + // TODO + // The general-purpose registers loaded can include the PC. If they do, the word loaded for the PC is treated + // as an address and a branch occurs to that address. In ARMv5 and above, bit[0] of the loaded value + // determines whether execution continues after this branch in ARM state or in Thumb state, as though a BX + // (loaded_value) instruction had been executed (but see also The T and J bits on page A2-15 for operation on + // non-T variants of ARMv5). In earlier versions of the architecture, bits[1:0] of the loaded value are ignored + // and execution continues in ARM state, as though the instruction MOV PC,(loaded_value) had been executed. + // + //value = Memory[address,4] + //if (architecture version 5 or above) then + // pc = value AND 0xFFFFFFFE + // T Bit = value[0] + //else + // pc = value AND 0xFFFFFFFC + if (PROCNUM == 0) + { + cpu->CPSR.bits.T = BIT0(tmp); + registres[15] = tmp & 0xFFFFFFFE; + } + else + registres[15] = tmp & 0xFFFFFFFC; + //start += 4; cpu->next_instruction = registres[15]; c += MMU_memAccessCycles(start); @@ -5495,12 +4871,16 @@ TEMPLATE static u32 FASTCALL OP_LDMIB(const u32 i) if(BIT15(i)) { - u32 tmp; start += 4; c += MMU_memAccessCycles(start); - tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR.bits.T = BIT0(tmp); + u32 tmp = READ32(cpu->mem_if->data, start); + if (PROCNUM == 0) + { + cpu->CPSR.bits.T = BIT0(tmp); + registres[15] = tmp & 0xFFFFFFFE; + } + else + registres[15] = tmp & 0xFFFFFFFC; cpu->next_instruction = registres[15]; return MMU_aluMemCycles(4, c); } @@ -5518,8 +4898,13 @@ TEMPLATE static u32 FASTCALL OP_LDMDA(const u32 i) if(BIT15(i)) { u32 tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR.bits.T = BIT0(tmp); + if (PROCNUM == 0) + { + cpu->CPSR.bits.T = BIT0(tmp); + registres[15] = tmp & 0xFFFFFFFE; + } + else + registres[15] = tmp & 0xFFFFFFFC; c += MMU_memAccessCycles(start); start -= 4; cpu->next_instruction = registres[15]; @@ -5553,11 +4938,15 @@ TEMPLATE static u32 FASTCALL OP_LDMDB(const u32 i) if(BIT15(i)) { - u32 tmp; start -= 4; - tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR.bits.T = BIT0(tmp); + u32 tmp = READ32(cpu->mem_if->data, start); + if (PROCNUM == 0) + { + cpu->CPSR.bits.T = BIT0(tmp); + registres[15] = tmp & 0xFFFFFFFE; + } + else + registres[15] = tmp & 0xFFFFFFFC; cpu->next_instruction = registres[15]; c += MMU_memAccessCycles(start); } @@ -5608,8 +4997,13 @@ TEMPLATE static u32 FASTCALL OP_LDMIA_W(const u32 i) if(BIT15(i)) { u32 tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR.bits.T = BIT0(tmp); + if (PROCNUM == 0) + { + cpu->CPSR.bits.T = BIT0(tmp); + registres[15] = tmp & 0xFFFFFFFE; + } + else + registres[15] = tmp & 0xFFFFFFFC; c += MMU_memAccessCycles(start); start += 4; cpu->next_instruction = registres[15]; @@ -5655,9 +5049,14 @@ TEMPLATE static u32 FASTCALL OP_LDMIB_W(const u32 i) start += 4; c += MMU_memAccessCycles(start); tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR.bits.T = BIT0(tmp); - cpu->next_instruction = registres[15]; + if (PROCNUM == 0) + { + cpu->CPSR.bits.T = BIT0(tmp); + registres[15] = tmp & 0xFFFFFFFE; + } + else + registres[15] = tmp & 0xFFFFFFFC; + cpu->next_instruction = registres[15]; } if(i & (1 << REG_POS(i,16))) { @@ -5684,8 +5083,13 @@ TEMPLATE static u32 FASTCALL OP_LDMDA_W(const u32 i) if(BIT15(i)) { u32 tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR.bits.T = BIT0(tmp); + if (PROCNUM == 0) + { + cpu->CPSR.bits.T = BIT0(tmp); + registres[15] = tmp & 0xFFFFFFFE; + } + else + registres[15] = tmp & 0xFFFFFFFC; c += MMU_memAccessCycles(start); start -= 4; cpu->next_instruction = registres[15]; @@ -5729,8 +5133,13 @@ TEMPLATE static u32 FASTCALL OP_LDMDB_W(const u32 i) u32 tmp; start -= 4; tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR.bits.T = BIT0(tmp); + if (PROCNUM == 0) + { + cpu->CPSR.bits.T = BIT0(tmp); + registres[15] = tmp & 0xFFFFFFFE; + } + else + registres[15] = tmp & 0xFFFFFFFC; cpu->next_instruction = registres[15]; c += MMU_memAccessCycles(start); } @@ -5764,7 +5173,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDB_W(const u32 i) TEMPLATE static u32 FASTCALL OP_LDMIA2(const u32 i) { u32 oldmode = 0; - + u32 c = 0; u32 start = cpu->R[REG_POS(i,16)]; @@ -5772,8 +5181,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2(const u32 i) if(BIT15(i)==0) { - if(cpu->CPSR.bits.mode==USR) - return 1; + if((cpu->CPSR.bits.mode==USR)||(cpu->CPSR.bits.mode==SYS)) { printf("ERROR1\n"); return 1; } oldmode = armcpu_switchMode(cpu, SYS); } @@ -5828,8 +5236,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2(const u32 i) if(BIT15(i)==0) { - if(cpu->CPSR.bits.mode==USR) - return 2; + if((cpu->CPSR.bits.mode==USR)||(cpu->CPSR.bits.mode==SYS)) { printf("ERROR1\n"); return 1; } oldmode = armcpu_switchMode(cpu, SYS); } @@ -5885,8 +5292,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDA2(const u32 i) if(BIT15(i)==0) { - if(cpu->CPSR.bits.mode==USR) - return 2; + if((cpu->CPSR.bits.mode==USR)||(cpu->CPSR.bits.mode==SYS)) { printf("ERROR1\n"); return 1; } oldmode = armcpu_switchMode(cpu, SYS); } @@ -5943,8 +5349,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDB2(const u32 i) u32 start = cpu->R[REG_POS(i,16)]; if(BIT15(i)==0) { - if(cpu->CPSR.bits.mode==USR) - return 2; + if((cpu->CPSR.bits.mode==USR)||(cpu->CPSR.bits.mode==SYS)) { printf("ERROR1\n"); return 1; } oldmode = armcpu_switchMode(cpu, SYS); } @@ -6005,8 +5410,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2_W(const u32 i) // emu_halt(); if(BIT15(i)==0) { - if(cpu->CPSR.bits.mode==USR) - return 2; + if((cpu->CPSR.bits.mode==USR)||(cpu->CPSR.bits.mode==SYS)) { printf("ERROR1\n"); return 1; } oldmode = armcpu_switchMode(cpu, SYS); } @@ -6030,12 +5434,14 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2_W(const u32 i) if(BIT15(i)==0) { - registres[REG_POS(i,16)] = start; + if (!BIT_N(i, REG_POS(i,16))) + registres[REG_POS(i,16)] = start; armcpu_switchMode(cpu, oldmode); return MMU_aluMemCycles(2, c); } - registres[REG_POS(i,16)] = start + 4; + if (!BIT_N(i, REG_POS(i,16))) + registres[REG_POS(i,16)] = start + 4; tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); SPSR = cpu->SPSR; @@ -6060,8 +5466,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2_W(const u32 i) if(BIT15(i)==0) { - if(cpu->CPSR.bits.mode==USR) - return 2; + if((cpu->CPSR.bits.mode==USR)||(cpu->CPSR.bits.mode==SYS)) { printf("ERROR1\n"); return 1; } oldmode = armcpu_switchMode(cpu, SYS); } @@ -6085,13 +5490,15 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2_W(const u32 i) if(BIT15(i)==0) { + if (!BIT_N(i, REG_POS(i,16))) + registres[REG_POS(i,16)] = start; armcpu_switchMode(cpu, oldmode); - registres[REG_POS(i,16)] = start; return MMU_aluMemCycles(2, c); } - registres[REG_POS(i,16)] = start + 4; + if (!BIT_N(i, REG_POS(i,16))) + registres[REG_POS(i,16)] = start + 4; tmp = READ32(cpu->mem_if->data, start + 4); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR = cpu->SPSR; @@ -6117,8 +5524,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDA2_W(const u32 i) // emu_halt(); if(BIT15(i)==0) { - if(cpu->CPSR.bits.mode==USR) - return 2; + if((cpu->CPSR.bits.mode==USR)||(cpu->CPSR.bits.mode==SYS)) { printf("ERROR1\n"); return 1; } oldmode = armcpu_switchMode(cpu, SYS); } @@ -6126,6 +5532,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDA2_W(const u32 i) if(BIT15(i)) { + if (BIT_N(i, REG_POS(i,16))) printf("error1_1\n"); u32 tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); c += MMU_memAccessCycles(start); @@ -6149,7 +5556,8 @@ TEMPLATE static u32 FASTCALL OP_LDMDA2_W(const u32 i) OP_L_DA(1, start); OP_L_DA(0, start); - registres[REG_POS(i,16)] = start; + if (!BIT_N(i, REG_POS(i,16))) + registres[REG_POS(i,16)] = start; if(BIT15(i)==0) { @@ -6175,8 +5583,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDB2_W(const u32 i) // emu_halt(); if(BIT15(i)==0) { - if(cpu->CPSR.bits.mode==USR) - return 2; + if((cpu->CPSR.bits.mode==USR)||(cpu->CPSR.bits.mode==SYS)) { printf("ERROR1\n"); return 1; } oldmode = armcpu_switchMode(cpu, SYS); } @@ -6184,6 +5591,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDB2_W(const u32 i) if(BIT15(i)) { + if (BIT_N(i, REG_POS(i,16))) printf("error1_2\n"); u32 tmp; start -= 4; tmp = READ32(cpu->mem_if->data, start); @@ -6210,7 +5618,8 @@ TEMPLATE static u32 FASTCALL OP_LDMDB2_W(const u32 i) OP_L_DB(1, start); OP_L_DB(0, start); - registres[REG_POS(i,16)] = start; + if (!BIT_N(i, REG_POS(i,16))) + registres[REG_POS(i,16)] = start; if(BIT15(i)==0) { @@ -6229,12 +5638,12 @@ TEMPLATE static u32 FASTCALL OP_LDMDB2_W(const u32 i) // STMIA / STMIB / STMDA / STMDB //----------------------------------------------------------------------------- -TEMPLATE static u32 FASTCALL OP_STMIA(const u32 i) +TEMPLATE static u32 FASTCALL OP_STMIA(const u32 i) { u32 c = 0, b; u32 start = cpu->R[REG_POS(i,16)]; - for(b=0; b<16; ++b) + for(b=0; b<16; b++) { if(BIT_N(i, b)) { @@ -6251,7 +5660,7 @@ TEMPLATE static u32 FASTCALL OP_STMIB(const u32 i) u32 c = 0, b; u32 start = cpu->R[REG_POS(i,16)]; - for(b=0; b<16; ++b) + for(b=0; b<16; b++) { if(BIT_N(i, b)) { @@ -6268,7 +5677,7 @@ TEMPLATE static u32 FASTCALL OP_STMDA(const u32 i) u32 c = 0, b; u32 start = cpu->R[REG_POS(i,16)]; - for(b=0; b<16; ++b) + for(b=0; b<16; b++) { if(BIT_N(i, 15-b)) { @@ -6285,7 +5694,7 @@ TEMPLATE static u32 FASTCALL OP_STMDB(const u32 i) u32 c = 0, b; u32 start = cpu->R[REG_POS(i,16)]; - for(b=0; b<16; ++b) + for(b=0; b<16; b++) { if(BIT_N(i, 15-b)) { @@ -6302,7 +5711,7 @@ TEMPLATE static u32 FASTCALL OP_STMIA_W(const u32 i) u32 c = 0, b; u32 start = cpu->R[REG_POS(i,16)]; - for(b=0; b<16; ++b) + for(b=0; b<16; b++) { if(BIT_N(i, b)) { @@ -6321,7 +5730,7 @@ TEMPLATE static u32 FASTCALL OP_STMIB_W(const u32 i) u32 c = 0, b; u32 start = cpu->R[REG_POS(i,16)]; - for(b=0; b<16; ++b) + for(b=0; b<16; b++) { if(BIT_N(i, b)) { @@ -6339,7 +5748,7 @@ TEMPLATE static u32 FASTCALL OP_STMDA_W(const u32 i) u32 c = 0, b; u32 start = cpu->R[REG_POS(i,16)]; - for(b=0; b<16; ++b) + for(b=0; b<16; b++) { if(BIT_N(i, 15-b)) { @@ -6358,7 +5767,7 @@ TEMPLATE static u32 FASTCALL OP_STMDB_W(const u32 i) u32 c = 0, b; u32 start = cpu->R[REG_POS(i,16)]; - for(b=0; b<16; ++b) + for(b=0; b<16; b++) { if(BIT_N(i, 15-b)) { @@ -6387,7 +5796,7 @@ TEMPLATE static u32 FASTCALL OP_STMIA2(const u32 i) UNTESTEDOPCODELOG("Untested opcode: OP_STMIA2 \n"); - for(b=0; b<16; ++b) + for(b=0; b<16; b++) { if(BIT_N(i, b)) { @@ -6416,7 +5825,7 @@ TEMPLATE static u32 FASTCALL OP_STMIB2(const u32 i) UNTESTEDOPCODELOG("Untested opcode: OP_STMIB2 \n"); - for(b=0; b<16; ++b) + for(b=0; b<16; b++) { if(BIT_N(i, b)) { @@ -6445,7 +5854,7 @@ TEMPLATE static u32 FASTCALL OP_STMDA2(const u32 i) UNTESTEDOPCODELOG("Untested opcode: OP_STMDA2 \n"); - for(b=0; b<16; ++b) + for(b=0; b<16; b++) { if(BIT_N(i, 15-b)) { @@ -6472,7 +5881,7 @@ TEMPLATE static u32 FASTCALL OP_STMDB2(const u32 i) start = cpu->R[REG_POS(i,16)]; oldmode = armcpu_switchMode(cpu, SYS); - for(b=0; b<16; ++b) + for(b=0; b<16; b++) { if(BIT_N(i, 15-b)) { @@ -6501,7 +5910,7 @@ TEMPLATE static u32 FASTCALL OP_STMIA2_W(const u32 i) UNTESTEDOPCODELOG("Untested opcode: OP_STMIA2_W \n"); - for(b=0; b<16; ++b) + for(b=0; b<16; b++) { if(BIT_N(i, b)) { @@ -6529,7 +5938,7 @@ TEMPLATE static u32 FASTCALL OP_STMIB2_W(const u32 i) start = cpu->R[REG_POS(i,16)]; oldmode = armcpu_switchMode(cpu, SYS); - for(b=0; b<16; ++b) + for(b=0; b<16; b++) { if(BIT_N(i, b)) { @@ -6559,7 +5968,7 @@ TEMPLATE static u32 FASTCALL OP_STMDA2_W(const u32 i) UNTESTEDOPCODELOG("Untested opcode: OP_STMDA2_W \n"); - for(b=0; b<16; ++b) + for(b=0; b<16; b++) { if(BIT_N(i, 15-b)) { @@ -6591,7 +6000,7 @@ TEMPLATE static u32 FASTCALL OP_STMDB2_W(const u32 i) UNTESTEDOPCODELOG("Untested opcode: OP_STMDB2_W \n"); - for(b=0; b<16; ++b) + for(b=0; b<16; b++) { if(BIT_N(i, 15-b)) { @@ -6616,14 +6025,14 @@ TEMPLATE static u32 FASTCALL OP_LDRD_STRD_POST_INDEX(const u32 i) u32 Rd_num = REG_POS( i, 12); u32 addr = cpu->R[REG_POS(i,16)]; u32 index; - + //printf("%s POST\n", BIT5(i)?"STRD":"LDRD"); /* I bit - immediate or register */ if ( BIT22(i)) index = IMM_OFF; else index = cpu->R[REG_POS(i,0)]; - /* U bit - add or subtract */ + // U bit - add or subtract if ( BIT23(i)) cpu->R[REG_POS(i,16)] += index; else @@ -6632,7 +6041,7 @@ TEMPLATE static u32 FASTCALL OP_LDRD_STRD_POST_INDEX(const u32 i) u32 c = 0; if ( !(Rd_num & 0x1)) { - /* Store/Load */ + // Store/Load if ( BIT5(i)) { WRITE32(cpu->mem_if->data, addr, cpu->R[Rd_num]); @@ -6658,43 +6067,38 @@ TEMPLATE static u32 FASTCALL OP_LDRD_STRD_OFFSET_PRE_INDEX(const u32 i) u32 addr = cpu->R[REG_POS(i,16)]; u32 index; - /* I bit - immediate or register */ + //printf("%s PRE\n", BIT5(i)?"STRD":"LDRD"); + // I bit - immediate or register if ( BIT22(i)) index = IMM_OFF; else index = cpu->R[REG_POS(i,0)]; - /* U bit - add or subtract */ + // U bit - add or subtract if ( BIT23(i)) - { addr += index; - - /* W bit - writeback */ - if ( BIT21(i)) - cpu->R[REG_POS(i,16)] = addr; - } else - { addr -= index; - /* W bit - writeback */ - if ( BIT21(i)) - cpu->R[REG_POS(i,16)] = addr; - } - u32 c = 0; if ( !(Rd_num & 0x1)) { - /* Store/Load */ + // Store/Load if ( BIT5(i)) { WRITE32(cpu->mem_if->data, addr, cpu->R[Rd_num]); WRITE32(cpu->mem_if->data, addr + 4, cpu->R[Rd_num + 1]); c += MMU_memAccessCycles(addr); c += MMU_memAccessCycles(addr + 4); + // W bit - writeback + if ( BIT21(i)) + cpu->R[REG_POS(i,16)] = addr; } else { + // W bit - writeback + if ( BIT21(i)) + cpu->R[REG_POS(i,16)] = addr; cpu->R[Rd_num] = READ32(cpu->mem_if->data, addr); cpu->R[Rd_num + 1] = READ32(cpu->mem_if->data, addr + 4); c += MMU_memAccessCycles(addr); @@ -6705,8 +6109,6 @@ TEMPLATE static u32 FASTCALL OP_LDRD_STRD_OFFSET_PRE_INDEX(const u32 i) return MMU_aluMemCycles(3, c); } - - //----------------------------------------------------------------------------- // STC // the NDS has no coproc that responses to a STC, no feedback is given to the arm @@ -6714,36 +6116,45 @@ TEMPLATE static u32 FASTCALL OP_LDRD_STRD_OFFSET_PRE_INDEX(const u32 i) TEMPLATE static u32 FASTCALL OP_STC_P_IMM_OFF(const u32 i) { + //INFO("OP_STC_P_IMM_OFF\n"); return TRAPUNDEF(cpu); } TEMPLATE static u32 FASTCALL OP_STC_M_IMM_OFF(const u32 i) { + //INFO("OP_STC_M_IMM_OFF\n"); return TRAPUNDEF(cpu); } TEMPLATE static u32 FASTCALL OP_STC_P_PREIND(const u32 i) { + //INFO("OP_STC_P_PREIND\n"); return TRAPUNDEF(cpu); } TEMPLATE static u32 FASTCALL OP_STC_M_PREIND(const u32 i) { + //INFO("OP_STC_M_PREIND\n"); return TRAPUNDEF(cpu); } TEMPLATE static u32 FASTCALL OP_STC_P_POSTIND(const u32 i) { + //INFO("OP_STC_P_POSTIND: cp_num %i\n", (i>>8)&0x0F); return TRAPUNDEF(cpu); + + } TEMPLATE static u32 FASTCALL OP_STC_M_POSTIND(const u32 i) { + //INFO("OP_STC_M_POSTIND\n"); return TRAPUNDEF(cpu); } TEMPLATE static u32 FASTCALL OP_STC_OPTION(const u32 i) { + //INFO("OP_STC_OPTION\n"); return TRAPUNDEF(cpu); } @@ -6754,36 +6165,43 @@ TEMPLATE static u32 FASTCALL OP_STC_OPTION(const u32 i) TEMPLATE static u32 FASTCALL OP_LDC_P_IMM_OFF(const u32 i) { + //INFO("OP_LDC_P_IMM_OFF\n"); return TRAPUNDEF(cpu); } TEMPLATE static u32 FASTCALL OP_LDC_M_IMM_OFF(const u32 i) { + //INFO("OP_LDC_M_IMM_OFF\n"); return TRAPUNDEF(cpu); } TEMPLATE static u32 FASTCALL OP_LDC_P_PREIND(const u32 i) { + //INFO("OP_LDC_P_PREIND\n"); return TRAPUNDEF(cpu); } TEMPLATE static u32 FASTCALL OP_LDC_M_PREIND(const u32 i) { + //INFO("OP_LDC_M_PREIND\n"); return TRAPUNDEF(cpu); } TEMPLATE static u32 FASTCALL OP_LDC_P_POSTIND(const u32 i) { + //INFO("OP_LDC_P_POSTIND\n"); return TRAPUNDEF(cpu); } TEMPLATE static u32 FASTCALL OP_LDC_M_POSTIND(const u32 i) { + //INFO("OP_LDC_M_POSTIND\n"); return TRAPUNDEF(cpu); } TEMPLATE static u32 FASTCALL OP_LDC_OPTION(const u32 i) { + //INFO("OP_LDC_OPTION\n"); return TRAPUNDEF(cpu); } @@ -6794,31 +6212,55 @@ TEMPLATE static u32 FASTCALL OP_LDC_OPTION(const u32 i) TEMPLATE static u32 FASTCALL OP_MCR(const u32 i) { u32 cpnum = REG_POS(i, 8); - + if(!cpu->coproc[cpnum]) { - emu_halt(); - LOG("Stopped (OP_MCR) \n"); + //emu_halt(); + //INFO("Stopped (OP_MCR) \n"); + INFO("ARM%c: MCR P%i, 0, R%i, C%i, C%i, %i, %i (don't allocated coprocessor)\n", + PROCNUM?'7':'9', cpnum, REG_POS(i, 12), REG_POS(i, 16), REG_POS(i, 0), (i>>21)&0x7, (i>>5)&0x7); return 2; } - armcp15_moveARM2CP((armcp15_t*)cpu->coproc[cpnum], cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7); + armcp15_moveARM2CP((armcp15_t*)cpu->coproc[cpnum], cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&0x7, (i>>5)&0x7); //cpu->coproc[cpnum]->moveARM2CP(cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7); return 2; } TEMPLATE static u32 FASTCALL OP_MRC(const u32 i) { + //if (PROCNUM != 0) return 1; + u32 cpnum = REG_POS(i, 8); if(!cpu->coproc[cpnum]) { - emu_halt(); - LOG("Stopped (OP_MRC) \n"); + //emu_halt(); + //INFO("Stopped (OP_MRC) \n"); + INFO("ARM%c: MRC P%i, 0, R%i, C%i, C%i, %i, %i (don't allocated coprocessor)\n", + PROCNUM?'7':'9', cpnum, REG_POS(i, 12), REG_POS(i, 16), REG_POS(i, 0), (i>>21)&0x7, (i>>5)&0x7); return 2; } + + // ARM REF: + //data = value from Coprocessor[cp_num] + //if Rd is R15 then + // N flag = data[31] + // Z flag = data[30] + // C flag = data[29] + // V flag = data[28] + //else /* Rd is not R15 */ + // Rd = data - armcp15_moveCP2ARM((armcp15_t*)cpu->coproc[cpnum], &cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7); + armcp15_moveCP2ARM((armcp15_t*)cpu->coproc[cpnum], &cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&0x7, (i>>5)&0x7); + if (REG_POS(i, 12) == 15) + { + u32 Rd = cpu->R[REG_POS(i, 12)]; + cpu->CPSR.bits.N = BIT31(Rd); + cpu->CPSR.bits.Z = BIT30(Rd); + cpu->CPSR.bits.C = BIT29(Rd); + cpu->CPSR.bits.V = BIT28(Rd); + } //cpu->coproc[cpnum]->moveCP2ARM(&cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7); return 4; } @@ -6829,7 +6271,7 @@ TEMPLATE static u32 FASTCALL OP_MRC(const u32 i) TEMPLATE static u32 FASTCALL OP_SWI(const u32 i) { - u32 swinum = (cpu->instruction>>16)&0xFF; + u32 swinum = (i>>16)&0xFF; //ideas-style debug prints (execute this SWI with the null terminated string address in R0) if(swinum==0xFC) @@ -6891,7 +6333,7 @@ TEMPLATE static u32 FASTCALL OP_BKPT(const u32 i) TEMPLATE static u32 FASTCALL OP_CDP(const u32 i) { - LOG("Stopped (OP_CDP) \n"); + //INFO("Stopped (OP_CDP) \n"); return TRAPUNDEF(cpu); } diff --git a/desmume/src/armcpu.h b/desmume/src/armcpu.h index 4e367eb01..5fc87e59d 100644 --- a/desmume/src/armcpu.h +++ b/desmume/src/armcpu.h @@ -24,6 +24,7 @@ #include "types.h" #include "bits.h" #include "MMU.h" +#include "common.h" #define CODE(i) (((i)>>25)&0x7) #define OPCODE(i) (((i)>>21)&0xF) @@ -54,6 +55,31 @@ inline T SIGNED_OVERFLOW(T a,T b,T c) { return BIT31(((a)&(b)&(~c)) | ((~a)&(~(b template inline T SIGNED_UNDERFLOW(T a,T b,T c) { return BIT31(((a)&(~(b))&(~c)) | ((~a)&(b)&(c))); } +// ============================= CPRS flags funcs +inline bool CarryFrom(s32 left, s32 right) +{ + u32 res = (0xFFFFFFFFU - (u32)left); + + return ((u32)right > res); +} + +inline bool BorrowFrom(s32 left, s32 right) +{ + return ((u32)right > (u32)left); +} + +inline bool OverflowFromADD(s32 alu_out, s32 left, s32 right) +{ + return ((left >= 0 && right >= 0) || (left < 0 && right < 0)) + && ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0)); +} + +inline bool OverflowFromSUB(s32 alu_out, s32 left, s32 right) +{ + return ((left < 0 && right >= 0) || (left >= 0 && right < 0)) + && ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0)); +} + //zero 15-feb-2009 - these werent getting used and they were getting in my way //#define EQ 0x0 //#define NE 0x1 @@ -272,4 +298,22 @@ static INLINE void NDS_makeInt(u8 proc_ID,u32 num) } } + +static INLINE char *decodeIntruction(bool thumb_mode, u32 instr) +{ + char txt[20] = {0}; + u32 tmp = 0; + if (thumb_mode == true) + { + tmp = (instr >> 6); + strcpy(txt, intToBin((u16)tmp)+6); + } + else + { + tmp = ((instr >> 16) & 0x0FF0) | ((instr >> 4) & 0x0F); + strcpy(txt, intToBin((u32)tmp)+20); + } + return strdup(txt); +} + #endif diff --git a/desmume/src/common.cpp b/desmume/src/common.cpp index f6ba3f7d9..4677c8fce 100644 --- a/desmume/src/common.cpp +++ b/desmume/src/common.cpp @@ -37,20 +37,6 @@ const u8 logo_data[156] = { 0x78,0x00,0x90,0xCB,0x88,0x11,0x3A,0x94,0x65,0xC0,0x7C,0x63,0x87,0xF0,0x3C,0xAF, 0xD6,0x25,0xE4,0x8B,0x38,0x0A,0xAC,0x72,0x21,0xD4,0xF8,0x07}; -u8 reverseBitsInByte(u8 x) -{ - u8 h = 0; - u8 i = 0; - - for (i = 0; i < 8; i++) - { - h = (h << 1) + (x & 1); - x >>= 1; - } - - return h; -} - char *trim(char *s) { char *ptr = NULL; diff --git a/desmume/src/common.h b/desmume/src/common.h index d27ed978a..d58b933bf 100644 --- a/desmume/src/common.h +++ b/desmume/src/common.h @@ -56,7 +56,32 @@ extern const u8 logo_data[156]; #endif -extern u8 reverseBitsInByte(u8 x); +template +T reverseBits(T x) +{ + T h = 0; + T i = 0; + + for (i = 0; i < sizeof(T)*8; i++) + { + h = (h << 1) + (x & 1); + x >>= 1; + } + + return h; +} + +template +char *intToBin(T val) +{ + char buf[256] = {0}; + for (int i = sizeof(T)*8, t = 0; i > 0; --i, t++) + { + buf[i-1] = (val & (1<>n)&0x7) -// ============================= CPRS flags funcs -static bool CarryFrom(s32 left, s32 right) -{ - u32 res = (0xFFFFFFFF - (u32)left); - - return ((u32)right > res); -} - -static bool BorrowFrom(s32 left, s32 right) -{ - return ((u32)right > (u32)left); -} - -static bool OverflowFromADD(s32 alu_out, s32 left, s32 right) -{ - return ((left >= 0 && right >= 0) || (left < 0 && right < 0)) - && ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0)); -} - -static bool OverflowFromSUB(s32 alu_out, s32 left, s32 right) -{ - return ((left < 0 && right >= 0) || (left >= 0 && right < 0)) - && ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0)); -} - //----------------------------------------------------------------------------- // Undefined instruction //----------------------------------------------------------------------------- - TEMPLATE static u32 FASTCALL OP_UND_THUMB(const u32 i) { - INFO("THUMB%c: Undefined instruction: 0x%08X PC=0x%08X.\n", cpu->proc_ID?'7':'9', cpu->instruction, cpu->instruct_adr); + INFO("THUMB%c: Undefined instruction: 0x%08X (%s) PC=0x%08X\n", cpu->proc_ID?'7':'9', cpu->instruction, decodeIntruction(true, cpu->instruction), cpu->instruct_adr); TRAPUNDEF(cpu); return 1; } @@ -469,12 +443,19 @@ TEMPLATE static u32 FASTCALL OP_ADC_REG(const u32 i) u32 Rd = cpu->R[REG_NUM(i, 0)]; u32 Rm = cpu->R[REG_NUM(i, 3)]; - cpu->R[REG_NUM(i, 0)] = Rd + Rm + cpu->CPSR.bits.C; - + if (!cpu->CPSR.bits.C) + { + cpu->R[REG_NUM(i, 0)] = Rd + Rm; + cpu->CPSR.bits.C = cpu->R[REG_NUM(i, 0)] < Rm; + } + else + { + cpu->R[REG_NUM(i, 0)] = Rd + Rm + 1; + cpu->CPSR.bits.C = cpu->R[REG_NUM(i, 0)] <= Rm; + } cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 0)] == 0); - cpu->CPSR.bits.V = OverflowFromADD(cpu->R[REG_NUM(i, 0)], Rd, Rm + cpu->CPSR.bits.C); - cpu->CPSR.bits.C = CarryFrom(Rd, Rm + cpu->CPSR.bits.C); + cpu->CPSR.bits.V = (Rd ^ Rm ^ -1) & (Rd ^ cpu->R[REG_NUM(i, 0)]) != 0; return 1; } @@ -482,18 +463,25 @@ TEMPLATE static u32 FASTCALL OP_ADC_REG(const u32 i) //----------------------------------------------------------------------------- // SBC //----------------------------------------------------------------------------- - TEMPLATE static u32 FASTCALL OP_SBC_REG(const u32 i) { u32 Rd = cpu->R[REG_NUM(i, 0)]; u32 Rm = cpu->R[REG_NUM(i, 3)]; - cpu->R[REG_NUM(i, 0)] = Rd - Rm - !cpu->CPSR.bits.C; + if (!cpu->CPSR.bits.C) + { + cpu->R[REG_NUM(i, 0)] = Rd - Rm - 1; + cpu->CPSR.bits.C = Rd > Rm; + } + else + { + cpu->R[REG_NUM(i, 0)] = Rd - Rm; + cpu->CPSR.bits.C = Rd >= Rm; + } cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 0)] == 0); - cpu->CPSR.bits.V = OverflowFromSUB(cpu->R[REG_NUM(i, 0)], Rd, Rm - !cpu->CPSR.bits.C); - cpu->CPSR.bits.C = !BorrowFrom(Rd, Rm - !cpu->CPSR.bits.C); + cpu->CPSR.bits.V = ((Rd ^ Rm) & (Rd ^ cpu->R[REG_NUM(i, 0)])) != 0; return 1; } @@ -902,6 +890,13 @@ TEMPLATE static u32 FASTCALL OP_POP(const u32 i) return MMU_aluMemCycles(2, c); } +// In ARMv5 and above, bit[0] of the loaded value +// determines whether execution continues after this branch in ARM state or in Thumb state, as though the +// following instruction had been executed: +// BX (loaded_value) +// In T variants of ARMv4, bit[0] of the loaded value is ignored and execution continues in Thumb state, as +// though the following instruction had been executed: +// MOV PC,(loaded_value) TEMPLATE static u32 FASTCALL OP_POP_PC(const u32 i) { u32 adr = cpu->R[13];