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tried to correct structures packing (so that they take desired size)

This commit is contained in:
damdoum 2007-02-23 13:24:06 +00:00
parent 2eb5656ce6
commit cd488f63d6
2 changed files with 157 additions and 111 deletions
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95
desmume/src/GPU.c
View File

@ -205,7 +205,7 @@ void GPU_resortBGs(GPU *gpu)
for (i=NB_BG,j=0; i>0; ) { for (i=NB_BG,j=0; i>0; ) {
i--; i--;
if (!gpu->LayersEnable[i]) continue; if (!gpu->LayersEnable[i]) continue;
prio = gpu->dispx_st->dispx_BGxCNT[i].bits.Priority; prio = (gpu->dispx_st)->dispx_BGxCNT[i].bits.Priority;
item = &(gpu->itemsForPriority[prio]); item = &(gpu->itemsForPriority[prio]);
item->BGs[item->nbBGs]=i; item->BGs[item->nbBGs]=i;
item->nbBGs++; item->nbBGs++;
@ -237,10 +237,10 @@ void GPU_setVideoProp(GPU * gpu, u32 p)
BOOL LayersEnable[5]; BOOL LayersEnable[5];
u16 WinBG=0; u16 WinBG=0;
struct _DISPCNT * cnt; struct _DISPCNT * cnt;
cnt = &gpu->dispx_st->dispx_DISPCNT.bits; cnt = &(gpu->dispx_st)->dispx_DISPCNT.bits;
// cnt = &gpu->dispCnt.bits; // cnt = &gpu->dispCnt.bits;
gpu->dispx_st->dispx_DISPCNT.val = p; (gpu->dispx_st)->dispx_DISPCNT.val = p;
// gpu->dispMode = DISPCNT_DISPLAY_MODE(p,gpu->lcd) ; // gpu->dispMode = DISPCNT_DISPLAY_MODE(p,gpu->lcd) ;
gpu->dispMode = cnt->DisplayMode & ((gpu->core)?1:3); gpu->dispMode = cnt->DisplayMode & ((gpu->core)?1:3);
@ -303,11 +303,11 @@ void GPU_setVideoProp(GPU * gpu, u32 p)
/* FIXME: all DEBUG_TRI are broken */ /* FIXME: all DEBUG_TRI are broken */
void GPU_setBGProp(GPU * gpu, u16 num, u16 p) void GPU_setBGProp(GPU * gpu, u16 num, u16 p)
{ {
struct _BGxCNT * cnt = &(gpu->dispx_st->dispx_BGxCNT[num].bits), *cnt2; struct _BGxCNT * cnt = &((gpu->dispx_st)->dispx_BGxCNT[num].bits), *cnt2;
struct _DISPCNT * dispCnt = &gpu->dispx_st->dispx_DISPCNT.bits; struct _DISPCNT * dispCnt = &(gpu->dispx_st)->dispx_DISPCNT.bits;
int mode; int mode;
gpu->dispx_st->dispx_BGxCNT[num].val = p; (gpu->dispx_st)->dispx_BGxCNT[num].val = p;
GPU_resortBGs(gpu); GPU_resortBGs(gpu);
@ -354,6 +354,23 @@ void GPU_remove(GPU * gpu, u8 num)
} }
void GPU_addBack(GPU * gpu, u8 num) void GPU_addBack(GPU * gpu, u8 num)
{ {
REG_DISPx * r = gpu->dispx_st;
printf ("%08x %08x\n", r, (long)(&r->dispx_DISPCNT) - (long)r);
printf ("\t%08x\n", (long)(&r->dispA_DISPSTAT) - (long)r);
printf ("\t%08x\n", (long)(&r->dispx_VCOUNT) - (long)r);
printf ("\t%08x\n", (long)(&r->dispx_BGxCNT[0]) - (long)r);
printf ("\t%08x\n", (long)(&r->dispx_BGxCNT[1]) - (long)r);
printf ("\t%08x\n", (long)(&r->dispx_BGxCNT[2]) - (long)r);
printf ("\t%08x\n", (long)(&r->dispx_BGxCNT[3]) - (long)r);
printf ("\t%08x\n", (long)(&r->dispx_BGxOFS[0]) - (long)r);
printf ("\t%08x\n", (long)(&r->dispx_BG2PARMS) - (long)r);
printf ("\t%08x\n", (long)(&r->dispx_BG3PARMS) - (long)r);
printf ("\t%08x\n", (long)(&r->dispx_WINCNT) - (long)r);
printf ("\t%08x\n", (long)(&r->dispx_MISC) - (long)r);
printf ("\t%08x\n", (long)(&r->dispA_DISP3DCNT) - (long)r);
printf ("\t%08x\n", (long)(&r->dispA_DISPCAPCNT) - (long)r);
printf ("\t%08x\n", (long)(&r->dispA_DISPMMEMFIFO) - (long)r);
printf ("\t%08x\n", (long)(&r->dispx_MASTERBRIGHT) - (long)r);
if (num == 4) gpu->dispOBJ = 1; if (num == 4) gpu->dispOBJ = 1;
else gpu->dispBG[num] = 1; else gpu->dispBG[num] = 1;
GPU_resortBGs(gpu); GPU_resortBGs(gpu);
@ -548,7 +565,7 @@ INLINE BOOL withinRect (u8 x,u8 y, u16 startX, u16 startY, u16 endX, u16 endY)
// setting some values twice // setting some values twice
void renderline_checkWindows(GPU *gpu, u8 bgnum, u16 x, u16 y, BOOL *draw, BOOL *effect) void renderline_checkWindows(GPU *gpu, u8 bgnum, u16 x, u16 y, BOOL *draw, BOOL *effect)
{ {
struct _DISPCNT * dispCnt = &gpu->dispx_st->dispx_DISPCNT.bits; struct _DISPCNT * dispCnt = &(gpu->dispx_st)->dispx_DISPCNT.bits;
BOOL wwin0=0, wwin1=0, wwobj=0, windows=0; BOOL wwin0=0, wwin1=0, wwobj=0, windows=0;
// Check if win0 if enabled, and only check if it is // Check if win0 if enabled, and only check if it is
@ -710,8 +727,8 @@ INLINE BOOL renderline_setFinalColor(GPU *gpu,u32 passing,u8 bgnum,u8 *dst,u16 c
/* render a text background to the combined pixelbuffer */ /* render a text background to the combined pixelbuffer */
INLINE void renderline_textBG(GPU * gpu, u8 num, u8 * dst, u32 Y, u16 XBG, u16 YBG, u16 LG) INLINE void renderline_textBG(GPU * gpu, u8 num, u8 * dst, u32 Y, u16 XBG, u16 YBG, u16 LG)
{ {
struct _BGxCNT bgCnt = gpu->dispx_st->dispx_BGxCNT[num].bits; struct _BGxCNT * bgCnt = &(gpu->dispx_st)->dispx_BGxCNT[num].bits;
struct _DISPCNT * dispCnt = &gpu->dispx_st->dispx_DISPCNT.bits; struct _DISPCNT * dispCnt = &(gpu->dispx_st)->dispx_DISPCNT.bits;
u16 lg = gpu->BGSize[num][0]; u16 lg = gpu->BGSize[num][0];
u16 ht = gpu->BGSize[num][1]; u16 ht = gpu->BGSize[num][1];
u16 tmp = ((YBG&(ht-1))>>3); u16 tmp = ((YBG&(ht-1))>>3);
@ -732,7 +749,7 @@ INLINE void renderline_textBG(GPU * gpu, u8 num, u8 * dst, u32 Y, u16 XBG, u16 Y
if(tmp>31) if(tmp>31)
{ {
map+= ADDRESS_STEP_512B << bgCnt.ScreenSize ; map+= ADDRESS_STEP_512B << bgCnt->ScreenSize ;
} }
tile = (u8*) gpu->BG_tile_ram[num]; tile = (u8*) gpu->BG_tile_ram[num];
@ -740,9 +757,9 @@ INLINE void renderline_textBG(GPU * gpu, u8 num, u8 * dst, u32 Y, u16 XBG, u16 Y
xoff = XBG; xoff = XBG;
pal = ARM9Mem.ARM9_VMEM + gpu->core * ADDRESS_STEP_1KB ; pal = ARM9Mem.ARM9_VMEM + gpu->core * ADDRESS_STEP_1KB ;
if(!bgCnt.Palette_256) /* color: 16 palette entries */ if(!bgCnt->Palette_256) /* color: 16 palette entries */
{ {
if (bgCnt.Mosaic_Enable){ if (bgCnt->Mosaic_Enable){
/* test NDS: #2 of /* test NDS: #2 of
http://desmume.sourceforge.net/forums/index.php?action=vthread&forum=2&topic=50&page=0#msg192 */ http://desmume.sourceforge.net/forums/index.php?action=vthread&forum=2&topic=50&page=0#msg192 */
@ -967,10 +984,10 @@ INLINE void rot_scale_op(GPU * gpu, u8 num, u8 * dst, u16 H, s32 X, s32 Y, s16 P
INLINE void apply_rot_fun(GPU * gpu, u8 num, u8 * dst, u16 H, s32 X, s32 Y, s16 PA, s16 PB, s16 PC, s16 PD, u16 LG, rot_fun fun, u8 * map, u8 * tile, u8 * pal) INLINE void apply_rot_fun(GPU * gpu, u8 num, u8 * dst, u16 H, s32 X, s32 Y, s16 PA, s16 PB, s16 PC, s16 PD, u16 LG, rot_fun fun, u8 * map, u8 * tile, u8 * pal)
{ {
struct _BGxCNT bgCnt = gpu->dispx_st->dispx_BGxCNT[num].bits; struct _BGxCNT * bgCnt = &(gpu->dispx_st)->dispx_BGxCNT[num].bits;
s32 wh = gpu->BGSize[num][0]; s32 wh = gpu->BGSize[num][0];
s32 ht = gpu->BGSize[num][1]; s32 ht = gpu->BGSize[num][1];
rot_scale_op(gpu, num, dst, H, X, Y, PA, PB, PC, PD, LG, wh, ht, bgCnt.PaletteSet_Wrap, fun, map, tile, pal); rot_scale_op(gpu, num, dst, H, X, Y, PA, PB, PC, PD, LG, wh, ht, bgCnt->PaletteSet_Wrap, fun, map, tile, pal);
} }
@ -984,13 +1001,13 @@ INLINE void rotBG2(GPU * gpu, u8 num, u8 * dst, u16 H, s32 X, s32 Y, s16 PA, s16
INLINE void extRotBG2(GPU * gpu, u8 num, u8 * dst, u16 H, s32 X, s32 Y, s16 PA, s16 PB, s16 PC, s16 PD, s16 LG) INLINE void extRotBG2(GPU * gpu, u8 num, u8 * dst, u16 H, s32 X, s32 Y, s16 PA, s16 PB, s16 PC, s16 PD, s16 LG)
{ {
struct _BGxCNT bgCnt = gpu->dispx_st->dispx_BGxCNT[num].bits; struct _BGxCNT * bgCnt = &(gpu->dispx_st)->dispx_BGxCNT[num].bits;
u8 *map, *tile, *pal; u8 *map, *tile, *pal;
u8 affineModeSelection ; u8 affineModeSelection ;
/* see: http://nocash.emubase.de/gbatek.htm#dsvideobgmodescontrol */ /* see: http://nocash.emubase.de/gbatek.htm#dsvideobgmodescontrol */
affineModeSelection = (bgCnt.Palette_256 << 1) | (bgCnt.CharacBase_Block & 1) ; affineModeSelection = (bgCnt->Palette_256 << 1) | (bgCnt->CharacBase_Block & 1) ;
// printf("extrot mode %d\n", affineModeSelection); // printf("extrot mode %d\n", affineModeSelection);
switch(affineModeSelection) switch(affineModeSelection)
{ {
@ -1028,26 +1045,38 @@ void lineText(GPU * gpu, u8 num, u16 l, u8 * DST)
} }
void lineRot(GPU * gpu, u8 num, u16 l, u8 * DST) void lineRot(GPU * gpu, u8 num, u16 l, u8 * DST)
{ {
BGxPARMS * parms;
if (num==2) {
parms = &(gpu->dispx_st)->dispx_BG2PARMS;
} else {
parms = &(gpu->dispx_st)->dispx_BG3PARMS;
}
rotBG2(gpu, num, DST, l, rotBG2(gpu, num, DST, l,
gpu->BGX[num], parms->BGxX,
gpu->BGY[num], parms->BGxY,
gpu->BGPA[num], parms->BGxPA,
gpu->BGPB[num], parms->BGxPB,
gpu->BGPC[num], parms->BGxPC,
gpu->BGPD[num], parms->BGxPD,
256); 256);
} }
void lineExtRot(GPU * gpu, u8 num, u16 l, u8 * DST) void lineExtRot(GPU * gpu, u8 num, u16 l, u8 * DST)
{ {
BGxPARMS * parms;
if (num==2) {
parms = &(gpu->dispx_st)->dispx_BG2PARMS;
} else {
parms = &(gpu->dispx_st)->dispx_BG3PARMS;
}
extRotBG2(gpu, num, DST, l, extRotBG2(gpu, num, DST, l,
gpu->BGX[num], parms->BGxX,
gpu->BGY[num], parms->BGxY,
gpu->BGPA[num], parms->BGxPA,
gpu->BGPB[num], parms->BGxPB,
gpu->BGPC[num], parms->BGxPC,
gpu->BGPD[num], parms->BGxPD,
256); 256);
} }
@ -1224,7 +1253,7 @@ INLINE void compute_sprite_rotoscale(GPU * gpu, _OAM_ * spriteInfo,
void sprite1D(GPU * gpu, u16 l, u8 * dst, u8 * prioTab) void sprite1D(GPU * gpu, u16 l, u8 * dst, u8 * prioTab)
{ {
struct _DISPCNT * dispCnt = &gpu->dispx_st->dispx_DISPCNT.bits; struct _DISPCNT * dispCnt = &(gpu->dispx_st)->dispx_DISPCNT.bits;
_OAM_ * spriteInfo = (_OAM_ *)(gpu->oam + (nbShow-1));// + 127; _OAM_ * spriteInfo = (_OAM_ *)(gpu->oam + (nbShow-1));// + 127;
u8 block = gpu->sprBoundary; u8 block = gpu->sprBoundary;
u16 i; u16 i;
@ -1297,7 +1326,7 @@ void sprite1D(GPU * gpu, u16 l, u8 * dst, u8 * prioTab)
void sprite2D(GPU * gpu, u16 l, u8 * dst, u8 * prioTab) void sprite2D(GPU * gpu, u16 l, u8 * dst, u8 * prioTab)
{ {
struct _DISPCNT * dispCnt = &gpu->dispx_st->dispx_DISPCNT.bits; struct _DISPCNT * dispCnt = &(gpu->dispx_st)->dispx_DISPCNT.bits;
_OAM_ * spriteInfo = (_OAM_*)(gpu->oam + (nbShow-1));// + 127; _OAM_ * spriteInfo = (_OAM_*)(gpu->oam + (nbShow-1));// + 127;
u16 i; u16 i;
@ -1523,7 +1552,7 @@ void GPU_ligne(NDS_Screen * screen, u16 l)
{ {
GPU * gpu = screen->gpu; GPU * gpu = screen->gpu;
struct _DISPCAPCNT * capcnt; struct _DISPCAPCNT * capcnt;
struct _DISPCNT * dispCnt = &gpu->dispx_st->dispx_DISPCNT.bits; struct _DISPCNT * dispCnt = &(gpu->dispx_st)->dispx_DISPCNT.bits;
struct _MASTER_BRIGHT * mBright; struct _MASTER_BRIGHT * mBright;
u8 * dst = GPU_screen + (screen->offset + l) * 512; u8 * dst = GPU_screen + (screen->offset + l) * 512;
u8 * mdst = GPU_screen + (MainScreen.offset + l) * 512; u8 * mdst = GPU_screen + (MainScreen.offset + l) * 512;
@ -1748,7 +1777,7 @@ void GPU_ligne(NDS_Screen * screen, u16 l)
// Reference: http://nocash.emubase.de/gbatek.htm#dsvideo (Under MASTER_BRIGHTNESS) // Reference: http://nocash.emubase.de/gbatek.htm#dsvideo (Under MASTER_BRIGHTNESS)
/* Mightymax> it should be more effective if the windowmanager applies brightness when drawing */ /* Mightymax> it should be more effective if the windowmanager applies brightness when drawing */
/* it will most likly take acceleration, while we are stuck here with CPU power */ /* it will most likly take acceleration, while we are stuck here with CPU power */
mBright = &gpu->dispx_st->dispx_MASTERBRIGHT.bits; mBright = &(gpu->dispx_st)->dispx_MASTERBRIGHT.bits;
switch (mBright->Mode) switch (mBright->Mode)
{ {
// Disabled // Disabled

173
desmume/src/GPU.h
View File

@ -43,44 +43,44 @@ extern "C" {
struct _DISPCNT struct _DISPCNT
{ {
/*0*/ unsigned BG_Mode:3; // A+B: /* 0*/ u8 BG_Mode:3; // A+B:
/*3*/ unsigned BG0_3D:1; // A : 0=2D, 1=3D /* 3*/ u8 BG0_3D:1; // A : 0=2D, 1=3D
/*4*/ unsigned OBJ_Tile_1D:1; // A+B: 0=2D (32KB), 1=1D (32..256KB) /* 4*/ u8 OBJ_Tile_1D:1; // A+B: 0=2D (32KB), 1=1D (32..256KB)
/*5*/ unsigned OBJ_BMP_2D_dim:1; // A+B: 0=128x512, 1=256x256 pixels /* 5*/ u8 OBJ_BMP_2D_dim:1; // A+B: 0=128x512, 1=256x256 pixels
/*6*/ unsigned OBJ_BMP_mapping:1; // A+B: 0=2D (128KB), 1=1D (128..256KB) /* 6*/ u8 OBJ_BMP_mapping:1; // A+B: 0=2D (128KB), 1=1D (128..256KB)
// 7-15 same as GBA // 7-15 same as GBA
/*7*/ unsigned ForceBlank:1; // A+B: /* 7*/ u8 ForceBlank:1; // A+B:
/*8*/ unsigned BG0_Enable:1; // A+B: 0=disable, 1=Enable /* 8*/ u8 BG0_Enable:1; // A+B: 0=disable, 1=Enable
/*9*/ unsigned BG1_Enable:1; // A+B: 0=disable, 1=Enable /* 9*/ u8 BG1_Enable:1; // A+B: 0=disable, 1=Enable
/*10*/ unsigned BG2_Enable:1; // A+B: 0=disable, 1=Enable /*10*/ u8 BG2_Enable:1; // A+B: 0=disable, 1=Enable
/*11*/ unsigned BG3_Enable:1; // A+B: 0=disable, 1=Enable /*11*/ u8 BG3_Enable:1; // A+B: 0=disable, 1=Enable
/*12*/ unsigned OBJ_Enable:1; // A+B: 0=disable, 1=Enable /*12*/ u8 OBJ_Enable:1; // A+B: 0=disable, 1=Enable
/*13*/ unsigned Win0_Enable:1; // A+B: 0=disable, 1=Enable /*13*/ u8 Win0_Enable:1; // A+B: 0=disable, 1=Enable
/*14*/ unsigned Win1_Enable:1; // A+B: 0=disable, 1=Enable /*14*/ u8 Win1_Enable:1; // A+B: 0=disable, 1=Enable
/*15*/ unsigned WinOBJ_Enable:1; // A+B: 0=disable, 1=Enable /*15*/ u8 WinOBJ_Enable:1; // A+B: 0=disable, 1=Enable
/*16*/ unsigned DisplayMode:2; // A+B: coreA(0..3) coreB(0..1) GBA(Green Swap) /*16*/ u8 DisplayMode:2; // A+B: coreA(0..3) coreB(0..1) GBA(Green Swap)
// 0=off (white screen) // 0=off (white screen)
// 1=on (normal BG & OBJ layers) // 1=on (normal BG & OBJ layers)
// 2=VRAM display (coreA only) // 2=VRAM display (coreA only)
// 3=RAM display (coreA only, DMA transfers) // 3=RAM display (coreA only, DMA transfers)
/*18*/ unsigned VRAM_Block:2; // A : VRAM block (0..3=A..D) /*18*/ u8 VRAM_Block:2; // A : VRAM block (0..3=A..D)
/*20*/ unsigned OBJ_Tile_1D_Bound:2; // A+B: /*20*/ u8 OBJ_Tile_1D_Bound:2; // A+B:
/*22*/ unsigned OBJ_BMP_1D_Bound:1; // A : /*22*/ u8 OBJ_BMP_1D_Bound:1; // A :
/*23*/ unsigned OBJ_HBlank_process:1; // A+B: OBJ processed during HBlank (GBA bit5) /*23*/ u8 OBJ_HBlank_process:1; // A+B: OBJ processed during HBlank (GBA bit5)
/*24*/ unsigned CharacBase_Block:3; // A : Character Base (64K step) /*24*/ u8 CharacBase_Block:3; // A : Character Base (64K step)
/*27*/ unsigned ScreenBase_Block:3; // A : Screen Base (64K step) /*27*/ u8 ScreenBase_Block:3; // A : Screen Base (64K step)
/*30*/ unsigned ExBGxPalette_Enable:1; // A+B: 0=disable, 1=Enable BG extended Palette /*30*/ u8 ExBGxPalette_Enable:1; // A+B: 0=disable, 1=Enable BG extended Palette
/*31*/ unsigned ExOBJPalette_Enable:1; // A+B: 0=disable, 1=Enable OBJ extended Palette /*31*/ u8 ExOBJPalette_Enable:1; // A+B: 0=disable, 1=Enable OBJ extended Palette
}; };
typedef union typedef union
{ {
struct _DISPCNT bits; struct _DISPCNT bits;
u32 val; u32 val;
} DISPCNT; } DISPCNT;
#define BGxENABLED(cnt,num) ((num<8)? ((cnt.val>>8) & num):0) #define BGxENABLED(cnt,num) ((num<8)? ((cnt.val>>8) & num):0)
@ -95,27 +95,27 @@ typedef union
struct _BGxCNT struct _BGxCNT
{ {
/* 0*/ unsigned Priority:2; // 0..3=high..low /* 0*/ u8 Priority:2; // 0..3=high..low
/* 2*/ unsigned CharacBase_Block:4; // individual character base offset (n*16KB) /* 2*/ u8 CharacBase_Block:4; // individual character base offset (n*16KB)
/* 6*/ unsigned Mosaic_Enable:1; // 0=disable, 1=Enable mosaic /* 6*/ u8 Mosaic_Enable:1; // 0=disable, 1=Enable mosaic
/* 7*/ unsigned Palette_256:1; // 0=16x16, 1=1*256 palette /* 7*/ u8 Palette_256:1; // 0=16x16, 1=1*256 palette
/* 8*/ unsigned ScreenBase_Block:5; // individual screen base offset (text n*2KB, BMP n*16KB) /* 8*/ u8 ScreenBase_Block:5; // individual screen base offset (text n*2KB, BMP n*16KB)
/*13*/ unsigned PaletteSet_Wrap:1; // BG0 extended palette set 0=set0, 1=set2 /*13*/ u8 PaletteSet_Wrap:1; // BG0 extended palette set 0=set0, 1=set2
// BG1 extended palette set 0=set1, 1=set3 // BG1 extended palette set 0=set1, 1=set3
// BG2 overflow area wraparound 0=off, 1=wrap // BG2 overflow area wraparound 0=off, 1=wrap
// BG3 overflow area wraparound 0=off, 1=wrap // BG3 overflow area wraparound 0=off, 1=wrap
/*14*/ unsigned ScreenSize:2; // text : 256x256 512x256 256x512 512x512 /*14*/ u8 ScreenSize:2; // text : 256x256 512x256 256x512 512x512
// x/rot/s : 128x128 256x256 512x512 1024x1024 // x/rot/s : 128x128 256x256 512x512 1024x1024
// bmp : 128x128 256x256 512x256 512x512 // bmp : 128x128 256x256 512x256 512x512
// large : 512x1024 1024x512 - - // large : 512x1024 1024x512 - -
}; };
typedef union typedef union
{ {
struct _BGxCNT bits; struct _BGxCNT bits;
u16 val; u16 val;
} BGxCNT; } BGxCNT;
/******************************************************************************* /*******************************************************************************
this structure is for background offset this structure is for background offset
@ -124,7 +124,7 @@ typedef union
typedef struct { typedef struct {
u16 BGxHOFS; u16 BGxHOFS;
u16 BGxVOFS; u16 BGxVOFS;
} BGxOFS; } BGxOFS;
/******************************************************************************* /*******************************************************************************
this structure is for rotoscale parameters this structure is for rotoscale parameters
@ -137,7 +137,7 @@ typedef struct {
u16 BGxPD; u16 BGxPD;
u32 BGxX; u32 BGxX;
u32 BGxY; u32 BGxY;
} BGxPARMS; } BGxPARMS;
/******************************************************************************* /*******************************************************************************
@ -151,7 +151,7 @@ typedef struct {
u16 WIN1V; u16 WIN1V;
u16 WININ; u16 WININ;
u16 WINOUT; u16 WINOUT;
} WINCNT; } WINCNT;
/******************************************************************************* /*******************************************************************************
this structure is for miscellanous settings this structure is for miscellanous settings
@ -168,7 +168,7 @@ typedef struct {
u16 unused4; u16 unused4;
u16 unused5; u16 unused5;
u16 unused6; u16 unused6;
} MISCCNT; } MISCCNT;
/******************************************************************************* /*******************************************************************************
@ -177,26 +177,26 @@ typedef struct {
struct _DISP3DCNT struct _DISP3DCNT
{ {
/* 0*/ unsigned EnableTexMapping:1; // /* 0*/ u8 EnableTexMapping:1; //
/* 1*/ unsigned PolygonShading:1; // 0=Toon Shading, 1=Highlight Shading /* 1*/ u8 PolygonShading:1; // 0=Toon Shading, 1=Highlight Shading
/* 2*/ unsigned EnableAlphaTest:1; // see ALPHA_TEST_REF /* 2*/ u8 EnableAlphaTest:1; // see ALPHA_TEST_REF
/* 3*/ unsigned EnableAlphaBlending:1; // see various Alpha values /* 3*/ u8 EnableAlphaBlending:1; // see various Alpha values
/* 4*/ unsigned EnableAntiAliasing:1; // /* 4*/ u8 EnableAntiAliasing:1; //
/* 5*/ unsigned EnableEdgeMarking:1; // see EDGE_COLOR /* 5*/ u8 EnableEdgeMarking:1; // see EDGE_COLOR
/* 6*/ unsigned FogOnlyAlpha:1; // 0=Alpha and Color, 1=Only Alpha (see FOG_COLOR) /* 6*/ u8 FogOnlyAlpha:1; // 0=Alpha and Color, 1=Only Alpha (see FOG_COLOR)
/* 7*/ unsigned EnableFog:1; // Fog Master Enable /* 7*/ u8 EnableFog:1; // Fog Master Enable
/* 8*/ unsigned FogShiftSHR:4; // 0..10 SHR-Divider (see FOG_OFFSET) /* 8*/ u8 FogShiftSHR:4; // 0..10 SHR-Divider (see FOG_OFFSET)
/*12*/ unsigned AckColorBufferUnderflow:1; // Color Buffer RDLINES Underflow (0=None, 1=Underflow/Acknowledge) /*12*/ u8 AckColorBufferUnderflow:1; // Color Buffer RDLINES Underflow (0=None, 1=Underflow/Acknowledge)
/*13*/ unsigned AckVertexRAMOverflow:1; // Polygon/Vertex RAM Overflow (0=None, 1=Overflow/Acknowledge) /*13*/ u8 AckVertexRAMOverflow:1; // Polygon/Vertex RAM Overflow (0=None, 1=Overflow/Acknowledge)
/*14*/ unsigned RearPlaneMode:1; // 0=Blank, 1=Bitmap /*14*/ u8 RearPlaneMode:1; // 0=Blank, 1=Bitmap
/*15*/ unsigned :17; /*15*/ u8 :17;
}; };
typedef union typedef union
{ {
struct _DISP3DCNT bits; struct _DISP3DCNT bits;
u32 val; u32 val;
} DISP3DCNT; } DISP3DCNT;
/******************************************************************************* /*******************************************************************************
this structure is for capture control (core A only) this structure is for capture control (core A only)
@ -207,27 +207,27 @@ typedef union
struct _DISPCAPCNT struct _DISPCAPCNT
{ {
/* 0*/ unsigned BlendFactor_A:5; // 0..16 = Blending Factor for Source A /* 0*/ u8 BlendFactor_A:5; // 0..16 = Blending Factor for Source A
/* 5*/ unsigned :3; // /* 5*/ u8 :3; //
/* 8*/ unsigned BlendFactor_B:5; // 0..16 = Blending Factor for Source B /* 8*/ u8 BlendFactor_B:5; // 0..16 = Blending Factor for Source B
/*13*/ unsigned :3; // /*13*/ u8 :3; //
/*16*/ unsigned VRAM_Write_Block:2; // 0..3 = VRAM A..D /*16*/ u8 VRAM_Write_Block:2; // 0..3 = VRAM A..D
/*18*/ unsigned VRAM_Write_Offset:2; // n x 0x08000 /*18*/ u8 VRAM_Write_Offset:2; // n x 0x08000
/*20*/ unsigned Capture_Size:2; // 0=128x128, 1=256x64, 2=256x128, 3=256x192 dots /*20*/ u8 Capture_Size:2; // 0=128x128, 1=256x64, 2=256x128, 3=256x192 dots
/*22*/ unsigned :2; // /*22*/ u8 :2; //
/*24*/ unsigned Source_A:1; // 0=Graphics Screen BG+3D+OBJ, 1=3D Screen /*24*/ u8 Source_A:1; // 0=Graphics Screen BG+3D+OBJ, 1=3D Screen
/*25*/ unsigned Source_B:1; // 0=VRAM, 1=Main Memory Display FIFO /*25*/ u8 Source_B:1; // 0=VRAM, 1=Main Memory Display FIFO
/*26*/ unsigned VRAM_Read_Offset:2; // n x 0x08000 /*26*/ u8 VRAM_Read_Offset:2; // n x 0x08000
/*28*/ unsigned :1; // /*28*/ u8 :1; //
/*29*/ unsigned Capture_Source:2; // 0=Source A, 1=Source B, 2/3=Sources A+B blended /*29*/ u8 Capture_Source:2; // 0=Source A, 1=Source B, 2/3=Sources A+B blended
/*31*/ unsigned Capture_Enable:1; // 0=Disable/Ready, 1=Enable/Busy /*31*/ u8 Capture_Enable:1; // 0=Disable/Ready, 1=Enable/Busy
}; };
typedef union typedef union
{ {
struct _DISPCAPCNT bits; struct _DISPCAPCNT bits;
u32 val; u32 val;
} DISPCAPCNT; } DISPCAPCNT;
@ -241,17 +241,17 @@ typedef union
struct _MASTER_BRIGHT struct _MASTER_BRIGHT
{ {
/* 0*/ unsigned Factor:4; // combine with (Factor / 16) of white/black /* 0*/ u8 Factor:4; // combine with (Factor / 16) of white/black
/* 4*/ unsigned FactorEx:1; // if true use white or black /* 4*/ u8 FactorEx:1; // if true use white or black
/* 5*/ unsigned :9; /* 5*/ u8 :9;
/*14*/ unsigned Mode:2; // 0=off, 1=Lighten, 2=Darken, 3=? /*14*/ u8 Mode:2; // 0=off, 1=Lighten, 2=Darken, 3=?
}; };
typedef union typedef union
{ {
struct _MASTER_BRIGHT bits; struct _MASTER_BRIGHT bits;
u16 val; u16 val;
} MASTER_BRIGHT; } MASTER_BRIGHT;
/******************************************************************************* /*******************************************************************************
this structure holds everything and should be mapped to this structure holds everything and should be mapped to
@ -273,9 +273,26 @@ typedef struct _reg_dispx {
DISPCAPCNT dispA_DISPCAPCNT; // 0x04000064 DISPCAPCNT dispA_DISPCAPCNT; // 0x04000064
u32 dispA_DISPMMEMFIFO; // 0x04000068 u32 dispA_DISPMMEMFIFO; // 0x04000068
MASTER_BRIGHT dispx_MASTERBRIGHT; // 0x0400x06C MASTER_BRIGHT dispx_MASTERBRIGHT; // 0x0400x06C
} REG_DISPx; } REG_DISPx ;
// normally should have same addresses
static void REG_DISPx_pack_test(GPU * gpu)
{
REG_DISPx * r = gpu->dispx_st;
printf ("%08x %02x\n", r, (long)(&r->dispx_DISPCNT) - (long)r);
printf ("\t%02x\n", (long)(&r->dispA_DISPSTAT) - (long)r);
printf ("\t%02x\n", (long)(&r->dispx_VCOUNT) - (long)r);
printf ("\t%02x\n", (long)(&r->dispx_BGxCNT[0]) - (long)r);
printf ("\t%02x\n", (long)(&r->dispx_BGxOFS[0]) - (long)r);
printf ("\t%02x\n", (long)(&r->dispx_BG2PARMS) - (long)r);
printf ("\t%02x\n", (long)(&r->dispx_BG3PARMS) - (long)r);
printf ("\t%02x\n", (long)(&r->dispx_WINCNT) - (long)r);
printf ("\t%02x\n", (long)(&r->dispx_MISC) - (long)r);
printf ("\t%02x\n", (long)(&r->dispA_DISP3DCNT) - (long)r);
printf ("\t%02x\n", (long)(&r->dispA_DISPCAPCNT) - (long)r);
printf ("\t%02x\n", (long)(&r->dispA_DISPMMEMFIFO) - (long)r);
printf ("\t%02x\n", (long)(&r->dispx_MASTERBRIGHT) - (long)r);
}