From cb1d7d2f2332371d4a6a378aedb20cc81116f20c Mon Sep 17 00:00:00 2001 From: nitsuja Date: Sun, 20 Sep 2009 20:11:16 +0000 Subject: [PATCH] - new memory access timing, should be more accurate. this fixes some games for me. - this includes basic cache emulation, but that's disabled for now for performance reasons - got rid of the fast fetch execute menu option (switching between the two should no longer be needed and I don't think we should have things like that be options) --- desmume/src/MMU.cpp | 32 +- desmume/src/MMU.h | 3 - desmume/src/MMU_timing.h | 395 +++++++++++ desmume/src/Makefile.am | 2 +- desmume/src/NDSSystem.h | 3 - desmume/src/arm_instructions.cpp | 644 +++++++++--------- desmume/src/armcpu.cpp | 15 +- .../cocoa/DeSmuME.xcodeproj/project.pbxproj | 2 + desmume/src/mem.h | 5 +- desmume/src/saves.cpp | 35 +- desmume/src/thumb_instructions.cpp | 65 +- desmume/src/windows/DeSmuME_2005.vcproj | 4 + desmume/src/windows/DeSmuME_2008.vcproj | 4 + desmume/src/windows/DeSmuME_2010.vcxproj | 1 + .../src/windows/DeSmuME_2010.vcxproj.filters | 3 + desmume/src/windows/DeSmuME_Intel.icproj | 2 + desmume/src/windows/DeSmuME_Intel.vcproj | 4 + desmume/src/windows/main.cpp | 9 - desmume/src/windows/resource.h | 2 - desmume/src/windows/resources.rc | Bin 446356 -> 445796 bytes 20 files changed, 825 insertions(+), 405 deletions(-) create mode 100644 desmume/src/MMU_timing.h diff --git a/desmume/src/MMU.cpp b/desmume/src/MMU.cpp index 61592d995..5bb553220 100644 --- a/desmume/src/MMU.cpp +++ b/desmume/src/MMU.cpp @@ -44,6 +44,7 @@ #include "addons.h" #include "mic.h" #include "movie.h" +#include "MMU_timing.h" #ifdef DO_ASSERT_UNALIGNED #define ASSERT_UNALIGNED(x) assert(x) @@ -163,6 +164,7 @@ void mmu_log_debug_ARM7(u32 adr, const char *fmt, ...) MMU_struct MMU; MMU_struct_new MMU_new; +MMU_struct_timing MMU_timing; u8 * MMU_struct::MMU_MEM[2][256] = { //arm9 @@ -252,17 +254,18 @@ u32 MMU_struct::MMU_MASK[2][256] = { } }; -CACHE_ALIGN -TWaitState MMU_struct::MMU_WAIT16[2][16] = { - { 1, 1, 1, 1, 1, 1, 1, 1, 5, 5, 5, 1, 1, 1, 1, 1 }, //arm9 - { 1, 1, 1, 1, 1, 1, 1, 1, 5, 5, 5, 1, 1, 1, 1, 1 }, //arm7 -}; - -CACHE_ALIGN -TWaitState MMU_struct::MMU_WAIT32[2][16] = { - { 1, 1, 1, 1, 1, 2, 2, 1, 8, 8, 5, 1, 1, 1, 1, 1 }, //arm9 - { 1, 1, 1, 1, 1, 1, 1, 1, 8, 8, 5, 1, 1, 1, 1, 1 }, //arm7 -}; +// this logic was moved to MMU_timing.h +//CACHE_ALIGN +//TWaitState MMU_struct::MMU_WAIT16[2][16] = { +// { 1, 1, 1, 1, 1, 1, 1, 1, 5, 5, 5, 1, 1, 1, 1, 1 }, //arm9 +// { 1, 1, 1, 1, 1, 1, 1, 1, 5, 5, 5, 1, 1, 1, 1, 1 }, //arm7 +//}; +// +//CACHE_ALIGN +//TWaitState MMU_struct::MMU_WAIT32[2][16] = { +// { 1, 1, 1, 1, 1, 2, 2, 1, 8, 8, 5, 1, 1, 1, 1, 1 }, //arm9 +// { 1, 1, 1, 1, 1, 1, 1, 1, 8, 8, 5, 1, 1, 1, 1, 1 }, //arm7 +//}; ////////////////////////////////////////////////////////////// @@ -965,6 +968,13 @@ void MMU_Reset() MMU.dscard[ARMCPU_ARM7].address = 0; MMU.dscard[ARMCPU_ARM7].transfer_count = 0; MMU.dscard[ARMCPU_ARM7].mode = CardMode_Normal; + + MMU_timing.arm7codeFetch.Reset(); + MMU_timing.arm7dataFetch.Reset(); + MMU_timing.arm9codeFetch.Reset(); + MMU_timing.arm9dataFetch.Reset(); + MMU_timing.arm9codeCache.Reset(); + MMU_timing.arm9dataCache.Reset(); } void MMU_setRom(u8 * rom, u32 mask) diff --git a/desmume/src/MMU.h b/desmume/src/MMU.h index 15deaa7f3..d62c888be 100644 --- a/desmume/src/MMU.h +++ b/desmume/src/MMU.h @@ -120,9 +120,6 @@ struct MMU_struct u8 ARM9_RW_MODE; - static CACHE_ALIGN TWaitState MMU_WAIT16[2][16]; - static CACHE_ALIGN TWaitState MMU_WAIT32[2][16]; - u32 DTCMRegion; u32 ITCMRegion; diff --git a/desmume/src/MMU_timing.h b/desmume/src/MMU_timing.h new file mode 100644 index 000000000..cb704d5e0 --- /dev/null +++ b/desmume/src/MMU_timing.h @@ -0,0 +1,395 @@ +/* Copyright (C) 2006 yopyop + yopyop156@ifrance.com + yopyop156.ifrance.com + + Copyright (C) 2007 shash + Copyright (C) 2007-2009 DeSmuME team + + This file is part of DeSmuME + + DeSmuME is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + DeSmuME is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with DeSmuME; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +// this file is split from MMU.h for the purpose of avoiding ridiculous recompile times +// when changing it, because practically everything includes MMU.h. +#ifndef MMUTIMING_H +#define MMUTIMING_H + +#include +#include "MMU.h" +#include "cp15.h" +#include "readwrite.h" + +//////////////////////////////////////////////////////////////// +// MEMORY TIMING ACCURACY CONFIGURATION +// +// the more of these are enabled, +// the more accurate memory access timing _should_ become. +// they should be listed roughly in order of most to least important. +// it's reasonable to disable some of these as a speed hack. +// obviously, these defines don't cover all the variables or features needed, +// and in particular, DMA or code+data access bus contention is still missing. + + // makes non-sequential accesses slower than sequential ones. +#define ACCOUNT_FOR_NON_SEQUENTIAL_ACCESS + + // enables emulation of code fetch waits. +#define ACCOUNT_FOR_CODE_FETCH_CYCLES + + // makes access to DTCM (arm9 only) fast. +#define ACCOUNT_FOR_DATA_TCM_SPEED + + // enables simulation of cache hits and cache misses. + // currently disabled for a few FPS of emulator speedup. +//#define ENABLE_CACHE_CONTROLLER_EMULATION + +// +//////////////////////////////////////////////////////////////// + + +enum MMU_ACCESS_DIRECTION +{ + MMU_AD_READ, MMU_AD_WRITE +}; + + +// note that we don't actually emulate the cache contents here, +// only enough to guess what would be a cache hit or a cache miss. +// this doesn't really get used unless ENABLE_CACHE_CONTROLLER_EMULATION is defined. +template +class CacheController +{ +public: + template + FORCEINLINE bool Cached(u32 addr) + { + u32 blockMasked = addr & BLOCKMASK; + if(blockMasked == m_cacheCache) + return true; + else + return this->CachedInternal(addr, blockMasked); + } + + void Reset() + { + for(int blockIndex = 0; blockIndex < NUMBLOCKS; blockIndex++) + m_blocks[blockIndex].Reset(); + m_cacheCache = ~0; + } + CacheController() + { + Reset(); + } + + void savestate(EMUFILE* os, int version) + { + write32le(m_cacheCache, os); + for(int i = 0; i < NUMBLOCKS; i++) + { + for(int j = 0; j < ASSOCIATIVITY; j++) + write32le(m_blocks[i].tag[j],os); + write32le(m_blocks[i].nextWay,os); + } + } + bool loadstate(EMUFILE* is, int version) + { + read32le(&m_cacheCache, is); + for(int i = 0; i < NUMBLOCKS; i++) + { + for(int j = 0; j < ASSOCIATIVITY; j++) + read32le(&m_blocks[i].tag[j],is); + read32le(&m_blocks[i].nextWay,is); + } + return true; + } + +private: + template + bool CachedInternal(u32 addr, u32 blockMasked) + { + u32 blockIndex = blockMasked >> BLOCKSIZESHIFT; + CacheBlock& block = m_blocks[blockIndex]; + addr &= TAGMASK; + + for(int way = 0; way < ASSOCIATIVITY; way++) + if(addr == block.tag[way]) + { + // found it, already allocated + m_cacheCache = blockMasked; + return true; + } + if(DIR == MMU_AD_READ) + { + // TODO: support other allocation orders? + block.tag[block.nextWay++] = addr; + block.nextWay %= ASSOCIATIVITY; + m_cacheCache = blockMasked; + } + return false; + } + + enum { SIZE = 1 << SIZESHIFT }; + enum { ASSOCIATIVITY = 1 << ASSOCIATIVESHIFT }; + enum { BLOCKSIZE = 1 << BLOCKSIZESHIFT }; + enum { TAGSHIFT = SIZESHIFT - ASSOCIATIVESHIFT }; + enum { TAGMASK = (u32)(~0 << TAGSHIFT) }; + enum { BLOCKMASK = ((u32)~0 >> (32 - TAGSHIFT)) & (u32)(~0 << BLOCKSIZESHIFT) }; + enum { WORDSIZE = sizeof(u32) }; + enum { WORDSPERBLOCK = (1 << BLOCKSIZESHIFT) / WORDSIZE }; + enum { DATAPERWORD = WORDSIZE * ASSOCIATIVITY }; + enum { DATAPERBLOCK = DATAPERWORD * WORDSPERBLOCK }; + enum { NUMBLOCKS = SIZE / DATAPERBLOCK }; + + struct CacheBlock + { + u32 tag [ASSOCIATIVITY]; + u32 nextWay; + + void Reset() + { + nextWay = 0; + for(int way = 0; way < ASSOCIATIVITY; way++) + tag[way] = 0; + } + }; + + u32 m_cacheCache; // optimization + + CacheBlock m_blocks [NUMBLOCKS]; +}; + + +template +FORCEINLINE u32 _MMU_accesstime(u32 addr, bool sequential); + + +template +class FetchAccessUnit +{ +public: + template + FORCEINLINE u32 Fetch(u32 address) + { +#ifndef ACCOUNT_FOR_CODE_FETCH_CYCLES + if(AT == MMU_AT_CODE) + return 1; +#endif + + u32 time = _MMU_accesstime(address, +#ifdef ACCOUNT_FOR_NON_SEQUENTIAL_ACCESS + address == (m_lastAddress + (READSIZE>>3)) +#else + true +#endif + ); + +#ifdef ACCOUNT_FOR_NON_SEQUENTIAL_ACCESS + m_lastAddress = address; +#endif + + return time; + } + + void Reset() + { + m_lastAddress = ~0; + } + FetchAccessUnit() { this->Reset(); } + + void savestate(EMUFILE* os, int version) + { + write32le(m_lastAddress,os); + } + bool loadstate(EMUFILE* is, int version) + { + read32le(&m_lastAddress,is); + return true; + } + +private: + u32 m_lastAddress; +}; + + + + + +struct MMU_struct_timing +{ + // technically part of the cp15, but I didn't want the dereferencing penalty. + // these template values correspond with the value of armcp15->cacheType. + CacheController<13,2,5> arm9codeCache; // 8192 bytes, 4-way associative, 32-byte blocks + CacheController<12,2,5> arm9dataCache; // 4096 bytes, 4-way associative, 32-byte blocks + + // technically part of armcpu_t, but that struct isn't templated on PROCNUM + FetchAccessUnit<0,MMU_AT_CODE> arm9codeFetch; + FetchAccessUnit<0,MMU_AT_DATA> arm9dataFetch; + FetchAccessUnit<1,MMU_AT_CODE> arm7codeFetch; + FetchAccessUnit<1,MMU_AT_DATA> arm7dataFetch; + + template FORCEINLINE FetchAccessUnit& armCodeFetch(); + template FORCEINLINE FetchAccessUnit& armDataFetch(); +}; +template<> FORCEINLINE FetchAccessUnit<0,MMU_AT_CODE>& MMU_struct_timing::armCodeFetch<0>() { return this->arm9codeFetch; } +template<> FORCEINLINE FetchAccessUnit<1,MMU_AT_CODE>& MMU_struct_timing::armCodeFetch<1>() { return this->arm7codeFetch; } +template<> FORCEINLINE FetchAccessUnit<0,MMU_AT_DATA>& MMU_struct_timing::armDataFetch<0>() { return this->arm9dataFetch; } +template<> FORCEINLINE FetchAccessUnit<1,MMU_AT_DATA>& MMU_struct_timing::armDataFetch<1>() { return this->arm7dataFetch; } + + +extern MMU_struct_timing MMU_timing; + + + +// calculates the time a single memory access takes, +// in units of cycles of the current processor. +// this function replaces what used to be MMU_WAIT16 and MMU_WAIT32. +template +FORCEINLINE u32 _MMU_accesstime(u32 addr, bool sequential) +{ + static const int MC = 1; // cached or tcm memory speed + static const int M32 = (PROCNUM==ARMCPU_ARM9) ? 2 : 1; // access through 32-bit bus + static const int M16 = M32 * ((READSIZE>16) ? 2 : 1); // access through 16-bit bus + static const int MSLW = M16 * 8; // this needs tuning + + if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_CODE && addr < 0x02000000) + return MC; // ITCM + +#ifdef ACCOUNT_FOR_DATA_TCM_SPEED + if(PROCNUM==ARMCPU_ARM9 && AT==MMU_AT_DATA && (addr&(~0x3FFF)) == MMU.DTCMRegion) + return MC; // DTCM +#endif + + // for now, assume the cache is always enabled for all of main memory + if(PROCNUM==ARMCPU_ARM9 && (addr & 0x0F000000) == 0x02000000) + { +#ifdef ENABLE_CACHE_CONTROLLER_EMULATION + bool cached = false; + if(AT==MMU_AT_CODE) + cached = MMU_timing.arm9codeCache.Cached(addr); + if(AT==MMU_AT_DATA) + cached = MMU_timing.arm9dataCache.Cached(addr); + if(cached) + return MC; + if(sequential && AT==MMU_AT_DATA) + return M16; + return M16 * ((DIRECTION == MMU_AD_READ) ? 5 : 4); +#elif defined(ACCOUNT_FOR_NON_SEQUENTIAL_ACCESS) + // this is the closest approximation I could find + // to the with-cache-controller timing + // that doesn't do any actual caching logic. + return sequential ? MC : M16; +#endif + } + + static const TWaitState MMU_WAIT[16*16] = { + // ITCM, ITCM, MAIN, SWI, REG, VMEM, LCD, OAM, ROM, ROM, RAM, U, U, U, U, BIOS +#define X MC, MC, M16, M32, M32, M16, M16, M32, MSLW, MSLW, MSLW, M32,M32,M32,M32, M32, + // duplicate it 16 times (this was somehow faster than using a mask of 0xF) + X X X X X X X X X X X X X X X X +#undef X + }; + + u32 c = MMU_WAIT[(addr >> 24)]; + +#ifdef ACCOUNT_FOR_NON_SEQUENTIAL_ACCESS + if(!sequential) + { + //if(c != MC || PROCNUM==ARMCPU_ARM7) // check not needed anymore because ITCM/DTCM return earlier + { + c += (PROCNUM==ARMCPU_ARM9) ? 3*2 : 1; + } + } +#endif + + return c; +} + + + + + +// calculates the cycle time of a single memory access in the MEM stage. +// to be used to calculate the memCycles argument for MMU_aluMemCycles. +// this may have side effects, so don't call it more than necessary. +template +FORCEINLINE u32 MMU_memAccessCycles(u32 addr) +{ + return MMU_timing.armDataFetch().template Fetch((addr)&(~((READSIZE>>3)-1))); +} + +// calculates the cycle time of a single code fetch in the FETCH stage +// to be used to calculate the fetchCycles argument for MMU_fetchExecuteCycles. +// this may have side effects, so don't call it more than necessary. +template +FORCEINLINE u32 MMU_codeFetchCycles(u32 addr) +{ + return MMU_timing.armCodeFetch().template Fetch((addr)&(~((READSIZE>>3)-1))); +} + +// calculates the cycle contribution of ALU + MEM stages (= EXECUTE) +// given ALU cycle time and the summation of multiple memory access cycle times. +// this function might belong more in armcpu, but I don't think it matters. +template +FORCEINLINE u32 MMU_aluMemCycles(u32 aluCycles, u32 memCycles) +{ + if(PROCNUM==ARMCPU_ARM9) + { + // ALU and MEM are different stages of the 5-stage pipeline. + // we approximate the pipeline throughput using max, + // since simply adding the cycles of each instruction together + // fails to take into account the parallelism of the arm pipeline + // and would make the emulated system unnaturally slow. + return std::max(aluCycles, memCycles); + } + else + { + // ALU and MEM are part of the same stage of the 3-stage pipeline, + // thus they occur in sequence and we can simply add the counts together. + return aluCycles + memCycles; + } +} + +// calculates the cycle contribution of ALU + MEM stages (= EXECUTE) +// given ALU cycle time and the description of a single memory access. +// this may have side effects, so don't call it more than necessary. +template +FORCEINLINE u32 MMU_aluMemAccessCycles(u32 aluCycles, u32 addr) +{ + u32 memCycles = MMU_memAccessCycles(addr); + return MMU_aluMemCycles(aluCycles, memCycles); +} + +// calculates the cycle contribution of FETCH + EXECUTE stages +// given executeCycles = the combined ALU+MEM cycles +// and fetchCycles = the cycle time of the FETCH stage +// this function might belong more in armcpu, but I don't think it matters. +template +FORCEINLINE u32 MMU_fetchExecuteCycles(u32 executeCycles, u32 fetchCycles) +{ +#ifdef ACCOUNT_FOR_CODE_FETCH_CYCLES + // execute and fetch are different stages of the pipeline for both arm7 and arm9. + // again, we approximate the pipeline throughput using max. + return std::max(executeCycles, fetchCycles); + // TODO: add an option to support conflict between MEM and FETCH cycles + // if they're both using the same data bus. + // in the case of a conflict this should be: + // return std::max(aluCycles, memCycles + fetchCycles); +#else + return executeCycles; +#endif +} + + +#endif diff --git a/desmume/src/Makefile.am b/desmume/src/Makefile.am index 74bdf9b8b..9c51521ee 100644 --- a/desmume/src/Makefile.am +++ b/desmume/src/Makefile.am @@ -25,7 +25,7 @@ libdesmume_a_SOURCES = \ path.h \ readwrite.cpp readwrite.h \ wifi.cpp wifi.h \ - MMU.cpp MMU.h NDSSystem.cpp NDSSystem.h registers.h \ + MMU.cpp MMU.h MMU_timing.h NDSSystem.cpp NDSSystem.h registers.h \ OGLRender.cpp OGLRender.h \ ROMReader.cpp ROMReader.h \ render3D.cpp render3D.h \ diff --git a/desmume/src/NDSSystem.h b/desmume/src/NDSSystem.h index 263a86113..ea7255de9 100644 --- a/desmume/src/NDSSystem.h +++ b/desmume/src/NDSSystem.h @@ -431,7 +431,6 @@ extern struct TCommonSettings { , spuAdpcmCache(false) , gfx3d_flushMode(0) , manualBackupType(0) - , armFastFetchExecute(false) { strcpy(ARM9BIOS, "biosnds9.bin"); strcpy(ARM7BIOS, "biosnds7.bin"); @@ -472,8 +471,6 @@ extern struct TCommonSettings { //this is the user's choice of manual backup type, for cases when the autodetection can't be trusted int manualBackupType; - bool armFastFetchExecute; - bool spu_muteChannels[16]; struct _ShowGpu { diff --git a/desmume/src/arm_instructions.cpp b/desmume/src/arm_instructions.cpp index aa072aa54..db842ad26 100644 --- a/desmume/src/arm_instructions.cpp +++ b/desmume/src/arm_instructions.cpp @@ -25,6 +25,7 @@ #include "armcpu.h" #include "NDSSystem.h" #include "arm_instructions.h" +#include "MMU_timing.h" #define cpu (&ARMPROC) #define TEMPLATE template @@ -2449,7 +2450,9 @@ TEMPLATE static u32 FASTCALL OP_SWP(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,0)]); cpu->R[REG_POS(i,12)] = tmp; - return 4 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]*2; + u32 c = MMU_memAccessCycles(adr); + c += MMU_memAccessCycles(adr); + return MMU_aluMemCycles(4, c); } TEMPLATE static u32 FASTCALL OP_SWPB(const u32 i) @@ -2459,7 +2462,9 @@ TEMPLATE static u32 FASTCALL OP_SWPB(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)(cpu->R[REG_POS(i,0)]&0xFF)); cpu->R[REG_POS(i,12)] = tmp; - return 4 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]*2; + u32 c = MMU_memAccessCycles(adr); + c += MMU_memAccessCycles(adr); + return MMU_aluMemCycles(4, c); } //------------LDRH----------------------------- @@ -2469,7 +2474,7 @@ TEMPLATE static u32 FASTCALL OP_LDRH_P_IMM_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRH_M_IMM_OFF(const u32 i) @@ -2477,7 +2482,7 @@ TEMPLATE static u32 FASTCALL OP_LDRH_M_IMM_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRH_P_REG_OFF(const u32 i) @@ -2485,7 +2490,7 @@ TEMPLATE static u32 FASTCALL OP_LDRH_P_REG_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRH_M_REG_OFF(const u32 i) @@ -2493,7 +2498,7 @@ TEMPLATE static u32 FASTCALL OP_LDRH_M_REG_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_P_IMM_OFF(const u32 i) @@ -2502,7 +2507,7 @@ TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_P_IMM_OFF(const u32 i) cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_M_IMM_OFF(const u32 i) @@ -2512,7 +2517,7 @@ TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_M_IMM_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_P_REG_OFF(const u32 i) @@ -2521,7 +2526,7 @@ TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_P_REG_OFF(const u32 i) cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] =(u32)READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_M_REG_OFF(const u32 i) @@ -2530,7 +2535,7 @@ TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_M_REG_OFF(const u32 i) cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_P_IMM_OFF(const u32 i) @@ -2539,7 +2544,7 @@ TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_P_IMM_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] += IMM_OFF; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_M_IMM_OFF(const u32 i) @@ -2548,7 +2553,7 @@ TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_M_IMM_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] -= IMM_OFF; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_P_REG_OFF(const u32 i) @@ -2557,7 +2562,7 @@ TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_P_REG_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_M_REG_OFF(const u32 i) @@ -2566,7 +2571,7 @@ TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_M_REG_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } //------------STRH----------------------------- @@ -2576,7 +2581,7 @@ TEMPLATE static u32 FASTCALL OP_STRH_P_IMM_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRH_M_IMM_OFF(const u32 i) @@ -2584,7 +2589,7 @@ TEMPLATE static u32 FASTCALL OP_STRH_M_IMM_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRH_P_REG_OFF(const u32 i) @@ -2592,7 +2597,7 @@ TEMPLATE static u32 FASTCALL OP_STRH_P_REG_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRH_M_REG_OFF(const u32 i) @@ -2600,7 +2605,7 @@ TEMPLATE static u32 FASTCALL OP_STRH_M_REG_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_P_IMM_OFF(const u32 i) @@ -2609,7 +2614,7 @@ TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_P_IMM_OFF(const u32 i) cpu->R[REG_POS(i,16)] = adr; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_M_IMM_OFF(const u32 i) @@ -2618,7 +2623,7 @@ TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_M_IMM_OFF(const u32 i) WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_P_REG_OFF(const u32 i) @@ -2627,7 +2632,7 @@ TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_P_REG_OFF(const u32 i) WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_M_REG_OFF(const u32 i) @@ -2636,7 +2641,7 @@ TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_M_REG_OFF(const u32 i) WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_P_IMM_OFF(const u32 i) @@ -2645,7 +2650,7 @@ TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_P_IMM_OFF(const u32 i) WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] += IMM_OFF; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_M_IMM_OFF(const u32 i) @@ -2654,7 +2659,7 @@ TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_M_IMM_OFF(const u32 i) WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] -= IMM_OFF; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_P_REG_OFF(const u32 i) @@ -2663,7 +2668,7 @@ TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_P_REG_OFF(const u32 i) WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_M_REG_OFF(const u32 i) @@ -2672,7 +2677,7 @@ TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_M_REG_OFF(const u32 i) WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } //----------------LDRSH-------------------------- @@ -2682,7 +2687,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSH_P_IMM_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSH_M_IMM_OFF(const u32 i) @@ -2690,7 +2695,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSH_M_IMM_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSH_P_REG_OFF(const u32 i) @@ -2698,7 +2703,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSH_P_REG_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSH_M_REG_OFF(const u32 i) @@ -2706,7 +2711,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSH_M_REG_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_P_IMM_OFF(const u32 i) @@ -2715,7 +2720,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_P_IMM_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_M_IMM_OFF(const u32 i) @@ -2724,7 +2729,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_M_IMM_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_P_REG_OFF(const u32 i) @@ -2733,7 +2738,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_P_REG_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_M_REG_OFF(const u32 i) @@ -2742,7 +2747,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_M_REG_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_P_IMM_OFF(const u32 i) @@ -2751,7 +2756,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_P_IMM_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] += IMM_OFF; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_M_IMM_OFF(const u32 i) @@ -2760,7 +2765,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_M_IMM_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] -= IMM_OFF; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_P_REG_OFF(const u32 i) @@ -2769,7 +2774,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_P_REG_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_M_REG_OFF(const u32 i) @@ -2778,7 +2783,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_M_REG_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } //----------------------LDRSB---------------------- @@ -2788,7 +2793,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSB_P_IMM_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSB_M_IMM_OFF(const u32 i) @@ -2796,7 +2801,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSB_M_IMM_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSB_P_REG_OFF(const u32 i) @@ -2804,7 +2809,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSB_P_REG_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSB_M_REG_OFF(const u32 i) @@ -2812,7 +2817,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSB_M_REG_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_P_IMM_OFF(const u32 i) @@ -2821,7 +2826,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_P_IMM_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_M_IMM_OFF(const u32 i) @@ -2830,7 +2835,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_M_IMM_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_P_REG_OFF(const u32 i) @@ -2839,7 +2844,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_P_REG_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_M_REG_OFF(const u32 i) @@ -2848,7 +2853,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_M_REG_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_P_IMM_OFF(const u32 i) @@ -2857,7 +2862,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_P_IMM_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] += IMM_OFF; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_M_IMM_OFF(const u32 i) @@ -2866,7 +2871,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_M_IMM_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] -= IMM_OFF; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_P_REG_OFF(const u32 i) @@ -2875,7 +2880,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_P_REG_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_M_REG_OFF(const u32 i) @@ -2884,7 +2889,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_M_REG_OFF(const u32 i) cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } //--------------MRS-------------------------------- @@ -3416,11 +3421,11 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF(const u32 i) cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF(const u32 i) @@ -3435,12 +3440,12 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF(const u32 i) cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF(const u32 i) @@ -3459,12 +3464,12 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF(const u32 i) cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF(const u32 i) @@ -3483,12 +3488,12 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF(const u32 i) cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF(const u32 i) @@ -3507,12 +3512,12 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF(const u32 i) cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF(const u32 i) @@ -3531,12 +3536,12 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF(const u32 i) cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF(const u32 i) @@ -3555,12 +3560,12 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF(const u32 i) cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF(const u32 i) @@ -3579,12 +3584,12 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF(const u32 i) cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF(const u32 i) @@ -3603,12 +3608,12 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF(const u32 i) cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF(const u32 i) @@ -3627,13 +3632,13 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF(const u32 i) cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_PREIND(const u32 i) @@ -3649,13 +3654,13 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_PREIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF_PREIND(const u32 i) @@ -3671,14 +3676,14 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF_PREIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_PREIND(const u32 i) @@ -3698,14 +3703,14 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_PREIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_PREIND(const u32 i) @@ -3725,14 +3730,14 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_PREIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_PREIND(const u32 i) @@ -3752,14 +3757,14 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_PREIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_PREIND(const u32 i) @@ -3779,14 +3784,14 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_PREIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_PREIND(const u32 i) @@ -3806,14 +3811,14 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_PREIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_PREIND(const u32 i) @@ -3833,14 +3838,14 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_PREIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_PREIND(const u32 i) @@ -3860,14 +3865,14 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_PREIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_PREIND(const u32 i) @@ -3887,13 +3892,13 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_PREIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND(const u32 i) @@ -3909,13 +3914,13 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } //------------------------------------------------------------ @@ -3933,7 +3938,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND2(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } old = armcpu_switchMode(cpu, USR); @@ -3942,7 +3947,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND2(const u32 i) cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } //------------------------------------------------------------ @@ -3960,13 +3965,13 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF_POSTIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_POSTIND(const u32 i) @@ -3986,13 +3991,13 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_POSTIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr + shift_op; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_POSTIND(const u32 i) @@ -4012,13 +4017,13 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_POSTIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr - shift_op; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_POSTIND(const u32 i) @@ -4038,13 +4043,13 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_POSTIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr + shift_op; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_POSTIND(const u32 i) @@ -4064,13 +4069,13 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_POSTIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr - shift_op; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_POSTIND(const u32 i) @@ -4090,13 +4095,13 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_POSTIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr + shift_op; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_POSTIND(const u32 i) @@ -4116,13 +4121,13 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_POSTIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr - shift_op; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_POSTIND(const u32 i) @@ -4142,13 +4147,13 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_POSTIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr + shift_op; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_POSTIND(const u32 i) @@ -4168,13 +4173,13 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_POSTIND(const u32 i) cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr - shift_op; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(5,adr); } cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } //-----------------LDRB------------------------------------------- @@ -4185,7 +4190,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF(const u32 i) u32 val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_IMM_OFF(const u32 i) @@ -4194,7 +4199,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_IMM_OFF(const u32 i) u32 val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF(const u32 i) @@ -4207,7 +4212,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF(const u32 i) val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF(const u32 i) @@ -4220,7 +4225,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF(const u32 i) val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF(const u32 i) @@ -4233,7 +4238,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF(const u32 i) val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF(const u32 i) @@ -4246,7 +4251,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF(const u32 i) val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF(const u32 i) @@ -4259,7 +4264,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF(const u32 i) val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF(const u32 i) @@ -4272,7 +4277,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF(const u32 i) val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF(const u32 i) @@ -4285,7 +4290,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF(const u32 i) val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF(const u32 i) @@ -4299,7 +4304,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF(const u32 i) cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF_PREIND(const u32 i) @@ -4311,7 +4316,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF_PREIND(const u32 i) cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_IMM_OFF_PREIND(const u32 i) @@ -4322,7 +4327,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_IMM_OFF_PREIND(const u32 i) cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_PREIND(const u32 i) @@ -4338,7 +4343,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_PREIND(const u32 i) cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_PREIND(const u32 i) @@ -4353,7 +4358,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_PREIND(const u32 i) cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_PREIND(const u32 i) @@ -4367,7 +4372,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_PREIND(const u32 i) cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_PREIND(const u32 i) @@ -4381,7 +4386,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_PREIND(const u32 i) cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_PREIND(const u32 i) @@ -4395,7 +4400,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_PREIND(const u32 i) cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_PREIND(const u32 i) @@ -4409,7 +4414,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_PREIND(const u32 i) cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_PREIND(const u32 i) @@ -4423,7 +4428,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_PREIND(const u32 i) cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_PREIND(const u32 i) @@ -4437,7 +4442,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_PREIND(const u32 i) cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF_POSTIND(const u32 i) @@ -4447,7 +4452,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF_POSTIND(const u32 i) cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_IMM_OFF_POSTIND(const u32 i) @@ -4457,7 +4462,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_IMM_OFF_POSTIND(const u32 i) cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_POSTIND(const u32 i) @@ -4471,7 +4476,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_POSTIND(const u32 i) cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_POSTIND(const u32 i) @@ -4485,7 +4490,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_POSTIND(const u32 i) cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_POSTIND(const u32 i) @@ -4499,7 +4504,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_POSTIND(const u32 i) cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_POSTIND(const u32 i) @@ -4513,7 +4518,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_POSTIND(const u32 i) cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_POSTIND(const u32 i) @@ -4527,7 +4532,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_POSTIND(const u32 i) cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_POSTIND(const u32 i) @@ -4541,7 +4546,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_POSTIND(const u32 i) cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_POSTIND(const u32 i) @@ -4555,7 +4560,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_POSTIND(const u32 i) cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_POSTIND(const u32 i) @@ -4569,7 +4574,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_POSTIND(const u32 i) cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3,adr); } //----------------------STR-------------------------------- @@ -4581,7 +4586,7 @@ TEMPLATE static u32 FASTCALL OP_STR_P_IMM_OFF(const u32 i) // emu_halt(); - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF(const u32 i) @@ -4589,7 +4594,7 @@ TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF(const u32 i) @@ -4600,7 +4605,7 @@ TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF(const u32 i) adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF(const u32 i) @@ -4611,7 +4616,7 @@ TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF(const u32 i) adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF(const u32 i) @@ -4622,7 +4627,7 @@ TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF(const u32 i) adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF(const u32 i) @@ -4633,7 +4638,7 @@ TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF(const u32 i) adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF(const u32 i) @@ -4644,7 +4649,7 @@ TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF(const u32 i) adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF(const u32 i) @@ -4655,7 +4660,7 @@ TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF(const u32 i) adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF(const u32 i) @@ -4666,7 +4671,7 @@ TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF(const u32 i) adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF(const u32 i) @@ -4678,7 +4683,7 @@ TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_P_IMM_OFF_PREIND(const u32 i) @@ -4687,7 +4692,7 @@ TEMPLATE static u32 FASTCALL OP_STR_P_IMM_OFF_PREIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF_PREIND(const u32 i) @@ -4696,7 +4701,7 @@ TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF_PREIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_PREIND(const u32 i) @@ -4708,7 +4713,7 @@ TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_PREIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_PREIND(const u32 i) @@ -4720,7 +4725,7 @@ TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_PREIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_PREIND(const u32 i) @@ -4732,7 +4737,7 @@ TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_PREIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_PREIND(const u32 i) @@ -4744,7 +4749,7 @@ TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_PREIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_PREIND(const u32 i) @@ -4756,7 +4761,7 @@ TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_PREIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_PREIND(const u32 i) @@ -4768,7 +4773,7 @@ TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_PREIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_PREIND(const u32 i) @@ -4780,7 +4785,7 @@ TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_PREIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_PREIND(const u32 i) @@ -4792,7 +4797,7 @@ TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_PREIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_P_IMM_OFF_POSTIND(const u32 i) @@ -4801,7 +4806,7 @@ TEMPLATE static u32 FASTCALL OP_STR_P_IMM_OFF_POSTIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF_POSTIND(const u32 i) @@ -4810,7 +4815,7 @@ TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF_POSTIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_POSTIND(const u32 i) @@ -4822,7 +4827,7 @@ TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_POSTIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_POSTIND(const u32 i) @@ -4834,7 +4839,7 @@ TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_POSTIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_POSTIND(const u32 i) @@ -4846,7 +4851,7 @@ TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_POSTIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_POSTIND(const u32 i) @@ -4858,7 +4863,7 @@ TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_POSTIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_POSTIND(const u32 i) @@ -4870,7 +4875,7 @@ TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_POSTIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_POSTIND(const u32 i) @@ -4882,7 +4887,7 @@ TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_POSTIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_POSTIND(const u32 i) @@ -4894,7 +4899,7 @@ TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_POSTIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_POSTIND(const u32 i) @@ -4906,7 +4911,7 @@ TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_POSTIND(const u32 i) WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } //-----------------------STRB------------------------------------- @@ -4916,7 +4921,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_IMM_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_IMM_OFF(const u32 i) @@ -4924,7 +4929,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_IMM_OFF(const u32 i) u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF(const u32 i) @@ -4935,7 +4940,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF(const u32 i) adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF(const u32 i) @@ -4946,7 +4951,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF(const u32 i) adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF(const u32 i) @@ -4957,7 +4962,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF(const u32 i) adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF(const u32 i) @@ -4968,7 +4973,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF(const u32 i) adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF(const u32 i) @@ -4979,7 +4984,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF(const u32 i) adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF(const u32 i) @@ -4990,7 +4995,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF(const u32 i) adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF(const u32 i) @@ -5001,7 +5006,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF(const u32 i) adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF(const u32 i) @@ -5012,7 +5017,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF(const u32 i) adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_P_IMM_OFF_PREIND(const u32 i) @@ -5021,7 +5026,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_IMM_OFF_PREIND(const u32 i) WRITE8(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_IMM_OFF_PREIND(const u32 i) @@ -5030,7 +5035,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_IMM_OFF_PREIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_PREIND(const u32 i) @@ -5042,7 +5047,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_PREIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_PREIND(const u32 i) @@ -5054,7 +5059,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_PREIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_PREIND(const u32 i) @@ -5066,7 +5071,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_PREIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_PREIND(const u32 i) @@ -5078,7 +5083,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_PREIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_PREIND(const u32 i) @@ -5090,7 +5095,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_PREIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_PREIND(const u32 i) @@ -5102,7 +5107,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_PREIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_PREIND(const u32 i) @@ -5114,7 +5119,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_PREIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_PREIND(const u32 i) @@ -5126,7 +5131,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_PREIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_P_IMM_OFF_POSTIND(const u32 i) @@ -5135,7 +5140,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_IMM_OFF_POSTIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_IMM_OFF_POSTIND(const u32 i) @@ -5144,7 +5149,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_IMM_OFF_POSTIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_POSTIND(const u32 i) @@ -5156,7 +5161,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_POSTIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_POSTIND(const u32 i) @@ -5168,7 +5173,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_POSTIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_POSTIND(const u32 i) @@ -5180,7 +5185,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_POSTIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_POSTIND(const u32 i) @@ -5192,7 +5197,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_POSTIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_POSTIND(const u32 i) @@ -5204,7 +5209,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_POSTIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_POSTIND(const u32 i) @@ -5216,7 +5221,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_POSTIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_POSTIND(const u32 i) @@ -5228,7 +5233,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_POSTIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) @@ -5240,7 +5245,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2,adr); } ////-----------------------LDRBT------------------------------------- @@ -5264,7 +5269,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(3,adr); //} // //TEMPLATE static u32 FASTCALL OP_LDRBT_M_IMM_OFF_POSTIND(const u32 i) @@ -5288,7 +5293,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(3,adr); //} // //TEMPLATE static u32 FASTCALL OP_LDRBT_P_REG_OFF_POSTIND(const u32 i) @@ -5313,7 +5318,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(3,adr); //} // //TEMPLATE static u32 FASTCALL OP_LDRBT_P_LSL_IMM_OFF_POSTIND(const u32 i) @@ -5339,7 +5344,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(3,adr); //} // //TEMPLATE static u32 FASTCALL OP_LDRBT_M_LSL_IMM_OFF_POSTIND(const u32 i) @@ -5366,7 +5371,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(3,adr); //} // //TEMPLATE static u32 FASTCALL OP_LDRBT_P_LSR_IMM_OFF_POSTIND(const u32 i) @@ -5393,7 +5398,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(3,adr); //} // //TEMPLATE static u32 FASTCALL OP_LDRBT_M_LSR_IMM_OFF_POSTIND(const u32 i) @@ -5420,7 +5425,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(3,adr); //} // //TEMPLATE static u32 FASTCALL OP_LDRBT_P_ASR_IMM_OFF_POSTIND(const u32 i) @@ -5448,7 +5453,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(3,adr); //} // //TEMPLATE static u32 FASTCALL OP_LDRBT_M_ASR_IMM_OFF_POSTIND(const u32 i) @@ -5476,7 +5481,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(3,adr); //} // //TEMPLATE static u32 FASTCALL OP_LDRBT_P_ROR_IMM_OFF_POSTIND(const u32 i) @@ -5504,7 +5509,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(3,adr); //} // //TEMPLATE static u32 FASTCALL OP_LDRBT_M_ROR_IMM_OFF_POSTIND(const u32 i) @@ -5532,7 +5537,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(3,adr); //} // ////----------------------STRBT---------------------------- @@ -5556,7 +5561,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(2,adr); //} // //TEMPLATE static u32 FASTCALL OP_STRBT_M_IMM_OFF_POSTIND(const u32 i) @@ -5578,7 +5583,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(2,adr); //} // //TEMPLATE static u32 FASTCALL OP_STRBT_P_REG_OFF_POSTIND(const u32 i) @@ -5600,7 +5605,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(2,adr); //} // //TEMPLATE static u32 FASTCALL OP_STRBT_M_REG_OFF_POSTIND(const u32 i) @@ -5622,7 +5627,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(2,adr); //} // //TEMPLATE static u32 FASTCALL OP_STRBT_P_LSL_IMM_OFF_POSTIND(const u32 i) @@ -5646,7 +5651,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(2,adr); //} // //TEMPLATE static u32 FASTCALL OP_STRBT_M_LSL_IMM_OFF_POSTIND(const u32 i) @@ -5670,7 +5675,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(2,adr); //} // //TEMPLATE static u32 FASTCALL OP_STRBT_P_LSR_IMM_OFF_POSTIND(const u32 i) @@ -5694,7 +5699,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(2,adr); //} // //TEMPLATE static u32 FASTCALL OP_STRBT_M_LSR_IMM_OFF_POSTIND(const u32 i) @@ -5718,7 +5723,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(2,adr); //} // //TEMPLATE static u32 FASTCALL OP_STRBT_P_ASR_IMM_OFF_POSTIND(const u32 i) @@ -5742,7 +5747,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(2,adr); //} // //TEMPLATE static u32 FASTCALL OP_STRBT_M_ASR_IMM_OFF_POSTIND(const u32 i) @@ -5766,7 +5771,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(2,adr); //} // //TEMPLATE static u32 FASTCALL OP_STRBT_P_ROR_IMM_OFF_POSTIND(const u32 i) @@ -5790,7 +5795,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(2,adr); //} // //TEMPLATE static u32 FASTCALL OP_STRBT_M_ROR_IMM_OFF_POSTIND(const u32 i) @@ -5814,7 +5819,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) // // armcpu_switchMode(cpu, oldmode); // -// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +// return MMU_aluMemAccessCycles(2,adr); //} //---------------------LDM----------------------------- @@ -5822,7 +5827,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) #define OP_L_IA(reg, adr) if(BIT##reg(i))\ {\ registres[reg] = READ32(cpu->mem_if->data, start);\ - c += waitState[(start>>24)&0xF];\ + c += MMU_memAccessCycles(start);\ adr += 4;\ } @@ -5830,13 +5835,13 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) {\ adr += 4;\ registres[reg] = READ32(cpu->mem_if->data, start);\ - c += waitState[(start>>24)&0xF];\ + c += MMU_memAccessCycles(start);\ } #define OP_L_DA(reg, adr) if(BIT##reg(i))\ {\ registres[reg] = READ32(cpu->mem_if->data, start);\ - c += waitState[(start>>24)&0xF];\ + c += MMU_memAccessCycles(start);\ adr -= 4;\ } @@ -5844,7 +5849,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) {\ adr -= 4;\ registres[reg] = READ32(cpu->mem_if->data, start);\ - c += waitState[(start>>24)&0xF];\ + c += MMU_memAccessCycles(start);\ } TEMPLATE static u32 FASTCALL OP_LDMIA(const u32 i) @@ -5853,7 +5858,6 @@ TEMPLATE static u32 FASTCALL OP_LDMIA(const u32 i) u32 start = cpu->R[REG_POS(i,16)]; u32 * registres = cpu->R; - TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; OP_L_IA(0, start); OP_L_IA(1, start); @@ -5878,10 +5882,10 @@ TEMPLATE static u32 FASTCALL OP_LDMIA(const u32 i) cpu->CPSR.bits.T = BIT0(tmp); //start += 4; cpu->next_instruction = registres[15]; - c += waitState[(start>>24)&0xF]; + c += MMU_memAccessCycles(start); } - return c + 2; + return MMU_aluMemCycles(2, c); } TEMPLATE static u32 FASTCALL OP_LDMIB(const u32 i) @@ -5890,7 +5894,6 @@ TEMPLATE static u32 FASTCALL OP_LDMIB(const u32 i) u32 start = cpu->R[REG_POS(i,16)]; u32 * registres = cpu->R; - TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; OP_L_IB(0, start); OP_L_IB(1, start); @@ -5912,15 +5915,15 @@ TEMPLATE static u32 FASTCALL OP_LDMIB(const u32 i) { u32 tmp; start += 4; - c += waitState[(start>>24)&0xF]; + c += MMU_memAccessCycles(start); tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR.bits.T = BIT0(tmp); cpu->next_instruction = registres[15]; - c += 2 + (c==0); + return MMU_aluMemCycles(4, c); } - return c + 2; + return MMU_aluMemCycles(2, c); } TEMPLATE static u32 FASTCALL OP_LDMDA(const u32 i) @@ -5929,14 +5932,13 @@ TEMPLATE static u32 FASTCALL OP_LDMDA(const u32 i) u32 start = cpu->R[REG_POS(i,16)]; u32 * registres = cpu->R; - TWaitState * waitState = MMU.MMU_WAIT32[PROCNUM]; if(BIT15(i)) { u32 tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR.bits.T = BIT0(tmp); - c += waitState[(start>>24)&0xF]; + c += MMU_memAccessCycles(start); start -= 4; cpu->next_instruction = registres[15]; } @@ -5957,7 +5959,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDA(const u32 i) OP_L_DA(1, start); OP_L_DA(0, start); - return c + 2; + return MMU_aluMemCycles(2, c); } TEMPLATE static u32 FASTCALL OP_LDMDB(const u32 i) @@ -5966,7 +5968,6 @@ TEMPLATE static u32 FASTCALL OP_LDMDB(const u32 i) u32 start = cpu->R[REG_POS(i,16)]; u32 * registres = cpu->R; - TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; if(BIT15(i)) { @@ -5976,7 +5977,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDB(const u32 i) registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR.bits.T = BIT0(tmp); cpu->next_instruction = registres[15]; - c += waitState[(start>>24)&0xF]; + c += MMU_memAccessCycles(start); } OP_L_DB(14, start); @@ -5995,7 +5996,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDB(const u32 i) OP_L_DB(1, start); OP_L_DB(0, start); - return c + 2; + return MMU_aluMemCycles(2, c); } TEMPLATE static u32 FASTCALL OP_LDMIA_W(const u32 i) @@ -6005,7 +6006,6 @@ TEMPLATE static u32 FASTCALL OP_LDMIA_W(const u32 i) u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF; u32 * registres = cpu->R; - TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; OP_L_IA(0, start); OP_L_IA(1, start); @@ -6028,7 +6028,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIA_W(const u32 i) u32 tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR.bits.T = BIT0(tmp); - c += waitState[(start>>24)&0xF]; + c += MMU_memAccessCycles(start); start += 4; cpu->next_instruction = registres[15]; } @@ -6040,7 +6040,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIA_W(const u32 i) else cpu->R[REG_POS(i,16)] = start; - return c + 2; + return MMU_aluMemCycles(2, c); } TEMPLATE static u32 FASTCALL OP_LDMIB_W(const u32 i) @@ -6050,7 +6050,6 @@ TEMPLATE static u32 FASTCALL OP_LDMIB_W(const u32 i) u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF; u32 * registres = cpu->R; - TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; OP_L_IB(0, start); OP_L_IB(1, start); @@ -6072,12 +6071,11 @@ TEMPLATE static u32 FASTCALL OP_LDMIB_W(const u32 i) { u32 tmp; start += 4; - c += waitState[(start>>24)&0xF]; + c += MMU_memAccessCycles(start); tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR.bits.T = BIT0(tmp); cpu->next_instruction = registres[15]; - c += 2 + (c==0); } if(i & (1 << REG_POS(i,16))) { @@ -6087,7 +6085,10 @@ TEMPLATE static u32 FASTCALL OP_LDMIB_W(const u32 i) else cpu->R[REG_POS(i,16)] = start; - return c + 2; + if(BIT15(i)) + return MMU_aluMemCycles(4, c); + else + return MMU_aluMemCycles(2, c); } TEMPLATE static u32 FASTCALL OP_LDMDA_W(const u32 i) @@ -6097,14 +6098,13 @@ TEMPLATE static u32 FASTCALL OP_LDMDA_W(const u32 i) u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF; u32 * registres = cpu->R; - TWaitState * waitState = MMU.MMU_WAIT32[PROCNUM]; if(BIT15(i)) { u32 tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR.bits.T = BIT0(tmp); - c += waitState[(start>>24)&0xF]; + c += MMU_memAccessCycles(start); start -= 4; cpu->next_instruction = registres[15]; } @@ -6132,7 +6132,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDA_W(const u32 i) else cpu->R[REG_POS(i,16)] = start; - return c + 2; + return MMU_aluMemCycles(2, c); } TEMPLATE static u32 FASTCALL OP_LDMDB_W(const u32 i) @@ -6141,7 +6141,6 @@ TEMPLATE static u32 FASTCALL OP_LDMDB_W(const u32 i) u32 start = cpu->R[REG_POS(i,16)]; u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF; u32 * registres = cpu->R; - TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; if(BIT15(i)) { @@ -6151,7 +6150,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDB_W(const u32 i) registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR.bits.T = BIT0(tmp); cpu->next_instruction = registres[15]; - c += waitState[(start>>24)&0xF]; + c += MMU_memAccessCycles(start); } OP_L_DB(14, start); @@ -6177,7 +6176,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDB_W(const u32 i) else cpu->R[REG_POS(i,16)] = start; - return c + 2; + return MMU_aluMemCycles(2, c); } TEMPLATE static u32 FASTCALL OP_LDMIA2(const u32 i) @@ -6188,7 +6187,6 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2(const u32 i) u32 start = cpu->R[REG_POS(i,16)]; u32 * registres; - TWaitState* waitState; if(BIT15(i)==0) { @@ -6198,7 +6196,6 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2(const u32 i) } registres = cpu->R; - waitState = MMU.MMU_WAIT32[PROCNUM]; OP_L_IA(0, start); OP_L_IA(1, start); @@ -6231,9 +6228,9 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2(const u32 i) cpu->CPSR=SPSR; //start += 4; cpu->next_instruction = cpu->R[15]; - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + c += MMU_memAccessCycles(start); } - return c + 2; + return MMU_aluMemCycles(2, c); } TEMPLATE static u32 FASTCALL OP_LDMIB2(const u32 i) @@ -6243,7 +6240,6 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2(const u32 i) u32 start = cpu->R[REG_POS(i,16)]; u32 * registres; - TWaitState* waitState; UNTESTEDOPCODELOG("Untested opcode: OP_LDMIB2\n"); @@ -6255,7 +6251,6 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2(const u32 i) } registres = cpu->R; - waitState = MMU.MMU_WAIT32[PROCNUM]; OP_L_IB(0, start); OP_L_IB(1, start); @@ -6288,9 +6283,9 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2(const u32 i) armcpu_switchMode(cpu, SPSR.bits.mode); cpu->CPSR=SPSR; cpu->next_instruction = registres[15]; - c += waitState[(start>>24)&0xF]; + c += MMU_memAccessCycles(start); } - return c + 2; + return MMU_aluMemCycles(2, c); } TEMPLATE static u32 FASTCALL OP_LDMDA2(const u32 i) @@ -6299,7 +6294,6 @@ TEMPLATE static u32 FASTCALL OP_LDMDA2(const u32 i) u32 oldmode = 0; u32 c = 0; u32 * registres; - TWaitState* waitState; u32 start = cpu->R[REG_POS(i,16)]; @@ -6313,14 +6307,13 @@ TEMPLATE static u32 FASTCALL OP_LDMDA2(const u32 i) } registres = cpu->R; - waitState = MMU.MMU_WAIT32[PROCNUM]; if(BIT15(i)) { u32 tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR = cpu->SPSR; - c += waitState[(start>>24)&0xF]; + c += MMU_memAccessCycles(start); start -= 4; cpu->next_instruction = registres[15]; } @@ -6352,16 +6345,14 @@ TEMPLATE static u32 FASTCALL OP_LDMDA2(const u32 i) cpu->CPSR=SPSR; } - return c + 2; + return MMU_aluMemCycles(2, c); } TEMPLATE static u32 FASTCALL OP_LDMDB2(const u32 i) { - u32 oldmode = 0; u32 c = 0; u32 * registres; - TWaitState* waitState; u32 start = cpu->R[REG_POS(i,16)]; if(BIT15(i)==0) @@ -6372,7 +6363,6 @@ TEMPLATE static u32 FASTCALL OP_LDMDB2(const u32 i) } registres = cpu->R; - waitState = MMU.MMU_WAIT32[PROCNUM]; if(BIT15(i)) { @@ -6382,7 +6372,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDB2(const u32 i) registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR = cpu->SPSR; cpu->next_instruction = registres[15]; - c += waitState[(start>>24)&0xF]; + c += MMU_memAccessCycles(start); } OP_L_DB(14, start); @@ -6412,7 +6402,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDB2(const u32 i) cpu->CPSR=SPSR; } - return 2 + c; + return MMU_aluMemCycles(2, c); } TEMPLATE static u32 FASTCALL OP_LDMIA2_W(const u32 i) @@ -6422,7 +6412,6 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2_W(const u32 i) u32 oldmode = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 * registres; - TWaitState* waitState; u32 tmp; Status_Reg SPSR; // emu_halt(); @@ -6434,7 +6423,6 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2_W(const u32 i) } registres = cpu->R; - waitState = MMU.MMU_WAIT32[PROCNUM]; OP_L_IA(0, start); OP_L_IA(1, start); @@ -6456,7 +6444,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2_W(const u32 i) { registres[REG_POS(i,16)] = start; armcpu_switchMode(cpu, oldmode); - return c + 2; + return MMU_aluMemCycles(2, c); } registres[REG_POS(i,16)] = start + 4; @@ -6466,9 +6454,9 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2_W(const u32 i) armcpu_switchMode(cpu, SPSR.bits.mode); cpu->CPSR=SPSR; cpu->next_instruction = registres[15]; - c += waitState[(start>>24)&0xF]; + c += MMU_memAccessCycles(start); - return c + 2; + return MMU_aluMemCycles(2, c); } TEMPLATE static u32 FASTCALL OP_LDMIB2_W(const u32 i) @@ -6478,7 +6466,6 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2_W(const u32 i) u32 oldmode = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 * registres; - TWaitState* waitState; u32 tmp; Status_Reg SPSR; @@ -6490,7 +6477,6 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2_W(const u32 i) } registres = cpu->R; - waitState = MMU.MMU_WAIT32[PROCNUM]; OP_L_IB(0, start); OP_L_IB(1, start); @@ -6513,7 +6499,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2_W(const u32 i) armcpu_switchMode(cpu, oldmode); registres[REG_POS(i,16)] = start; - return c + 2; + return MMU_aluMemCycles(2, c); } registres[REG_POS(i,16)] = start + 4; @@ -6524,9 +6510,9 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2_W(const u32 i) SPSR = cpu->SPSR; armcpu_switchMode(cpu, SPSR.bits.mode); cpu->CPSR=SPSR; - c += waitState[(start>>24)&0xF]; + c += MMU_memAccessCycles(start); - return c + 2; + return MMU_aluMemCycles(2, c); } TEMPLATE static u32 FASTCALL OP_LDMDA2_W(const u32 i) @@ -6536,7 +6522,6 @@ TEMPLATE static u32 FASTCALL OP_LDMDA2_W(const u32 i) u32 oldmode = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 * registres; - TWaitState * waitState; Status_Reg SPSR; // emu_halt(); if(BIT15(i)==0) @@ -6547,13 +6532,12 @@ TEMPLATE static u32 FASTCALL OP_LDMDA2_W(const u32 i) } registres = cpu->R; - waitState = MMU.MMU_WAIT32[PROCNUM]; if(BIT15(i)) { u32 tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - c += waitState[(start>>24)&0xF]; + c += MMU_memAccessCycles(start); start -= 4; cpu->next_instruction = registres[15]; } @@ -6579,13 +6563,13 @@ TEMPLATE static u32 FASTCALL OP_LDMDA2_W(const u32 i) if(BIT15(i)==0) { armcpu_switchMode(cpu, oldmode); - return c + 2; + return MMU_aluMemCycles(2, c); } SPSR = cpu->SPSR; armcpu_switchMode(cpu, SPSR.bits.mode); cpu->CPSR=SPSR; - return c + 2; + return MMU_aluMemCycles(2, c); } TEMPLATE static u32 FASTCALL OP_LDMDB2_W(const u32 i) @@ -6595,7 +6579,6 @@ TEMPLATE static u32 FASTCALL OP_LDMDB2_W(const u32 i) u32 oldmode = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 * registres; - TWaitState* waitState; Status_Reg SPSR; // emu_halt(); if(BIT15(i)==0) @@ -6606,14 +6589,13 @@ TEMPLATE static u32 FASTCALL OP_LDMDB2_W(const u32 i) } registres = cpu->R; - waitState = MMU.MMU_WAIT32[PROCNUM]; if(BIT15(i)) { u32 tmp; start -= 4; tmp = READ32(cpu->mem_if->data, start); - c += waitState[(start>>24)&0xF]; + c += MMU_memAccessCycles(start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR = cpu->SPSR; cpu->next_instruction = registres[15]; @@ -6640,13 +6622,13 @@ TEMPLATE static u32 FASTCALL OP_LDMDB2_W(const u32 i) if(BIT15(i)==0) { armcpu_switchMode(cpu, oldmode); - return c + 2; + return MMU_aluMemCycles(2, c); } SPSR = cpu->SPSR; armcpu_switchMode(cpu, SPSR.bits.mode); cpu->CPSR=SPSR; - return c + 2; + return MMU_aluMemCycles(2, c); } //------------------------------STM---------------------------------- @@ -6661,11 +6643,11 @@ TEMPLATE static u32 FASTCALL OP_STMIA(const u32 i) if(BIT_N(i, b)) { WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + c += MMU_memAccessCycles(start); start += 4; } } - return c + 1; + return MMU_aluMemCycles(1, c); } TEMPLATE static u32 FASTCALL OP_STMIB(const u32 i) @@ -6679,10 +6661,10 @@ TEMPLATE static u32 FASTCALL OP_STMIB(const u32 i) { start += 4; WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + c += MMU_memAccessCycles(start); } } - return c + 1; + return MMU_aluMemCycles(1, c); } TEMPLATE static u32 FASTCALL OP_STMDA(const u32 i) @@ -6695,11 +6677,11 @@ TEMPLATE static u32 FASTCALL OP_STMDA(const u32 i) if(BIT_N(i, 15-b)) { WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + c += MMU_memAccessCycles(start); start -= 4; } } - return c + 1; + return MMU_aluMemCycles(1, c); } TEMPLATE static u32 FASTCALL OP_STMDB(const u32 i) @@ -6713,10 +6695,10 @@ TEMPLATE static u32 FASTCALL OP_STMDB(const u32 i) { start -= 4; WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + c += MMU_memAccessCycles(start); } } - return c + 1; + return MMU_aluMemCycles(1, c); } TEMPLATE static u32 FASTCALL OP_STMIA_W(const u32 i) @@ -6729,13 +6711,13 @@ TEMPLATE static u32 FASTCALL OP_STMIA_W(const u32 i) if(BIT_N(i, b)) { WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + c += MMU_memAccessCycles(start); start += 4; } } cpu->R[REG_POS(i,16)] = start; - return c + 1; + return MMU_aluMemCycles(1, c); } TEMPLATE static u32 FASTCALL OP_STMIB_W(const u32 i) @@ -6749,11 +6731,11 @@ TEMPLATE static u32 FASTCALL OP_STMIB_W(const u32 i) { start += 4; WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + c += MMU_memAccessCycles(start); } } cpu->R[REG_POS(i,16)] = start; - return c + 1; + return MMU_aluMemCycles(1, c); } TEMPLATE static u32 FASTCALL OP_STMDA_W(const u32 i) @@ -6766,13 +6748,13 @@ TEMPLATE static u32 FASTCALL OP_STMDA_W(const u32 i) if(BIT_N(i, 15-b)) { WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + c += MMU_memAccessCycles(start); start -= 4; } } cpu->R[REG_POS(i,16)] = start; - return c + 1; + return MMU_aluMemCycles(1, c); } TEMPLATE static u32 FASTCALL OP_STMDB_W(const u32 i) @@ -6786,12 +6768,12 @@ TEMPLATE static u32 FASTCALL OP_STMDB_W(const u32 i) { start -= 4; WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + c += MMU_memAccessCycles(start); } } cpu->R[REG_POS(i,16)] = start; - return c + 1; + return MMU_aluMemCycles(1, c); } TEMPLATE static u32 FASTCALL OP_STMIA2(const u32 i) @@ -6814,13 +6796,13 @@ TEMPLATE static u32 FASTCALL OP_STMIA2(const u32 i) if(BIT_N(i, b)) { WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + c += MMU_memAccessCycles(start); start += 4; } } armcpu_switchMode(cpu, oldmode); - return c + 1; + return MMU_aluMemCycles(1, c); } TEMPLATE static u32 FASTCALL OP_STMIB2(const u32 i) @@ -6844,12 +6826,12 @@ TEMPLATE static u32 FASTCALL OP_STMIB2(const u32 i) { start += 4; WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + c += MMU_memAccessCycles(start); } } armcpu_switchMode(cpu, oldmode); - return c + 1; + return MMU_aluMemCycles(1, c); } TEMPLATE static u32 FASTCALL OP_STMDA2(const u32 i) @@ -6872,13 +6854,13 @@ TEMPLATE static u32 FASTCALL OP_STMDA2(const u32 i) if(BIT_N(i, 15-b)) { WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + c += MMU_memAccessCycles(start); start -= 4; } } armcpu_switchMode(cpu, oldmode); - return c + 1; + return MMU_aluMemCycles(1, c); } TEMPLATE static u32 FASTCALL OP_STMDB2(const u32 i) @@ -6900,12 +6882,12 @@ TEMPLATE static u32 FASTCALL OP_STMDB2(const u32 i) { start -= 4; WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + c += MMU_memAccessCycles(start); } } armcpu_switchMode(cpu, oldmode); - return c + 1; + return MMU_aluMemCycles(1, c); } TEMPLATE static u32 FASTCALL OP_STMIA2_W(const u32 i) @@ -6928,7 +6910,7 @@ TEMPLATE static u32 FASTCALL OP_STMIA2_W(const u32 i) if(BIT_N(i, b)) { WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + c += MMU_memAccessCycles(start); start += 4; } } @@ -6936,7 +6918,7 @@ TEMPLATE static u32 FASTCALL OP_STMIA2_W(const u32 i) cpu->R[REG_POS(i,16)] = start; armcpu_switchMode(cpu, oldmode); - return c + 1; + return MMU_aluMemCycles(1, c); } TEMPLATE static u32 FASTCALL OP_STMIB2_W(const u32 i) @@ -6957,13 +6939,13 @@ TEMPLATE static u32 FASTCALL OP_STMIB2_W(const u32 i) { start += 4; WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + c += MMU_memAccessCycles(start); } } armcpu_switchMode(cpu, oldmode); cpu->R[REG_POS(i,16)] = start; - return c + 1; + return MMU_aluMemCycles(1, c); } TEMPLATE static u32 FASTCALL OP_STMDA2_W(const u32 i) @@ -6986,7 +6968,7 @@ TEMPLATE static u32 FASTCALL OP_STMDA2_W(const u32 i) if(BIT_N(i, 15-b)) { WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + c += MMU_memAccessCycles(start); start -= 4; } } @@ -6994,7 +6976,7 @@ TEMPLATE static u32 FASTCALL OP_STMDA2_W(const u32 i) cpu->R[REG_POS(i,16)] = start; armcpu_switchMode(cpu, oldmode); - return c + 1; + return MMU_aluMemCycles(1, c); } TEMPLATE static u32 FASTCALL OP_STMDB2_W(const u32 i) @@ -7019,14 +7001,14 @@ TEMPLATE static u32 FASTCALL OP_STMDB2_W(const u32 i) { start -= 4; WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + c += MMU_memAccessCycles(start); } } cpu->R[REG_POS(i,16)] = start; armcpu_switchMode(cpu, oldmode); - return c + 1; + return MMU_aluMemCycles(1, c); } /* @@ -7052,19 +7034,24 @@ TEMPLATE static u32 FASTCALL OP_LDRD_STRD_POST_INDEX(const u32 i) else cpu->R[REG_POS(i,16)] -= index; + u32 c = 0; if ( !(Rd_num & 0x1)) { /* Store/Load */ if ( BIT5(i)) { WRITE32(cpu->mem_if->data, addr, cpu->R[Rd_num]); WRITE32(cpu->mem_if->data, addr + 4, cpu->R[Rd_num + 1]); + c += MMU_memAccessCycles(addr); + c += MMU_memAccessCycles(addr + 4); } else { cpu->R[Rd_num] = READ32(cpu->mem_if->data, addr); cpu->R[Rd_num + 1] = READ32(cpu->mem_if->data, addr + 4); + c += MMU_memAccessCycles(addr); + c += MMU_memAccessCycles(addr + 4); } } - return 3 + (MMU.MMU_WAIT32[PROCNUM][(addr>>24)&0xF] * 2); + return MMU_aluMemCycles(3, c); } TEMPLATE static u32 FASTCALL OP_LDRD_STRD_OFFSET_PRE_INDEX(const u32 i) @@ -7095,19 +7082,24 @@ TEMPLATE static u32 FASTCALL OP_LDRD_STRD_OFFSET_PRE_INDEX(const u32 i) cpu->R[REG_POS(i,16)] = addr; } + u32 c = 0; if ( !(Rd_num & 0x1)) { /* Store/Load */ if ( BIT5(i)) { WRITE32(cpu->mem_if->data, addr, cpu->R[Rd_num]); WRITE32(cpu->mem_if->data, addr + 4, cpu->R[Rd_num + 1]); + c += MMU_memAccessCycles(addr); + c += MMU_memAccessCycles(addr + 4); } else { cpu->R[Rd_num] = READ32(cpu->mem_if->data, addr); cpu->R[Rd_num + 1] = READ32(cpu->mem_if->data, addr + 4); + c += MMU_memAccessCycles(addr); + c += MMU_memAccessCycles(addr + 4); } } - return 3 + (MMU.MMU_WAIT32[PROCNUM][(addr>>24)&0xF] * 2); + return MMU_aluMemCycles(3, c); } diff --git a/desmume/src/armcpu.cpp b/desmume/src/armcpu.cpp index b35333fb4..02f100dc9 100644 --- a/desmume/src/armcpu.cpp +++ b/desmume/src/armcpu.cpp @@ -30,6 +30,7 @@ #include "debug.h" #include "Disassembler.h" #include "NDSSystem.h" +#include "MMU_timing.h" template static u32 armcpu_prefetch(); @@ -391,7 +392,7 @@ FORCEINLINE static u32 armcpu_prefetch() armcpu->R[15] = curInstruction + 8; #endif - return MMU.MMU_WAIT32[PROCNUM][(curInstruction>>24)&0xF]; + return MMU_codeFetchCycles(curInstruction); } u32 curInstruction = armcpu->next_instruction; @@ -413,18 +414,16 @@ FORCEINLINE static u32 armcpu_prefetch() armcpu->R[15] = curInstruction + 4; #endif -#if 0 if(PROCNUM==0) { // arm9 fetches 2 instructions at a time in thumb mode if(!(curInstruction == armcpu->instruct_adr + 2 && (curInstruction & 2))) - return MMU.MMU_WAIT32[PROCNUM][(curInstruction>>24)&0xF]; + return MMU_codeFetchCycles(curInstruction); else return 0; } -#endif - return MMU.MMU_WAIT16[PROCNUM][(curInstruction>>24)&0xF]; + return MMU_codeFetchCycles(curInstruction); } #if 0 /* not used */ @@ -531,7 +530,7 @@ u32 armcpu_exec() cFetch = armcpu_prefetch(&ARMPROC); if (ARMPROC.stalled) { - return CommonSettings.armFastFetchExecute ? std::max(cFetch, cExecute) : (cFetch + cExecute); + return MMU_fetchExecuteCycles(cExecute, cFetch); } #endif @@ -565,7 +564,7 @@ u32 armcpu_exec() #else cFetch = armcpu_prefetch(); #endif - return CommonSettings.armFastFetchExecute ? std::max(cFetch, cExecute) : (cFetch + cExecute); + return MMU_fetchExecuteCycles(cExecute, cFetch); } if(PROCNUM==0) @@ -590,7 +589,7 @@ u32 armcpu_exec() #else cFetch = armcpu_prefetch(); #endif - return CommonSettings.armFastFetchExecute ? std::max(cFetch, cExecute) : (cFetch + cExecute); + return MMU_fetchExecuteCycles(cExecute, cFetch); } //these templates needed to be instantiated manually diff --git a/desmume/src/cocoa/DeSmuME.xcodeproj/project.pbxproj b/desmume/src/cocoa/DeSmuME.xcodeproj/project.pbxproj index a33ea07a5..304f95ad8 100644 --- a/desmume/src/cocoa/DeSmuME.xcodeproj/project.pbxproj +++ b/desmume/src/cocoa/DeSmuME.xcodeproj/project.pbxproj @@ -259,6 +259,7 @@ 729BECB80D9D57AF00ED561B /* mc.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = mc.h; path = ../mc.h; sourceTree = SOURCE_ROOT; }; 729BECB90D9D57AF00ED561B /* mem.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = mem.h; path = ../mem.h; sourceTree = SOURCE_ROOT; }; 729BECBB0D9D57AF00ED561B /* MMU.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = MMU.h; path = ../MMU.h; sourceTree = SOURCE_ROOT; }; + 729BECBC0D9D57AF00ED561B /* MMU_timing.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = MMU_timing.h; path = ../MMU_timing.h; sourceTree = SOURCE_ROOT; }; 729BECBD0D9D57AF00ED561B /* NDSSystem.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = NDSSystem.h; path = ../NDSSystem.h; sourceTree = SOURCE_ROOT; }; 729BECBE0D9D57AF00ED561B /* registers.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = registers.h; path = ../registers.h; sourceTree = SOURCE_ROOT; }; 729BECC00D9D57AF00ED561B /* render3D.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = render3D.h; path = ../render3D.h; sourceTree = SOURCE_ROOT; }; @@ -491,6 +492,7 @@ 729BECB80D9D57AF00ED561B /* mc.h */, 729BECB90D9D57AF00ED561B /* mem.h */, 729BECBB0D9D57AF00ED561B /* MMU.h */, + 729BECBC0D9D57AF00ED561B /* MMU_timing.h */, 729BECBD0D9D57AF00ED561B /* NDSSystem.h */, 95D5FE4F1007BC4500882BAE /* guitarGrip.cpp */, 729BECBE0D9D57AF00ED561B /* registers.h */, diff --git a/desmume/src/mem.h b/desmume/src/mem.h index 261f7c138..a94dd6777 100644 --- a/desmume/src/mem.h +++ b/desmume/src/mem.h @@ -63,13 +63,14 @@ static INLINE u32 T1ReadLong_guaranteedAligned(u8* const mem, const u32 addr) } -static INLINE u32 T1ReadLong(u8* const mem, const u32 addr) +static INLINE u32 T1ReadLong(u8* const mem, u32 addr) { + addr &= ~3; #ifdef WORDS_BIGENDIAN return (mem[addr + 3] << 24 | mem[addr + 2] << 16 | mem[addr + 1] << 8 | mem[addr]); #else - return *((u32 *)mem + (addr>>2)); + return *(u32*)(mem + addr); #endif } diff --git a/desmume/src/saves.cpp b/desmume/src/saves.cpp index b55e1b393..be1fa9001 100644 --- a/desmume/src/saves.cpp +++ b/desmume/src/saves.cpp @@ -41,6 +41,7 @@ #include "gfx3d.h" #include "movie.h" #include "mic.h" +#include "MMU_timing.h" #include "path.h" @@ -265,11 +266,18 @@ SFORMAT SF_MOVIE[]={ static void mmu_savestate(EMUFILE* os) { - //version - write32le(2,os); + u32 version = 3; + write32le(version,os); //newer savefile system: MMU_new.backupDevice.save_state(os); + + MMU_timing.arm9codeFetch.savestate(os, version); + MMU_timing.arm9dataFetch.savestate(os, version); + MMU_timing.arm7codeFetch.savestate(os, version); + MMU_timing.arm7dataFetch.savestate(os, version); + MMU_timing.arm9codeCache.savestate(os, version); + MMU_timing.arm9dataCache.savestate(os, version); } SFORMAT SF_WIFI[]={ @@ -411,13 +419,24 @@ static bool mmu_loadstate(EMUFILE* is, int size) delete[] temp; if(is->fail()) return false; } - else if(version == 2) - { - //newer savefile system: - MMU_new.backupDevice.load_state(is); - } - return true; + if(version < 2) + return true; + + //newer savefile system: + bool ok = MMU_new.backupDevice.load_state(is); + + if(version < 3) + return ok; + + ok &= MMU_timing.arm9codeFetch.loadstate(is, version); + ok &= MMU_timing.arm9dataFetch.loadstate(is, version); + ok &= MMU_timing.arm7codeFetch.loadstate(is, version); + ok &= MMU_timing.arm7dataFetch.loadstate(is, version); + ok &= MMU_timing.arm9codeCache.loadstate(is, version); + ok &= MMU_timing.arm9dataCache.loadstate(is, version); + + return ok; } static void cp15_saveone(armcp15_t *cp15, EMUFILE* os) diff --git a/desmume/src/thumb_instructions.cpp b/desmume/src/thumb_instructions.cpp index 751283552..f36213ae8 100644 --- a/desmume/src/thumb_instructions.cpp +++ b/desmume/src/thumb_instructions.cpp @@ -29,6 +29,7 @@ #include "MMU.h" #include "NDSSystem.h" #include "thumb_instructions.h" +#include "MMU_timing.h" #include #define cpu (&ARMPROC) @@ -547,7 +548,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_PCREL(const u32 i) cpu->R[REG_NUM(cpu->instruction, 8)] = READ32(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3, adr); } TEMPLATE static u32 FASTCALL OP_STR_REG_OFF(const u32 i) @@ -555,7 +556,7 @@ TEMPLATE static u32 FASTCALL OP_STR_REG_OFF(const u32 i) u32 adr = cpu->R[REG_NUM(i, 6)] + cpu->R[REG_NUM(i, 3)]; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 0)]); - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2, adr); } TEMPLATE static u32 FASTCALL OP_STRH_REG_OFF(const u32 i) @@ -563,7 +564,7 @@ TEMPLATE static u32 FASTCALL OP_STRH_REG_OFF(const u32 i) u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; WRITE16(cpu->mem_if->data, adr, ((u16)cpu->R[REG_NUM(i, 0)])); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2, adr); } TEMPLATE static u32 FASTCALL OP_STRB_REG_OFF(const u32 i) @@ -571,7 +572,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_REG_OFF(const u32 i) u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; WRITE8(cpu->mem_if->data, adr, ((u8)cpu->R[REG_NUM(i, 0)])); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2, adr); } TEMPLATE static u32 FASTCALL OP_LDRSB_REG_OFF(const u32 i) @@ -579,7 +580,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSB_REG_OFF(const u32 i) u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; cpu->R[REG_NUM(i, 0)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3, adr); } TEMPLATE static u32 FASTCALL OP_LDR_REG_OFF(const u32 i) @@ -591,7 +592,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_REG_OFF(const u32 i) tempValue = (tempValue>>adr) | (tempValue<<(32-adr)); cpu->R[REG_NUM(i, 0)] = tempValue; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3, adr); } TEMPLATE static u32 FASTCALL OP_LDRH_REG_OFF(const u32 i) @@ -599,7 +600,7 @@ TEMPLATE static u32 FASTCALL OP_LDRH_REG_OFF(const u32 i) u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; cpu->R[REG_NUM(i, 0)] = (u32)READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3, adr); } TEMPLATE static u32 FASTCALL OP_LDRB_REG_OFF(const u32 i) @@ -607,7 +608,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_REG_OFF(const u32 i) u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; cpu->R[REG_NUM(i, 0)] = (u32)READ8(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3, adr); } TEMPLATE static u32 FASTCALL OP_LDRSH_REG_OFF(const u32 i) @@ -615,7 +616,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSH_REG_OFF(const u32 i) u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; cpu->R[REG_NUM(i, 0)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3, adr); } TEMPLATE static u32 FASTCALL OP_STR_IMM_OFF(const u32 i) @@ -623,7 +624,7 @@ TEMPLATE static u32 FASTCALL OP_STR_IMM_OFF(const u32 i) u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C); WRITE32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 0)]); - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2, adr); } TEMPLATE static u32 FASTCALL OP_LDR_IMM_OFF(const u32 i) @@ -634,7 +635,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_IMM_OFF(const u32 i) tempValue = (tempValue>>adr) | (tempValue<<(32-adr)); cpu->R[REG_NUM(i, 0)] = tempValue; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3, adr); } TEMPLATE static u32 FASTCALL OP_STRB_IMM_OFF(const u32 i) @@ -642,7 +643,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_IMM_OFF(const u32 i) u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F); WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_NUM(i, 0)]); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2, adr); } TEMPLATE static u32 FASTCALL OP_LDRB_IMM_OFF(const u32 i) @@ -650,7 +651,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_IMM_OFF(const u32 i) u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F); cpu->R[REG_NUM(i, 0)] = READ8(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3, adr); } TEMPLATE static u32 FASTCALL OP_STRH_IMM_OFF(const u32 i) @@ -658,7 +659,7 @@ TEMPLATE static u32 FASTCALL OP_STRH_IMM_OFF(const u32 i) u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E); WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_NUM(i, 0)]); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2, adr); } TEMPLATE static u32 FASTCALL OP_LDRH_IMM_OFF(const u32 i) @@ -666,7 +667,7 @@ TEMPLATE static u32 FASTCALL OP_LDRH_IMM_OFF(const u32 i) u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E); cpu->R[REG_NUM(i, 0)] = READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3, adr); } TEMPLATE static u32 FASTCALL OP_STR_SPREL(const u32 i) @@ -674,7 +675,7 @@ TEMPLATE static u32 FASTCALL OP_STR_SPREL(const u32 i) u32 adr = cpu->R[13] + ((i&0xFF)<<2); WRITE32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 8)]); - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(2, adr); } TEMPLATE static u32 FASTCALL OP_LDR_SPREL(const u32 i) @@ -682,7 +683,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_SPREL(const u32 i) u32 adr = cpu->R[13] + ((i&0xFF)<<2); cpu->R[REG_NUM(i, 8)] = READ32(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + return MMU_aluMemAccessCycles(3, adr); } TEMPLATE static u32 FASTCALL OP_ADD_2PC(const u32 i) @@ -722,12 +723,12 @@ TEMPLATE static u32 FASTCALL OP_PUSH(const u32 i) if(BIT_N(i, 7-j)) { WRITE32(cpu->mem_if->data, adr, cpu->R[7-j]); - c += MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + c += MMU_memAccessCycles(adr); adr -= 4; } cpu->R[13] = adr + 4; - return c + 3; + return MMU_aluMemCycles(3, c); } TEMPLATE static u32 FASTCALL OP_PUSH_LR(const u32 i) @@ -736,19 +737,19 @@ TEMPLATE static u32 FASTCALL OP_PUSH_LR(const u32 i) u32 c = 0, j; WRITE32(cpu->mem_if->data, adr, cpu->R[14]); - c += MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + c += MMU_memAccessCycles(adr); adr -= 4; for(j = 0; j<8; ++j) if(BIT_N(i, 7-j)) { WRITE32(cpu->mem_if->data, adr, cpu->R[7-j]); - c += MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + c += MMU_memAccessCycles(adr); adr -= 4; } cpu->R[13] = adr + 4; - return c + 4; + return MMU_aluMemCycles(4, c); } TEMPLATE static u32 FASTCALL OP_POP(const u32 i) @@ -760,12 +761,12 @@ TEMPLATE static u32 FASTCALL OP_POP(const u32 i) if(BIT_N(i, j)) { cpu->R[j] = READ32(cpu->mem_if->data, adr); - c += MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + c += MMU_memAccessCycles(adr); adr += 4; } cpu->R[13] = adr; - return c + 2; + return MMU_aluMemCycles(2, c); } TEMPLATE static u32 FASTCALL OP_POP_PC(const u32 i) @@ -778,20 +779,20 @@ TEMPLATE static u32 FASTCALL OP_POP_PC(const u32 i) if(BIT_N(i, j)) { cpu->R[j] = READ32(cpu->mem_if->data, adr); - c += MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + c += MMU_memAccessCycles(adr); adr += 4; } v = READ32(cpu->mem_if->data, adr); - c += MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + c += MMU_memAccessCycles(adr); cpu->R[15] = v & 0xFFFFFFFE; cpu->next_instruction = v & 0xFFFFFFFE; if(PROCNUM==0) cpu->CPSR.bits.T = BIT0(v); adr += 4; - cpu->R[13] = adr; - return c + 5; + cpu->R[13] = adr; + return MMU_aluMemCycles(5, c); } TEMPLATE static u32 FASTCALL OP_BKPT_THUMB(const u32 i) @@ -808,11 +809,11 @@ TEMPLATE static u32 FASTCALL OP_STMIA_THUMB(const u32 i) if(BIT_N(i, j)) { WRITE32(cpu->mem_if->data, adr, cpu->R[j]); - c += MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + c += MMU_memAccessCycles(adr); adr += 4; } cpu->R[REG_NUM(i, 8)] = adr; - return c + 2; + return MMU_aluMemCycles(2, c); } TEMPLATE static u32 FASTCALL OP_LDMIA_THUMB(const u32 i) @@ -825,7 +826,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIA_THUMB(const u32 i) if(BIT_N(i, j)) { cpu->R[j] = READ32(cpu->mem_if->data, adr); - c += MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + c += MMU_memAccessCycles(adr); adr += 4; } @@ -833,7 +834,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIA_THUMB(const u32 i) if(!BIT_N(i, regIndex)) cpu->R[regIndex] = adr; - return c + 3; + return MMU_aluMemCycles(3, c); } TEMPLATE static u32 FASTCALL OP_B_COND(const u32 i) diff --git a/desmume/src/windows/DeSmuME_2005.vcproj b/desmume/src/windows/DeSmuME_2005.vcproj index 5b01bc709..bf93b03cb 100644 --- a/desmume/src/windows/DeSmuME_2005.vcproj +++ b/desmume/src/windows/DeSmuME_2005.vcproj @@ -1378,6 +1378,10 @@ RelativePath="..\MMU.h" > + + diff --git a/desmume/src/windows/DeSmuME_2008.vcproj b/desmume/src/windows/DeSmuME_2008.vcproj index f14b2f1f7..8f892169c 100644 --- a/desmume/src/windows/DeSmuME_2008.vcproj +++ b/desmume/src/windows/DeSmuME_2008.vcproj @@ -804,6 +804,10 @@ RelativePath="..\MMU.h" > + + diff --git a/desmume/src/windows/DeSmuME_2010.vcxproj b/desmume/src/windows/DeSmuME_2010.vcxproj index 93159a0de..1976606ee 100644 --- a/desmume/src/windows/DeSmuME_2010.vcxproj +++ b/desmume/src/windows/DeSmuME_2010.vcxproj @@ -308,6 +308,7 @@ + diff --git a/desmume/src/windows/DeSmuME_2010.vcxproj.filters b/desmume/src/windows/DeSmuME_2010.vcxproj.filters index 1b72c9ade..6df73fec7 100644 --- a/desmume/src/windows/DeSmuME_2010.vcxproj.filters +++ b/desmume/src/windows/DeSmuME_2010.vcxproj.filters @@ -388,6 +388,9 @@ Core + + Core + Core diff --git a/desmume/src/windows/DeSmuME_Intel.icproj b/desmume/src/windows/DeSmuME_Intel.icproj index 21170b564..cf8fd670d 100644 --- a/desmume/src/windows/DeSmuME_Intel.icproj +++ b/desmume/src/windows/DeSmuME_Intel.icproj @@ -559,6 +559,8 @@ RelativePath="..\MMU.cpp"/> + + + diff --git a/desmume/src/windows/main.cpp b/desmume/src/windows/main.cpp index 33fef8f6d..0fac2a4c3 100644 --- a/desmume/src/windows/main.cpp +++ b/desmume/src/windows/main.cpp @@ -1934,7 +1934,6 @@ int _main() CommonSettings.showGpu.main = GetPrivateProfileInt("Display", "MainGpu", 1, IniName) != 0; CommonSettings.showGpu.sub = GetPrivateProfileInt("Display", "SubGpu", 1, IniName) != 0; lostFocusPause = GetPrivateProfileBool("Focus", "BackgroundPause", false, IniName); - CommonSettings.armFastFetchExecute = GetPrivateProfileBool("Emulation", "FetchExecute", false, IniName); //Get Ram-Watch values RWSaveWindowPos = GetPrivateProfileBool("RamWatch", "SaveWindowPos", false, IniName); @@ -3039,8 +3038,6 @@ LRESULT CALLBACK WindowProcedure (HWND hwnd, UINT message, WPARAM wParam, LPARAM //Gray the recent ROM menu item if there are no recent ROMs DesEnableMenuItem(mainMenu, ID_FILE_RECENTROM, RecentRoms.size()>0); - DesEnableMenuItem(mainMenu, IDC_FASTFETCHEXECUTE, movieMode == MOVIEMODE_INACTIVE); - //Updated Checked menu items //Pause @@ -3116,7 +3113,6 @@ LRESULT CALLBACK WindowProcedure (HWND hwnd, UINT message, WPARAM wParam, LPARAM MainWindow->checkMenu(IDC_STATEREWINDING, staterewindingenabled == 1 ); MainWindow->checkMenu(IDC_BACKGROUNDPAUSE, lostFocusPause); - MainWindow->checkMenu(IDC_FASTFETCHEXECUTE, CommonSettings.armFastFetchExecute); //Save type const int savelist[] = {IDC_SAVETYPE1,IDC_SAVETYPE2,IDC_SAVETYPE3,IDC_SAVETYPE4,IDC_SAVETYPE5,IDC_SAVETYPE6,IDC_SAVETYPE7}; @@ -4118,11 +4114,6 @@ LRESULT CALLBACK WindowProcedure (HWND hwnd, UINT message, WPARAM wParam, LPARAM WritePrivateProfileInt("Focus", "BackgroundPause", (int)lostFocusPause, IniName); return 0; - case IDC_FASTFETCHEXECUTE: - CommonSettings.armFastFetchExecute = !CommonSettings.armFastFetchExecute; - WritePrivateProfileInt("Emulation", "FetchExecute", (int)CommonSettings.armFastFetchExecute, IniName); - return 0; - case IDC_SAVETYPE1: backup_setManualBackupType(0); return 0; case IDC_SAVETYPE2: backup_setManualBackupType(1); return 0; case IDC_SAVETYPE3: backup_setManualBackupType(2); return 0; diff --git a/desmume/src/windows/resource.h b/desmume/src/windows/resource.h index 05a2b9a54..4af76ad88 100644 --- a/desmume/src/windows/resource.h +++ b/desmume/src/windows/resource.h @@ -781,8 +781,6 @@ #define IDC_HKCOMBO 60077 #define IDD_KEYCUSTOM 60078 #define IDM_HOTKEY_CONFIG 60079 -#define IDC_FASTFETCHEXECUTE 60080 - #define IDM_RENDER_HQ2XS 60081 #define IDM_RENDER_LQ2X 60082 #define IDM_RENDER_LQ2XS 60083 diff --git a/desmume/src/windows/resources.rc b/desmume/src/windows/resources.rc index 01838e6c37e5852b3db34a9cbc829230d426bd94..5a572904299dca145f8bfe15eb8861b2839d5cc7 100644 GIT binary patch delta 63 zcmbO-U;4=`=?!Q6raSy)RcNm8Z?EuY++N|&lwbuCQQF?t#gy=Idfio4rS>T`%s|Yt PeM$|hLc?~TY{(@5a+DiH delta 363 zcmaDdOM1$D=?!Q6rYF2$m63O2NMtBxC}B`waAQaX(#Z@N47v=i3>83LGDGR~gEh>u z(-#yob4fcg1T%yHRk;F5X9f=-9RbA74517m(;0uW>NmgfYk%X%xc!YEQ-T$h4L97L m*U6Odar%TBW-2<_u>C_7GZ3?E|4_xM&_G2uZwCfQ@+AOzA6te1