From c97ba8fb161573366e854449e46befa7d7c12a90 Mon Sep 17 00:00:00 2001 From: zeromus Date: Mon, 10 Apr 2023 11:43:46 -0400 Subject: [PATCH] fix spurious RRX variant selection in several disassembly macros (fixes #652 maybe) --- desmume/src/frontend/modules/Disassembler.cpp | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/desmume/src/frontend/modules/Disassembler.cpp b/desmume/src/frontend/modules/Disassembler.cpp index 8dbe881cd..506f9485b 100644 --- a/desmume/src/frontend/modules/Disassembler.cpp +++ b/desmume/src/frontend/modules/Disassembler.cpp @@ -93,8 +93,10 @@ const char MSR_FIELD[16][5] = { Registre[REG_POS(i,0)],\ tmp); #define DATAPROC_ROR_IMM(nom, s) char tmp[10] = "";\ - if(((i>>7)&0x1F)!=0)\ + if(((i>>7)&0x1F)==0)\ sprintf(tmp, ", RRX");\ + else\ + sprintf(tmp, ", ROR %d", (int)((i>>7)&0x1F));\ sprintf(txt, "%s%s%s %s, %s, %s%s",\ #nom,\ Condition[CONDITION(i)],\ @@ -208,8 +210,10 @@ const char MSR_FIELD[16][5] = { tmp,\ op3); #define LDRSTR_ROR_IMM(nom, op, op2, op3) char tmp[10] = "";\ - if(((i>>7)&0x1F)!=0)\ + if(((i>>7)&0x1F)==0)\ sprintf(tmp, ", RRX");\ + else\ + sprintf(tmp, ", ROR %d", (int)((i>>7)&0x1F));\ sprintf(txt, "%s%s %s, [%s%s, %s%s%s%s",\ #nom,\ Condition[CONDITION(i)],\