From b45daf7e74993526391a94285f77ca7ecc6de3e2 Mon Sep 17 00:00:00 2001 From: yabause Date: Sat, 14 Oct 2006 11:58:27 +0000 Subject: [PATCH] - Changed configure.ac so Mac OS X uses fs-linux.c ... I may rename it :p - Added "static" to functions in thumb_instructions.c, arm_instructions.c and Disassembler.c. They are "private" functions and they are declared both in Disassembler and arm/thumb_instructions leading to duplicate symbols in libdesmume.a --- desmume/configure.ac | 1 + desmume/src/Disassembler.c | 1214 +++++++++++++++--------------- desmume/src/arm_instructions.c | 1082 +++++++++++++------------- desmume/src/thumb_instructions.c | 140 ++-- 4 files changed, 1219 insertions(+), 1218 deletions(-) diff --git a/desmume/configure.ac b/desmume/configure.ac index 34ad3f1d1..fbe5f3538 100644 --- a/desmume/configure.ac +++ b/desmume/configure.ac @@ -6,6 +6,7 @@ AC_CANONICAL_TARGET case $target in *linux*) desmume_arch=linux;; *mingw*) desmume_arch=windows;; + *darwin*) desmume_arch=linux;; esac AC_SUBST(desmume_arch) diff --git a/desmume/src/Disassembler.c b/desmume/src/Disassembler.c index 8365e71c5..5f1e685a0 100644 --- a/desmume/src/Disassembler.c +++ b/desmume/src/Disassembler.c @@ -267,225 +267,225 @@ const char MSR_FIELD[16][5] = { }\ lreg[strlen(lreg)-1]='\0'; -char * OP_UND(u32 adr, u32 i, char * txt) +static char * OP_UND(u32 adr, u32 i, char * txt) { sprintf(txt, "----"); return txt; } //-----------------------AND------------------------------------ -char * OP_AND_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_AND_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(AND, ""); return txt; } -char * OP_AND_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_AND_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(AND, LSL, ""); return txt; } -char * OP_AND_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_AND_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(AND, LSR, ""); return txt; } -char * OP_AND_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_AND_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(AND, LSR, ""); return txt; } -char * OP_AND_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_AND_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(AND, ASR, ""); return txt; } -char * OP_AND_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_AND_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(AND, ASR, ""); return txt; } -char * OP_AND_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_AND_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(AND, ""); return txt; } -char * OP_AND_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_AND_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(AND, ROR, ""); return txt; } -char * OP_AND_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_AND_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(AND, ""); return txt; } -char * OP_AND_S_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_AND_S_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(AND, "S"); return txt; } -char * OP_AND_S_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_AND_S_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(AND, LSL, "S"); return txt; } -char * OP_AND_S_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_AND_S_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(AND, LSR, "S"); return txt; } -char * OP_AND_S_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_AND_S_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(AND, LSR, "S"); return txt; } -char * OP_AND_S_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_AND_S_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(AND, ASR, "S"); return txt; } -char * OP_AND_S_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_AND_S_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(AND, ASR, "S"); return txt; } -char * OP_AND_S_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_AND_S_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(AND, "S"); return txt; } -char * OP_AND_S_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_AND_S_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(AND, ROR, "S"); return txt; } -char * OP_AND_S_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_AND_S_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(AND, "S"); return txt; } //--------------EOR------------------------------ -char * OP_EOR_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_EOR_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(EOR, ""); return txt; } -char * OP_EOR_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_EOR_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(EOR, LSL, ""); return txt; } -char * OP_EOR_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_EOR_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(EOR, LSR, ""); return txt; } -char * OP_EOR_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_EOR_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(EOR, LSR, ""); return txt; } -char * OP_EOR_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_EOR_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(EOR, ASR, ""); return txt; } -char * OP_EOR_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_EOR_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(EOR, ASR, ""); return txt; } -char * OP_EOR_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_EOR_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(EOR, ""); return txt; } -char * OP_EOR_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_EOR_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(EOR, ROR, ""); return txt; } -char * OP_EOR_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_EOR_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(EOR, ""); return txt; } -char * OP_EOR_S_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_EOR_S_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(EOR, "S"); return txt; } -char * OP_EOR_S_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_EOR_S_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(EOR, LSL, "S"); return txt; } -char * OP_EOR_S_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_EOR_S_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(EOR, LSR, "S"); return txt; } -char * OP_EOR_S_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_EOR_S_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(EOR, LSR, "S"); return txt; } -char * OP_EOR_S_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_EOR_S_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(EOR, ASR, "S"); return txt; } -char * OP_EOR_S_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_EOR_S_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(EOR, ASR, "S"); return txt; } -char * OP_EOR_S_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_EOR_S_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(EOR, "S"); return txt; } -char * OP_EOR_S_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_EOR_S_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(EOR, ROR, "S"); return txt; } -char * OP_EOR_S_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_EOR_S_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(EOR, "S"); return txt; @@ -493,1113 +493,1113 @@ char * OP_EOR_S_IMM_VAL(u32 adr, u32 i, char * txt) //-------------SUB------------------------------------- -char * OP_SUB_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_SUB_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(SUB, ""); return txt; } -char * OP_SUB_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_SUB_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(SUB, LSL, ""); return txt; } -char * OP_SUB_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_SUB_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(SUB, LSR, ""); return txt; } -char * OP_SUB_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_SUB_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(SUB, LSR, ""); return txt; } -char * OP_SUB_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_SUB_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(SUB, ASR, ""); return txt; } -char * OP_SUB_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_SUB_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(SUB, ASR, ""); return txt;} -char * OP_SUB_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_SUB_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(SUB, ""); return txt;} -char * OP_SUB_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_SUB_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(SUB, ROR, ""); return txt;} -char * OP_SUB_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_SUB_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(SUB, ""); return txt;} -char * OP_SUB_S_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_SUB_S_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(SUB, "S"); return txt;} -char * OP_SUB_S_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_SUB_S_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(SUB, LSL, "S"); return txt;} -char * OP_SUB_S_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_SUB_S_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(SUB, LSR, "S"); return txt;} -char * OP_SUB_S_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_SUB_S_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(SUB, LSR, "S"); return txt;} -char * OP_SUB_S_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_SUB_S_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(SUB, ASR, "S"); return txt;} -char * OP_SUB_S_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_SUB_S_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(SUB, ASR, "S"); return txt;} -char * OP_SUB_S_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_SUB_S_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(SUB, "S"); return txt;} -char * OP_SUB_S_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_SUB_S_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(SUB, ROR, "S"); return txt;} -char * OP_SUB_S_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_SUB_S_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(SUB, "S"); return txt;} //------------------RSB------------------------ -char * OP_RSB_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_RSB_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(RSB, ""); return txt;} -char * OP_RSB_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_RSB_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(RSB, LSL, ""); return txt;} -char * OP_RSB_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_RSB_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(RSB, LSR, ""); return txt;} -char * OP_RSB_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_RSB_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(RSB, LSR, ""); return txt;} -char * OP_RSB_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_RSB_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(RSB, ASR, ""); return txt;} -char * OP_RSB_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_RSB_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(RSB, ASR, ""); return txt;} -char * OP_RSB_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_RSB_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(RSB, ""); return txt;} -char * OP_RSB_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_RSB_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(RSB, ROR, ""); return txt;} -char * OP_RSB_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_RSB_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(RSB, ""); return txt;} -char * OP_RSB_S_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_RSB_S_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(RSB, "S"); return txt;} -char * OP_RSB_S_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_RSB_S_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(RSB, LSL, "S"); return txt;} -char * OP_RSB_S_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_RSB_S_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(RSB, LSR, "S"); return txt;} -char * OP_RSB_S_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_RSB_S_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(RSB, LSR, "S"); return txt;} -char * OP_RSB_S_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_RSB_S_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(RSB, ASR, "S"); return txt;} -char * OP_RSB_S_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_RSB_S_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(RSB, ASR, "S"); return txt;} -char * OP_RSB_S_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_RSB_S_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(RSB, "S"); return txt;} -char * OP_RSB_S_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_RSB_S_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(RSB, ROR, "S"); return txt;} -char * OP_RSB_S_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_RSB_S_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(RSB, "S"); return txt;} //------------------ADD----------------------------------- -char * OP_ADD_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_ADD_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(ADD, ""); return txt;} -char * OP_ADD_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_ADD_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ADD, LSL, ""); return txt;} -char * OP_ADD_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_ADD_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(ADD, LSR, ""); return txt;} -char * OP_ADD_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_ADD_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ADD, LSR, ""); return txt;} -char * OP_ADD_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_ADD_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(ADD, ASR, ""); return txt;} -char * OP_ADD_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_ADD_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ADD, ASR, ""); return txt;} -char * OP_ADD_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_ADD_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(ADD, ""); return txt;} -char * OP_ADD_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_ADD_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ADD, ROR, ""); return txt;} -char * OP_ADD_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_ADD_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(ADD, ""); return txt;} -char * OP_ADD_S_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_ADD_S_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(ADD, "S"); return txt;} -char * OP_ADD_S_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_ADD_S_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ADD, LSL, "S"); return txt;} -char * OP_ADD_S_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_ADD_S_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(ADD, LSR, "S"); return txt;} -char * OP_ADD_S_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_ADD_S_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ADD, LSR, "S"); return txt;} -char * OP_ADD_S_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_ADD_S_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(ADD, ASR, "S"); return txt;} -char * OP_ADD_S_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_ADD_S_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ADD, ASR, "S"); return txt;} -char * OP_ADD_S_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_ADD_S_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(ADD, "S"); return txt;} -char * OP_ADD_S_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_ADD_S_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ADD, ROR, "S"); return txt;} -char * OP_ADD_S_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_ADD_S_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(ADD, "S"); return txt;} //------------------ADC----------------------------------- -char * OP_ADC_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_ADC_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(ADC, ""); return txt;} -char * OP_ADC_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_ADC_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ADC, LSL, ""); return txt;} -char * OP_ADC_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_ADC_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(ADC, LSR, ""); return txt;} -char * OP_ADC_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_ADC_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ADC, LSR, ""); return txt;} -char * OP_ADC_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_ADC_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(ADC, ASR, ""); return txt;} -char * OP_ADC_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_ADC_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ADC, ASR, ""); return txt;} -char * OP_ADC_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_ADC_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(ADC, ""); return txt;} -char * OP_ADC_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_ADC_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ADC, ROR, ""); return txt;} -char * OP_ADC_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_ADC_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(ADC, ""); return txt;} -char * OP_ADC_S_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_ADC_S_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(ADC, "S"); return txt;} -char * OP_ADC_S_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_ADC_S_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ADC, LSL, "S"); return txt;} -char * OP_ADC_S_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_ADC_S_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(ADC, LSR, "S"); return txt;} -char * OP_ADC_S_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_ADC_S_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ADC, LSR, "S"); return txt;} -char * OP_ADC_S_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_ADC_S_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(ADC, ASR, "S"); return txt;} -char * OP_ADC_S_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_ADC_S_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ADC, ASR, "S"); return txt;} -char * OP_ADC_S_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_ADC_S_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(ADC, "S"); return txt;} -char * OP_ADC_S_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_ADC_S_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ADC, ROR, "S"); return txt;} -char * OP_ADC_S_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_ADC_S_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(ADC, "S"); return txt;} //-------------SBC------------------------------------- -char * OP_SBC_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_SBC_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(SBC, ""); return txt;} -char * OP_SBC_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_SBC_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(SBC, LSL, ""); return txt;} -char * OP_SBC_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_SBC_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(SBC, LSR, ""); return txt;} -char * OP_SBC_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_SBC_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(SBC, LSR, ""); return txt;} -char * OP_SBC_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_SBC_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(SBC, ASR, ""); return txt;} -char * OP_SBC_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_SBC_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(SBC, ASR, ""); return txt;} -char * OP_SBC_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_SBC_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(SBC, ""); return txt;} -char * OP_SBC_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_SBC_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(SBC, ROR, ""); return txt;} -char * OP_SBC_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_SBC_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(SBC, ""); return txt;} -char * OP_SBC_S_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_SBC_S_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(SBC, "S"); return txt;} -char * OP_SBC_S_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_SBC_S_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(SBC, LSL, "S"); return txt;} -char * OP_SBC_S_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_SBC_S_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(SBC, LSR, "S"); return txt;} -char * OP_SBC_S_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_SBC_S_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(SBC, LSR, "S"); return txt;} -char * OP_SBC_S_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_SBC_S_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(SBC, ASR, "S"); return txt;} -char * OP_SBC_S_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_SBC_S_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(SBC, ASR, "S"); return txt;} -char * OP_SBC_S_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_SBC_S_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(SBC, "S"); return txt;} -char * OP_SBC_S_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_SBC_S_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(SBC, ROR, "S"); return txt;} -char * OP_SBC_S_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_SBC_S_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(SBC, "S"); return txt;} //---------------RSC---------------------------------- -char * OP_RSC_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_RSC_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(RSC, ""); return txt;} -char * OP_RSC_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_RSC_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(RSC, LSL, ""); return txt;} -char * OP_RSC_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_RSC_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(RSC, LSR, ""); return txt;} -char * OP_RSC_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_RSC_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(RSC, LSR, ""); return txt;} -char * OP_RSC_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_RSC_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(RSC, ASR, ""); return txt;} -char * OP_RSC_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_RSC_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(RSC, ASR, ""); return txt;} -char * OP_RSC_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_RSC_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(RSC, ""); return txt;} -char * OP_RSC_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_RSC_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(RSC, ROR, ""); return txt;} -char * OP_RSC_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_RSC_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(RSC, ""); return txt;} -char * OP_RSC_S_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_RSC_S_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(RSC, "S"); return txt;} -char * OP_RSC_S_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_RSC_S_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(RSC, LSL, "S"); return txt;} -char * OP_RSC_S_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_RSC_S_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(RSC, LSR, "S"); return txt;} -char * OP_RSC_S_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_RSC_S_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(RSC, LSR, "S"); return txt;} -char * OP_RSC_S_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_RSC_S_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(RSC, ASR, "S"); return txt;} -char * OP_RSC_S_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_RSC_S_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(RSC, ASR, "S"); return txt;} -char * OP_RSC_S_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_RSC_S_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(RSC, "S"); return txt;} -char * OP_RSC_S_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_RSC_S_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(RSC, ROR, "S"); return txt;} -char * OP_RSC_S_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_RSC_S_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(RSC, "S"); return txt;} //-------------------TST---------------------------- -char * OP_TST_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_TST_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_LSL_IMM(TST, "", 16); return txt;} -char * OP_TST_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_TST_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(TST, LSL, "", 16); return txt;} -char * OP_TST_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_TST_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_SHIFT(TST, LSR, "", 16); return txt;} -char * OP_TST_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_TST_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(TST, LSR, "", 16); return txt;} -char * OP_TST_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_TST_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_SHIFT(TST, ASR, "", 16); return txt;} -char * OP_TST_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_TST_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(TST, ASR, "", 16); return txt;} -char * OP_TST_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_TST_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_ROR_IMM(TST, "", 16); return txt;} -char * OP_TST_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_TST_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(TST, ROR, "", 16); return txt;} -char * OP_TST_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_TST_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_VALUE(TST, "", 16); return txt;} //-------------------TEQ---------------------------- -char * OP_TEQ_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_TEQ_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_LSL_IMM(TEQ, "", 16); return txt;} -char * OP_TEQ_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_TEQ_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(TEQ, LSL, "", 16); return txt;} -char * OP_TEQ_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_TEQ_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_SHIFT(TEQ, LSR, "", 16); return txt;} -char * OP_TEQ_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_TEQ_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(TEQ, LSR, "", 16); return txt;} -char * OP_TEQ_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_TEQ_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_SHIFT(TEQ, ASR, "", 16); return txt;} -char * OP_TEQ_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_TEQ_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(TEQ, ASR, "", 16); return txt;} -char * OP_TEQ_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_TEQ_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_ROR_IMM(TEQ, "", 16); return txt;} -char * OP_TEQ_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_TEQ_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(TEQ, ROR, "", 16); return txt;} -char * OP_TEQ_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_TEQ_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_VALUE(TEQ, "", 16); return txt;} //-------------CMP------------------------------------- -char * OP_CMP_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_CMP_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_LSL_IMM(CMP, "", 16); return txt;} -char * OP_CMP_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_CMP_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(CMP, LSL, "", 16); return txt;} -char * OP_CMP_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_CMP_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_SHIFT(CMP, LSR, "", 16); return txt;} -char * OP_CMP_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_CMP_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(CMP, LSR, "", 16); return txt;} -char * OP_CMP_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_CMP_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_SHIFT(CMP, ASR, "", 16); return txt;} -char * OP_CMP_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_CMP_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(CMP, ASR, "", 16); return txt;} -char * OP_CMP_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_CMP_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_ROR_IMM(CMP, "", 16); return txt;} -char * OP_CMP_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_CMP_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(CMP, ROR, "", 16); return txt;} -char * OP_CMP_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_CMP_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_VALUE(CMP, "", 16); return txt;} //---------------CMN--------------------------- -char * OP_CMN_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_CMN_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_LSL_IMM(CMN, "", 16); return txt;} -char * OP_CMN_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_CMN_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(CMN, LSL, "", 16); return txt;} -char * OP_CMN_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_CMN_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_SHIFT(CMP, ASR, "", 16); return txt;} -char * OP_CMN_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_CMN_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(CMN, LSR, "", 16); return txt;} -char * OP_CMN_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_CMN_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_SHIFT(CMN, ASR, "", 16); return txt;} -char * OP_CMN_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_CMN_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(CMN, ASR, "", 16); return txt;} -char * OP_CMN_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_CMN_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_ROR_IMM(CMN, "", 16); return txt;} -char * OP_CMN_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_CMN_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(CMN, ROR, "", 16); return txt;} -char * OP_CMN_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_CMN_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_VALUE(CMN, "", 16); return txt;} //------------------ORR------------------- -char * OP_ORR_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_ORR_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(ORR, ""); return txt;} -char * OP_ORR_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_ORR_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ORR, LSL, ""); return txt;} -char * OP_ORR_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_ORR_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(ORR, LSR, ""); return txt;} -char * OP_ORR_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_ORR_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ORR, LSR, ""); return txt;} -char * OP_ORR_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_ORR_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(ORR, ASR, ""); return txt;} -char * OP_ORR_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_ORR_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ORR, ASR, ""); return txt;} -char * OP_ORR_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_ORR_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(ORR, ""); return txt;} -char * OP_ORR_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_ORR_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ORR, ROR, ""); return txt;} -char * OP_ORR_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_ORR_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(ORR, ""); return txt;} -char * OP_ORR_S_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_ORR_S_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(ORR, "S"); return txt;} -char * OP_ORR_S_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_ORR_S_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ORR, LSL, "S"); return txt;} -char * OP_ORR_S_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_ORR_S_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(ORR, LSR, "S"); return txt;} -char * OP_ORR_S_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_ORR_S_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ORR, LSR, "S"); return txt;} -char * OP_ORR_S_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_ORR_S_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(ORR, ASR, "S"); return txt;} -char * OP_ORR_S_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_ORR_S_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ORR, ASR, "S"); return txt;} -char * OP_ORR_S_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_ORR_S_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(ORR, "S"); return txt;} -char * OP_ORR_S_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_ORR_S_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(ORR, ROR, "S"); return txt;} -char * OP_ORR_S_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_ORR_S_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(ORR, "S"); return txt;} //------------------MOV------------------- -char * OP_MOV_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_MOV_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_LSL_IMM(MOV, "", 12); return txt;} -char * OP_MOV_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_MOV_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(MOV, LSL, "", 12); return txt;} -char * OP_MOV_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_MOV_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_SHIFT(MOV, LSR, "", 12); return txt;} -char * OP_MOV_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_MOV_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(MOV, LSR, "", 12); return txt;} -char * OP_MOV_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_MOV_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_SHIFT(MOV, ASR, "", 12); return txt;} -char * OP_MOV_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_MOV_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(MOV, ASR, "", 12); return txt;} -char * OP_MOV_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_MOV_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_ROR_IMM(MOV, "", 12); return txt;} -char * OP_MOV_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_MOV_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(MOV, ROR, "", 12); return txt;} -char * OP_MOV_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_MOV_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_VALUE(MOV, "", 12); return txt;} -char * OP_MOV_S_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_MOV_S_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_LSL_IMM(MOV, "S", 12); return txt;} -char * OP_MOV_S_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_MOV_S_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(MOV, LSL, "S", 12); return txt;} -char * OP_MOV_S_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_MOV_S_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_SHIFT(MOV, LSR, "S", 12); return txt;} -char * OP_MOV_S_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_MOV_S_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(MOV, LSR, "S", 12); return txt;} -char * OP_MOV_S_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_MOV_S_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_SHIFT(MOV, ASR, "S", 12); return txt;} -char * OP_MOV_S_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_MOV_S_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(MOV, ASR, "S", 12); return txt;} -char * OP_MOV_S_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_MOV_S_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_ROR_IMM(MOV, "S", 12); return txt;} -char * OP_MOV_S_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_MOV_S_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(MOV, ROR, "S", 12); return txt;} -char * OP_MOV_S_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_MOV_S_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_VALUE(MOV, "S", 12); return txt;} //------------------BIC------------------- -char * OP_BIC_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_BIC_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(BIC, ""); return txt;} -char * OP_BIC_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_BIC_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(BIC, LSL, ""); return txt;} -char * OP_BIC_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_BIC_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(BIC, LSR, ""); return txt;} -char * OP_BIC_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_BIC_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(BIC, LSR, ""); return txt;} -char * OP_BIC_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_BIC_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(BIC, ASR, ""); return txt;} -char * OP_BIC_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_BIC_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(BIC, ASR, ""); return txt;} -char * OP_BIC_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_BIC_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(BIC, ""); return txt;} -char * OP_BIC_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_BIC_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(BIC, ROR, ""); return txt;} -char * OP_BIC_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_BIC_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(BIC, ""); return txt;} -char * OP_BIC_S_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_BIC_S_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_LSL_IMM(BIC, "S"); return txt;} -char * OP_BIC_S_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_BIC_S_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(BIC, LSL, "S"); return txt;} -char * OP_BIC_S_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_BIC_S_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(BIC, LSR, "S"); return txt;} -char * OP_BIC_S_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_BIC_S_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(BIC, LSR, "S"); return txt;} -char * OP_BIC_S_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_BIC_S_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_IMM_SHIFT(BIC, ASR, "S"); return txt;} -char * OP_BIC_S_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_BIC_S_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(BIC, ASR, "S"); return txt;} -char * OP_BIC_S_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_BIC_S_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ROR_IMM(BIC, "S"); return txt;} -char * OP_BIC_S_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_BIC_S_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_REG_SHIFT(BIC, ROR, "S"); return txt;} -char * OP_BIC_S_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_BIC_S_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_IMM_VALUE(BIC, "S"); return txt;} //------------------MVN------------------- -char * OP_MVN_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_MVN_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_LSL_IMM(MVN, "", 12); return txt;} -char * OP_MVN_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_MVN_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(MVN, LSL, "", 12); return txt;} -char * OP_MVN_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_MVN_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_SHIFT(MVN, LSR, "", 12); return txt;} -char * OP_MVN_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_MVN_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(MVN, LSR, "", 12); return txt;} -char * OP_MVN_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_MVN_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_SHIFT(MVN, ASR, "", 12); return txt;} -char * OP_MVN_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_MVN_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(MVN, ASR, "", 12); return txt;} -char * OP_MVN_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_MVN_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_ROR_IMM(MVN, "", 12); return txt;} -char * OP_MVN_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_MVN_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(MVN, ROR, "", 12); return txt;} -char * OP_MVN_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_MVN_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_VALUE(MVN, "", 12); return txt;} -char * OP_MVN_S_LSL_IMM(u32 adr, u32 i, char * txt) +static char * OP_MVN_S_LSL_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_LSL_IMM(MVN, "S", 12); return txt;} -char * OP_MVN_S_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_MVN_S_LSL_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(MVN, LSL, "S", 12); return txt;} -char * OP_MVN_S_LSR_IMM(u32 adr, u32 i, char * txt) +static char * OP_MVN_S_LSR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_SHIFT(MVN, LSR, "S", 12); return txt;} -char * OP_MVN_S_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_MVN_S_LSR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(MVN, LSR, "S", 12); return txt;} -char * OP_MVN_S_ASR_IMM(u32 adr, u32 i, char * txt) +static char * OP_MVN_S_ASR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_SHIFT(MOV, ASR, "S", 12); return txt;} -char * OP_MVN_S_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_MVN_S_ASR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(MVN, ASR, "S", 12); return txt;} -char * OP_MVN_S_ROR_IMM(u32 adr, u32 i, char * txt) +static char * OP_MVN_S_ROR_IMM(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_ROR_IMM(MVN, "S", 12); return txt;} -char * OP_MVN_S_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_MVN_S_ROR_REG(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_REG_SHIFT(MVN, ROR, "S", 12); return txt;} -char * OP_MVN_S_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_MVN_S_IMM_VAL(u32 adr, u32 i, char * txt) { DATAPROC_ONE_OP_IMM_VALUE(MVN, "S", 12); return txt;} @@ -1607,22 +1607,22 @@ return txt;} //-------------MUL------------------------ -char * OP_MUL(u32 adr, u32 i, char * txt) +static char * OP_MUL(u32 adr, u32 i, char * txt) { sprintf(txt, "MUL%s %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} -char * OP_MLA(u32 adr, u32 i, char * txt) +static char * OP_MLA(u32 adr, u32 i, char * txt) { sprintf(txt, "MLA%s %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)], Registre[REG_POS(i,12)]); return txt;} -char * OP_MUL_S(u32 adr, u32 i, char * txt) +static char * OP_MUL_S(u32 adr, u32 i, char * txt) { sprintf(txt, "MUL%sS %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} -char * OP_MLA_S(u32 adr, u32 i, char * txt) +static char * OP_MLA_S(u32 adr, u32 i, char * txt) { sprintf(txt, "MLA%sS %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)], Registre[REG_POS(i,12)]); return txt;} @@ -1630,355 +1630,355 @@ return txt;} //----------UMUL-------------------------- -char * OP_UMULL(u32 adr, u32 i, char * txt) +static char * OP_UMULL(u32 adr, u32 i, char * txt) { sprintf(txt, "UMULL%s %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} -char * OP_UMLAL(u32 adr, u32 i, char * txt) +static char * OP_UMLAL(u32 adr, u32 i, char * txt) { sprintf(txt, "UMLAL%s %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} -char * OP_UMULL_S(u32 adr, u32 i, char * txt) +static char * OP_UMULL_S(u32 adr, u32 i, char * txt) { sprintf(txt, "UMULL%sS %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} -char * OP_UMLAL_S(u32 adr, u32 i, char * txt) +static char * OP_UMLAL_S(u32 adr, u32 i, char * txt) { sprintf(txt, "UMLAL%sS %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} //----------SMUL-------------------------- -char * OP_SMULL(u32 adr, u32 i, char * txt) +static char * OP_SMULL(u32 adr, u32 i, char * txt) { sprintf(txt, "SMULL%s %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} -char * OP_SMLAL(u32 adr, u32 i, char * txt) +static char * OP_SMLAL(u32 adr, u32 i, char * txt) { sprintf(txt, "SMLAL%s %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} -char * OP_SMULL_S(u32 adr, u32 i, char * txt) +static char * OP_SMULL_S(u32 adr, u32 i, char * txt) { sprintf(txt, "SMULL%sS %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} -char * OP_SMLAL_S(u32 adr, u32 i, char * txt) +static char * OP_SMLAL_S(u32 adr, u32 i, char * txt) { sprintf(txt, "SMLAL%sS %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} //---------------SWP------------------------------ -char * OP_SWP(u32 adr, u32 i, char * txt) +static char * OP_SWP(u32 adr, u32 i, char * txt) { sprintf(txt, "SWP%s %s, %s, [%s]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,0)], Registre[REG_POS(i,16)]); return txt;} -char * OP_SWPB(u32 adr, u32 i, char * txt) +static char * OP_SWPB(u32 adr, u32 i, char * txt) { sprintf(txt, "SWPB%s %s, %s, [%s]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,0)], Registre[REG_POS(i,16)]); return txt;} //------------LDRH----------------------------- -char * OP_LDRH_P_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRH_P_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRH%s %s, [%s, #%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_LDRH_M_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRH_M_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRH%s %s, [%s, -#%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_LDRH_P_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRH_P_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRH%s %s, [%s, %s]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_LDRH_M_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRH_M_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRH%s %s, [%s, -%s]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_LDRH_PRE_INDE_P_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRH_PRE_INDE_P_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRH%s %s, [%s, #%X]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_LDRH_PRE_INDE_M_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRH_PRE_INDE_M_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRH%s %s, [%s, -#%X]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_LDRH_PRE_INDE_P_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRH_PRE_INDE_P_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRH%s %s, [%s, %s]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_LDRH_PRE_INDE_M_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRH_PRE_INDE_M_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRH%s %s, [%s, -%s]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_LDRH_POS_INDE_P_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRH_POS_INDE_P_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRH%s %s, [%s], #%X", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_LDRH_POS_INDE_M_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRH_POS_INDE_M_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRH%s %s, [%s], -#%X", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_LDRH_POS_INDE_P_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRH_POS_INDE_P_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRH%s %s, [%s], %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_LDRH_POS_INDE_M_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRH_POS_INDE_M_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRH%s %s, [%s], -%s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} //------------STRH----------------------------- -char * OP_STRH_P_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRH_P_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STRH%s %s, [%s, #%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_STRH_M_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRH_M_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STRH%s %s, [%s, -#%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_STRH_P_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRH_P_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STRH%s %s, [%s, %s]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_STRH_M_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRH_M_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STRH%s %s, [%s, -%s]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_STRH_PRE_INDE_P_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRH_PRE_INDE_P_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STRH%s %s, [%s, #%X]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_STRH_PRE_INDE_M_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRH_PRE_INDE_M_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STRH%s %s, [%s, -#%X]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_STRH_PRE_INDE_P_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRH_PRE_INDE_P_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STRH%s %s, [%s, %s]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_STRH_PRE_INDE_M_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRH_PRE_INDE_M_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STRH%s %s, [%s, -%s]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_STRH_POS_INDE_P_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRH_POS_INDE_P_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STRH%s %s, [%s], #%X", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_STRH_POS_INDE_M_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRH_POS_INDE_M_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STRH%s %s, [%s], -#%X", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_STRH_POS_INDE_P_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRH_POS_INDE_P_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STRH%s %s, [%s], %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_STRH_POS_INDE_M_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRH_POS_INDE_M_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STRH%s %s, [%s], -%s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} //----------------LDRSH-------------------------- -char * OP_LDRSH_P_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSH_P_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSH%s %s, [%s, #%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_LDRSH_M_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSH_M_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSH%s %s, [%s, -#%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_LDRSH_P_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSH_P_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSH%s %s, [%s, %s]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_LDRSH_M_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSH_M_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSH%s %s, [%s, -%s]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_LDRSH_PRE_INDE_P_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSH_PRE_INDE_P_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSH%s %s, [%s, #%X]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_LDRSH_PRE_INDE_M_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSH_PRE_INDE_M_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSH%s %s, [%s, -#%X]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_LDRSH_PRE_INDE_P_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSH_PRE_INDE_P_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSH%s %s, [%s, %s]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_LDRSH_PRE_INDE_M_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSH_PRE_INDE_M_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSH%s %s, [%s, -%s]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_LDRSH_POS_INDE_P_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSH_POS_INDE_P_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSH%s %s, [%s], #%X", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_LDRSH_POS_INDE_M_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSH_POS_INDE_M_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSH%s %s, [%s], -#%X", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_LDRSH_POS_INDE_P_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSH_POS_INDE_P_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSH%s %s, [%s], %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_LDRSH_POS_INDE_M_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSH_POS_INDE_M_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSH%s %s, [%s], -%s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} //----------------------LDRSB---------------------- -char * OP_LDRSB_P_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSB_P_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSB%s %s, [%s, #%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_LDRSB_M_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSB_M_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSB%s %s, [%s, -#%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_LDRSB_P_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSB_P_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSB%s %s, [%s, %s]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_LDRSB_M_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSB_M_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSB%s %s, [%s, -%s]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_LDRSB_PRE_INDE_P_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSB_PRE_INDE_P_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSB%s %s, [%s, #%X]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_LDRSB_PRE_INDE_M_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSB_PRE_INDE_M_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSB%s %s, [%s, -#%X]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_LDRSB_PRE_INDE_P_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSB_PRE_INDE_P_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSB%s %s, [%s, %s]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_LDRSB_PRE_INDE_M_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSB_PRE_INDE_M_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSB%s %s, [%s, -%s]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_LDRSB_POS_INDE_P_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSB_POS_INDE_P_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSB%s %s, [%s], #%X", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_LDRSB_POS_INDE_M_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSB_POS_INDE_M_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSB%s %s, [%s], -#%X", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(((i>>4)&0xF0)|(i&0xF))); return txt;} -char * OP_LDRSB_POS_INDE_P_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSB_POS_INDE_P_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSB%s %s, [%s], %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_LDRSB_POS_INDE_M_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSB_POS_INDE_M_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSB%s %s, [%s], -%s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} //--------------MRS-------------------------------- -char * OP_MRS_CPSR(u32 adr, u32 i, char * txt) +static char * OP_MRS_CPSR(u32 adr, u32 i, char * txt) { sprintf(txt, "MRS%s %s, CPSR", Condition[CONDITION(i)], Registre[REG_POS(i,12)]); return txt;} -char * OP_MRS_SPSR(u32 adr, u32 i, char * txt) +static char * OP_MRS_SPSR(u32 adr, u32 i, char * txt) { sprintf(txt, "MRS%s %s, SPSR", Condition[CONDITION(i)], Registre[REG_POS(i,12)]); return txt;} //--------------MSR-------------------------------- -char * OP_MSR_CPSR(u32 adr, u32 i, char * txt) +static char * OP_MSR_CPSR(u32 adr, u32 i, char * txt) { sprintf(txt, "MSR%s CPSR_%s, %s", Condition[CONDITION(i)], MSR_FIELD[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_MSR_SPSR(u32 adr, u32 i, char * txt) +static char * OP_MSR_SPSR(u32 adr, u32 i, char * txt) { sprintf(txt, "MSR%s SPSR_%s, %s", Condition[CONDITION(i)], MSR_FIELD[REG_POS(i,16)], Registre[REG_POS(i,0)]); return txt;} -char * OP_MSR_CPSR_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_MSR_CPSR_IMM_VAL(u32 adr, u32 i, char * txt) { sprintf(txt, "MSR%s CPSR_%s, #%X", Condition[CONDITION(i)], MSR_FIELD[REG_POS(i,16)], (int)ROR((i&0xFF), ((i>>7)&0x1E))); return txt;} -char * OP_MSR_SPSR_IMM_VAL(u32 adr, u32 i, char * txt) +static char * OP_MSR_SPSR_IMM_VAL(u32 adr, u32 i, char * txt) { sprintf(txt, "MSR%s SPSR_%s, #%X", Condition[CONDITION(i)], MSR_FIELD[REG_POS(i,16)], (int)ROR((i&0xFF), (i>>7)&0x1E)); return txt;} //-----------------BRANCH-------------------------- -char * OP_BX(u32 adr, u32 i, char * txt) +static char * OP_BX(u32 adr, u32 i, char * txt) { sprintf(txt, "BX%s %s", Condition[CONDITION(i)], Registre[REG_POS(i,0)]); return txt;} -char * OP_BLX_REG(u32 adr, u32 i, char * txt) +static char * OP_BLX_REG(u32 adr, u32 i, char * txt) { sprintf(txt, "BLX%s %s", Condition[CONDITION(i)], Registre[REG_POS(i,0)]); return txt;} -char * OP_B(u32 adr, u32 i, char * txt) +static char * OP_B(u32 adr, u32 i, char * txt) { if(CONDITION(i)==0xF) { @@ -1987,7 +1987,7 @@ char * OP_B(u32 adr, u32 i, char * txt) sprintf(txt, "B%s %08X", Condition[CONDITION(i)], (int)(adr+(SIGNEXTEND_24(i)<<2)+8)); return txt;} -char * OP_BL(u32 adr, u32 i, char * txt) +static char * OP_BL(u32 adr, u32 i, char * txt) { if(CONDITION(i)==0xF) { @@ -1998,7 +1998,7 @@ return txt;} //----------------CLZ------------------------------- -char * OP_CLZ(u32 adr, u32 i, char * txt) +static char * OP_CLZ(u32 adr, u32 i, char * txt) { sprintf(txt, "CLZ%s %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,0)]); return txt;} @@ -2006,928 +2006,928 @@ return txt;} //--------------------QADD--QSUB------------------------------ -char * OP_QADD(u32 adr, u32 i, char * txt) +static char * OP_QADD(u32 adr, u32 i, char * txt) { sprintf(txt, "QADD%s %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,0)], Registre[REG_POS(i,16)]); return txt;} -char * OP_QSUB(u32 adr, u32 i, char * txt) +static char * OP_QSUB(u32 adr, u32 i, char * txt) { sprintf(txt, "QSUB%s %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,0)], Registre[REG_POS(i,16)]); return txt;} -char * OP_QDADD(u32 adr, u32 i, char * txt) +static char * OP_QDADD(u32 adr, u32 i, char * txt) { sprintf(txt, "QDADD%s %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,0)], Registre[REG_POS(i,16)]); return txt;} -char * OP_QDSUB(u32 adr, u32 i, char * txt) +static char * OP_QDSUB(u32 adr, u32 i, char * txt) { sprintf(txt, "QDSUB%s %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,0)], Registre[REG_POS(i,16)]); return txt;} //-----------------SMUL------------------------------- -char * OP_SMUL_B_B(u32 adr, u32 i, char * txt) +static char * OP_SMUL_B_B(u32 adr, u32 i, char * txt) { sprintf(txt, "SMULBB%s %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} -char * OP_SMUL_B_T(u32 adr, u32 i, char * txt) +static char * OP_SMUL_B_T(u32 adr, u32 i, char * txt) { sprintf(txt, "SMULBT%s %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} -char * OP_SMUL_T_B(u32 adr, u32 i, char * txt) +static char * OP_SMUL_T_B(u32 adr, u32 i, char * txt) { sprintf(txt, "SMULTB%s %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} -char * OP_SMUL_T_T(u32 adr, u32 i, char * txt) +static char * OP_SMUL_T_T(u32 adr, u32 i, char * txt) { sprintf(txt, "SMULTT%s %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} //-----------SMLA---------------------------- -char * OP_SMLA_B_B(u32 adr, u32 i, char * txt) +static char * OP_SMLA_B_B(u32 adr, u32 i, char * txt) { sprintf(txt, "SMLABB%s %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)], Registre[REG_POS(i,12)]); return txt;} -char * OP_SMLA_B_T(u32 adr, u32 i, char * txt) +static char * OP_SMLA_B_T(u32 adr, u32 i, char * txt) { sprintf(txt, "SMLABT%s %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)], Registre[REG_POS(i,12)]); return txt;} -char * OP_SMLA_T_B(u32 adr, u32 i, char * txt) +static char * OP_SMLA_T_B(u32 adr, u32 i, char * txt) { sprintf(txt, "SMLATB%s %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)], Registre[REG_POS(i,12)]); return txt;} -char * OP_SMLA_T_T(u32 adr, u32 i, char * txt) +static char * OP_SMLA_T_T(u32 adr, u32 i, char * txt) { sprintf(txt, "SMLATT%s %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)], Registre[REG_POS(i,12)]); return txt;} //--------------SMLAL--------------------------------------- -char * OP_SMLAL_B_B(u32 adr, u32 i, char * txt) +static char * OP_SMLAL_B_B(u32 adr, u32 i, char * txt) { sprintf(txt, "SMLABB%s %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} -char * OP_SMLAL_B_T(u32 adr, u32 i, char * txt) +static char * OP_SMLAL_B_T(u32 adr, u32 i, char * txt) { sprintf(txt, "SMLABT%s %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} -char * OP_SMLAL_T_B(u32 adr, u32 i, char * txt) +static char * OP_SMLAL_T_B(u32 adr, u32 i, char * txt) { sprintf(txt, "SMLATB%s %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} -char * OP_SMLAL_T_T(u32 adr, u32 i, char * txt) +static char * OP_SMLAL_T_T(u32 adr, u32 i, char * txt) { sprintf(txt, "SMLATT%s %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} //--------------SMULW-------------------- -char * OP_SMULW_B(u32 adr, u32 i, char * txt) +static char * OP_SMULW_B(u32 adr, u32 i, char * txt) { sprintf(txt, "SMULWB%s %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} -char * OP_SMULW_T(u32 adr, u32 i, char * txt) +static char * OP_SMULW_T(u32 adr, u32 i, char * txt) { sprintf(txt, "SMULWT%s %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)]); return txt;} //--------------SMLAW------------------- -char * OP_SMLAW_B(u32 adr, u32 i, char * txt) +static char * OP_SMLAW_B(u32 adr, u32 i, char * txt) { sprintf(txt, "SMLAWB%s %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)], Registre[REG_POS(i,12)]); return txt;} -char * OP_SMLAW_T(u32 adr, u32 i, char * txt) +static char * OP_SMLAW_T(u32 adr, u32 i, char * txt) { sprintf(txt, "SMLAWT%s %s, %s, %s, %s", Condition[CONDITION(i)], Registre[REG_POS(i,16)], Registre[REG_POS(i,0)], Registre[REG_POS(i,8)], Registre[REG_POS(i,12)]); return txt;} //------------LDR--------------------------- -char * OP_LDR_P_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDR_P_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDR%s %s, [%s, #%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_LDR_M_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDR_M_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDR%s %s, [%s, -#%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_LDR_P_LSL_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDR_P_LSL_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(LDR, "", "", "]"); return txt;} -char * OP_LDR_M_LSL_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDR_M_LSL_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(LDR, "-", "", "]"); return txt;} -char * OP_LDR_P_LSR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDR_P_LSR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDR, LSR, "", "", "]"); return txt;} -char * OP_LDR_M_LSR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDR_M_LSR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDR, LSR, "M", "", "]"); return txt;} -char * OP_LDR_P_ASR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDR_P_ASR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDR, ASR, "", "", "]"); return txt;} -char * OP_LDR_M_ASR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDR_M_ASR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDR, ASR, "-", "", "]"); return txt;} -char * OP_LDR_P_ROR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDR_P_ROR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(LDR, "", "", "]"); return txt;} -char * OP_LDR_M_ROR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDR_M_ROR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(LDR, "-", "", "]"); return txt;} -char * OP_LDR_P_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_P_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { sprintf(txt, "LDR%s %s, [%s, #%X]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_LDR_M_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_M_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { sprintf(txt, "LDR%s %s, [%s, -#%X]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_LDR_P_LSL_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_P_LSL_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(LDR, "", "", "]!"); return txt;} -char * OP_LDR_M_LSL_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_M_LSL_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(LDR, "-", "", "]!"); return txt;} -char * OP_LDR_P_LSR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_P_LSR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDR, LSR, "", "", "]!"); return txt;} -char * OP_LDR_M_LSR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_M_LSR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDR, LSR, "-", "", "]!"); return txt;} -char * OP_LDR_P_ASR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_P_ASR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDR, ASR, "", "", "]!"); return txt;} -char * OP_LDR_M_ASR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_M_ASR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDR, ASR, "-", "", "]!"); return txt;} -char * OP_LDR_P_ROR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_P_ROR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(LDR, "", "", "]!"); return txt;} -char * OP_LDR_M_ROR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_M_ROR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(LDR, "-", "", "]!"); return txt;} -char * OP_LDR_P_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_P_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { sprintf(txt, "LDR%s %s, [%s], #%X!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_LDR_P_IMM_OFF_POSTIND2(u32 adr, u32 i, char * txt) +static char * OP_LDR_P_IMM_OFF_POSTIND2(u32 adr, u32 i, char * txt) { sprintf(txt, "LDR%s %s, [%s], #%X!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_LDR_M_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_M_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { sprintf(txt, "LDR%s %s, [%s], -#%X!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_LDR_P_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_P_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(LDR, "", "]", ""); return txt;} -char * OP_LDR_M_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_M_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(LDR, "-", "]", ""); return txt;} -char * OP_LDR_P_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_P_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDR, LSR, "", "]", ""); return txt;} -char * OP_LDR_M_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_M_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDR, LSR, "-", "]", ""); return txt;} -char * OP_LDR_P_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_P_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDR, ASR, "", "]", ""); return txt;} -char * OP_LDR_M_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_M_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDR, ASR, "-", "]", ""); return txt;} -char * OP_LDR_P_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_P_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(LDR, "", "]", ""); return txt;} -char * OP_LDR_M_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDR_M_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(LDR, "-", "]", ""); return txt;} //-----------------LDRB------------------------------------------- -char * OP_LDRB_P_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRB_P_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRB%s %s, [%s, #%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_LDRB_M_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRB_M_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRB%s %s, [%s, -#%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_LDRB_P_LSL_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRB_P_LSL_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(LDRB, "", "", "]"); return txt;} -char * OP_LDRB_M_LSL_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRB_M_LSL_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(LDRB, "-", "", "]"); return txt;} -char * OP_LDRB_P_LSR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRB_P_LSR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDRB, LSR, "", "", "]"); return txt;} -char * OP_LDRB_M_LSR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRB_M_LSR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDRB, LSR, "M", "", "]"); return txt;} -char * OP_LDRB_P_ASR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRB_P_ASR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDRB, ASR, "", "", "]"); return txt;} -char * OP_LDRB_M_ASR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRB_M_ASR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDRB, ASR, "-", "", "]"); return txt;} -char * OP_LDRB_P_ROR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRB_P_ROR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(LDRB, "", "", "]"); return txt;} -char * OP_LDRB_M_ROR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRB_M_ROR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(LDRB, "-", "", "]"); return txt;} -char * OP_LDRB_P_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_P_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRB%s %s, [%s, #%X]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_LDRB_M_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_M_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRB%s %s, [%s, -#%X]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_LDRB_P_LSL_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_P_LSL_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(LDRB, "", "", "]!"); return txt;} -char * OP_LDRB_M_LSL_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_M_LSL_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(LDRB, "-", "", "]!"); return txt;} -char * OP_LDRB_P_LSR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_P_LSR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDRB, LSR, "", "", "]!"); return txt;} -char * OP_LDRB_M_LSR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_M_LSR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDRB, LSR, "-", "", "]!"); return txt;} -char * OP_LDRB_P_ASR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_P_ASR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDRB, ASR, "", "", "]!"); return txt;} -char * OP_LDRB_M_ASR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_M_ASR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDRB, ASR, "-", "", "]!"); return txt;} -char * OP_LDRB_P_ROR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_P_ROR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(LDRB, "", "", "]!"); return txt;} -char * OP_LDRB_M_ROR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_M_ROR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(LDRB, "-", "", "]!"); return txt;} -char * OP_LDRB_P_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_P_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRB%s %s, [%s], #%X!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_LDRB_M_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_M_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRB%s %s, [%s], -#%X!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_LDRB_P_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_P_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(LDRB, "", "]", ""); return txt;} -char * OP_LDRB_M_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_M_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(LDRB, "-", "]", ""); return txt;} -char * OP_LDRB_P_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_P_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDRB, LSR, "", "]", ""); return txt;} -char * OP_LDRB_M_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_M_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDRB, LSR, "-", "]", ""); return txt;} -char * OP_LDRB_P_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_P_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDRB, ASR, "", "]", ""); return txt;} -char * OP_LDRB_M_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_M_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDRB, ASR, "-", "]", ""); return txt;} -char * OP_LDRB_P_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_P_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(LDRB, "", "]", ""); return txt;} -char * OP_LDRB_M_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRB_M_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(LDRB, "-", "]", ""); return txt;} //----------------------STR-------------------------------- -char * OP_STR_P_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STR_P_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STR%s %s, [%s, #%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_STR_M_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STR_M_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STR%s %s, [%s, -#%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_STR_P_LSL_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STR_P_LSL_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(STR, "", "", "]"); return txt;} -char * OP_STR_M_LSL_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STR_M_LSL_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(STR, "-", "", "]"); return txt;} -char * OP_STR_P_LSR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STR_P_LSR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STR, LSR, "", "", "]"); return txt;} -char * OP_STR_M_LSR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STR_M_LSR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STR, LSR, "M", "", "]"); return txt;} -char * OP_STR_P_ASR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STR_P_ASR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STR, ASR, "", "", "]"); return txt;} -char * OP_STR_M_ASR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STR_M_ASR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STR, ASR, "-", "", "]"); return txt;} -char * OP_STR_P_ROR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STR_P_ROR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(STR, "", "", "]"); return txt;} -char * OP_STR_M_ROR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STR_M_ROR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(STR, "-", "", "]"); return txt;} -char * OP_STR_P_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STR_P_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { sprintf(txt, "STR%s %s, [%s, #%X]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_STR_M_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STR_M_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { sprintf(txt, "STR%s %s, [%s, -#%X]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_STR_P_LSL_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STR_P_LSL_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(STR, "", "", "]!"); return txt;} -char * OP_STR_M_LSL_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STR_M_LSL_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(STR, "-", "", "]!"); return txt;} -char * OP_STR_P_LSR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STR_P_LSR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STR, LSR, "", "", "]!"); return txt;} -char * OP_STR_M_LSR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STR_M_LSR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STR, LSR, "-", "", "]!"); return txt;} -char * OP_STR_P_ASR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STR_P_ASR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STR, ASR, "", "", "]!"); return txt;} -char * OP_STR_M_ASR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STR_M_ASR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STR, ASR, "-", "", "]!"); return txt;} -char * OP_STR_P_ROR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STR_P_ROR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(STR, "", "", "]!"); return txt;} -char * OP_STR_M_ROR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STR_M_ROR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(STR, "-", "", "]!"); return txt;} -char * OP_STR_P_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STR_P_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { sprintf(txt, "STR%s %s, [%s], #%X!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_STR_M_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STR_M_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { sprintf(txt, "STR%s %s, [%s], -#%X!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_STR_P_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STR_P_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(STR, "", "]", ""); return txt;} -char * OP_STR_M_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STR_M_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(STR, "-", "]", ""); return txt;} -char * OP_STR_P_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STR_P_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STR, LSR, "", "]", ""); return txt;} -char * OP_STR_M_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STR_M_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STR, LSR, "-", "]", ""); return txt;} -char * OP_STR_P_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STR_P_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STR, ASR, "", "]", ""); return txt;} -char * OP_STR_M_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STR_M_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STR, ASR, "-", "]", ""); return txt;} -char * OP_STR_P_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STR_P_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(STR, "", "]", ""); return txt;} -char * OP_STR_M_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STR_M_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(STR, "-", "]", ""); return txt;} //-----------------------STRB------------------------------------- -char * OP_STRB_P_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRB_P_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STRB%s %s, [%s, #%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_STRB_M_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRB_M_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STRB%s %s, [%s, -#%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_STRB_P_LSL_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRB_P_LSL_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(STRB, "", "", "]"); return txt;} -char * OP_STRB_M_LSL_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRB_M_LSL_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(STRB, "-", "", "]"); return txt;} -char * OP_STRB_P_LSR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRB_P_LSR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STRB, LSR, "", "", "]"); return txt;} -char * OP_STRB_M_LSR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRB_M_LSR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STRB, LSR, "M", "", "]"); return txt;} -char * OP_STRB_P_ASR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRB_P_ASR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STRB, ASR, "", "", "]"); return txt;} -char * OP_STRB_M_ASR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRB_M_ASR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STRB, ASR, "-", "", "]"); return txt;} -char * OP_STRB_P_ROR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRB_P_ROR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(STRB, "", "", "]"); return txt;} -char * OP_STRB_M_ROR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRB_M_ROR_IMM_OFF(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(STRB, "-", "", "]"); return txt;} -char * OP_STRB_P_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_P_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { sprintf(txt, "STRB%s %s, [%s, #%X]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_STRB_M_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_M_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { sprintf(txt, "STRB%s %s, [%s, -#%X]!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_STRB_P_LSL_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_P_LSL_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(STRB, "", "", "]!"); return txt;} -char * OP_STRB_M_LSL_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_M_LSL_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(STRB, "-", "", "]!"); return txt;} -char * OP_STRB_P_LSR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_P_LSR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STRB, LSR, "", "", "]!"); return txt;} -char * OP_STRB_M_LSR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_M_LSR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STRB, LSR, "-", "", "]!"); return txt;} -char * OP_STRB_P_ASR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_P_ASR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STRB, ASR, "", "", "]!"); return txt;} -char * OP_STRB_M_ASR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_M_ASR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STRB, ASR, "-", "", "]!"); return txt;} -char * OP_STRB_P_ROR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_P_ROR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(STRB, "", "", "]!"); return txt;} -char * OP_STRB_M_ROR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_M_ROR_IMM_OFF_PREIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(STRB, "-", "", "]!"); return txt;} -char * OP_STRB_P_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_P_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { sprintf(txt, "STRB%s %s, [%s], #%X!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_STRB_M_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_M_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { sprintf(txt, "STRB%s %s, [%s], -#%X!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_STRB_P_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_P_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(STRB, "", "]", ""); return txt;} -char * OP_STRB_M_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_M_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(STRB, "-", "]", ""); return txt;} -char * OP_STRB_P_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_P_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STRB, LSR, "", "]", ""); return txt;} -char * OP_STRB_M_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_M_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STRB, LSR, "-", "]", ""); return txt;} -char * OP_STRB_P_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_P_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STRB, ASR, "", "]", ""); return txt;} -char * OP_STRB_M_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_M_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STRB, ASR, "-", "]", ""); return txt;} -char * OP_STRB_P_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_P_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(STRB, "", "]", ""); return txt;} -char * OP_STRB_M_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRB_M_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(STRB, "-", "]", ""); return txt;} //-----------------------LDRBT------------------------------------- -char * OP_LDRBT_P_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRBT_P_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRBT%s %s, [%s], #%X!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_LDRBT_M_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRBT_M_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRBT%s %s, [%s], -#%X!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_LDRBT_P_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRBT_P_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(LDRBT, "", "]", ""); return txt;} -char * OP_LDRBT_M_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRBT_M_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(LDRBT, "-", "]", ""); return txt;} -char * OP_LDRBT_P_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRBT_P_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDRBT, LSR, "", "]", ""); return txt;} -char * OP_LDRBT_M_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRBT_M_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDRBT, LSR, "-", "]", ""); return txt;} -char * OP_LDRBT_P_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRBT_P_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDRBT, ASR, "", "]", ""); return txt;} -char * OP_LDRBT_M_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRBT_M_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(LDRBT, ASR, "-", "]", ""); return txt;} -char * OP_LDRBT_P_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRBT_P_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(LDRBT, "", "]", ""); return txt;} -char * OP_LDRBT_M_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDRBT_M_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(LDRBT, "-", "]", ""); return txt;} //----------------------STRBT---------------------------- -char * OP_STRBT_P_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRBT_P_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { sprintf(txt, "STRBT%s %s, [%s], #%X!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_STRBT_M_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRBT_M_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { sprintf(txt, "STRBT%s %s, [%s], -#%X!", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0xFF)); return txt;} -char * OP_STRBT_P_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRBT_P_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(STRBT, "", "]", ""); return txt;} -char * OP_STRBT_M_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRBT_M_LSL_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_LSL_IMM(STRBT, "-", "]", ""); return txt;} -char * OP_STRBT_P_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRBT_P_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STRBT, LSR, "", "]", ""); return txt;} -char * OP_STRBT_M_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRBT_M_LSR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STRBT, LSR, "-", "]", ""); return txt;} -char * OP_STRBT_P_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRBT_P_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STRBT, ASR, "", "]", ""); return txt;} -char * OP_STRBT_M_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRBT_M_ASR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_IMM_SHIFT(STRBT, ASR, "-", "]", ""); return txt;} -char * OP_STRBT_P_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRBT_P_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(STRBT, "", "]", ""); return txt;} -char * OP_STRBT_M_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STRBT_M_ROR_IMM_OFF_POSTIND(u32 adr, u32 i, char * txt) { LDRSTR_ROR_IMM(STRBT, "-", "]", ""); return txt;} //---------------------LDM----------------------------- -char * OP_LDMIA(u32 adr, u32 i, char * txt) +static char * OP_LDMIA(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "LDMIA%s %s, {%s}", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_LDMIB(u32 adr, u32 i, char * txt) +static char * OP_LDMIB(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "LDMIB%s %s, {%s}", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_LDMDA(u32 adr, u32 i, char * txt) +static char * OP_LDMDA(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "LDMDA%s %s, {%s}", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_LDMDB(u32 adr, u32 i, char * txt) +static char * OP_LDMDB(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "LDMDB%s %s, {%s}", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_LDMIA_W(u32 adr, u32 i, char * txt) +static char * OP_LDMIA_W(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "LDMIA%s %s!, {%s}", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_LDMIB_W(u32 adr, u32 i, char * txt) +static char * OP_LDMIB_W(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "LDMIB%s %s!, {%s}", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_LDMDA_W(u32 adr, u32 i, char * txt) +static char * OP_LDMDA_W(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "LDMDA%s %s!, {%s}", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_LDMDB_W(u32 adr, u32 i, char * txt) +static char * OP_LDMDB_W(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "LDMDB%s %s!, {%s}", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_LDMIA2(u32 adr, u32 i, char * txt) +static char * OP_LDMIA2(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "LDMIA%s %s, {%s}^", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_LDMIB2(u32 adr, u32 i, char * txt) +static char * OP_LDMIB2(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "LDMIB%s %s, {%s}^", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_LDMDA2(u32 adr, u32 i, char * txt) +static char * OP_LDMDA2(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "LDMDA%s %s, {%s}^", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_LDMDB2(u32 adr, u32 i, char * txt) +static char * OP_LDMDB2(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "LDMDB%s %s, {%s}^", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_LDMIA2_W(u32 adr, u32 i, char * txt) +static char * OP_LDMIA2_W(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "LDMIA%s %s!, {%s}^", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); if(BIT15(i)==0) sprintf(txt, "%s ?????", txt); return txt;} -char * OP_LDMIB2_W(u32 adr, u32 i, char * txt) +static char * OP_LDMIB2_W(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "LDMIB%s %s!, {%s}^", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); if(BIT15(i)==0) sprintf(txt, "%s ?????", txt); return txt;} -char * OP_LDMDA2_W(u32 adr, u32 i, char * txt) +static char * OP_LDMDA2_W(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "LDMDA%s %s!, {%s}^", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); if(BIT15(i)==0) sprintf(txt, "%s ?????", txt); return txt;} -char * OP_LDMDB2_W(u32 adr, u32 i, char * txt) +static char * OP_LDMDB2_W(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "LDMDB%s %s!, {%s}^", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); @@ -2936,98 +2936,98 @@ return txt;} //------------------------------STM---------------------------------- -char * OP_STMIA(u32 adr, u32 i, char * txt) +static char * OP_STMIA(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "STMIA%s %s, {%s}", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_STMIB(u32 adr, u32 i, char * txt) +static char * OP_STMIB(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "STMIB%s %s, {%s}", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_STMDA(u32 adr, u32 i, char * txt) +static char * OP_STMDA(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "STMDA%s %s, {%s}", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_STMDB(u32 adr, u32 i, char * txt) +static char * OP_STMDB(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "STMDB%s %s, {%s}", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_STMIA_W(u32 adr, u32 i, char * txt) +static char * OP_STMIA_W(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "STMIA%s %s!, {%s}", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_STMIB_W(u32 adr, u32 i, char * txt) +static char * OP_STMIB_W(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "STMIB%s %s!, {%s}", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_STMDA_W(u32 adr, u32 i, char * txt) +static char * OP_STMDA_W(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "STMDA%s %s!, {%s}", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_STMDB_W(u32 adr, u32 i, char * txt) +static char * OP_STMDB_W(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "STMDB%s %s!, {%s}", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_STMIA2(u32 adr, u32 i, char * txt) +static char * OP_STMIA2(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "STMIA%s %s, {%s}^", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_STMIB2(u32 adr, u32 i, char * txt) +static char * OP_STMIB2(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "STMIB%s %s, {%s}^", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_STMDA2(u32 adr, u32 i, char * txt) +static char * OP_STMDA2(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "STMDA%s %s, {%s}^", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_STMDB2(u32 adr, u32 i, char * txt) +static char * OP_STMDB2(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "STMDB%s %s, {%s}^", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_STMIA2_W(u32 adr, u32 i, char * txt) +static char * OP_STMIA2_W(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "STMIA%s %s!, {%s}^ ?????", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_STMIB2_W(u32 adr, u32 i, char * txt) +static char * OP_STMIB2_W(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "STMIB%s %s!, {%s}^ ?????", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt;} -char * OP_STMDA2_W(u32 adr, u32 i, char * txt) +static char * OP_STMDA2_W(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "STMDA%s %s!, {%s}^ ?????", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); return txt; } -char * OP_STMDB2_W(u32 adr, u32 i, char * txt) +static char * OP_STMDB2_W(u32 adr, u32 i, char * txt) { RegList(16); sprintf(txt, "STMDB%s %s!, {%s}^ ?????", Condition[CONDITION(i)], Registre[REG_POS(i,16)], lreg); @@ -3036,7 +3036,7 @@ char * OP_STMDB2_W(u32 adr, u32 i, char * txt) //---------------------STC---------------------------------- -char * OP_STC_P_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STC_P_IMM_OFF(u32 adr, u32 i, char * txt) { if(CONDITION(i)==0xF) { @@ -3047,7 +3047,7 @@ char * OP_STC_P_IMM_OFF(u32 adr, u32 i, char * txt) return txt; } -char * OP_STC_M_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STC_M_IMM_OFF(u32 adr, u32 i, char * txt) { if(CONDITION(i)==0xF) { @@ -3058,7 +3058,7 @@ char * OP_STC_M_IMM_OFF(u32 adr, u32 i, char * txt) return txt; } -char * OP_STC_P_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STC_P_PREIND(u32 adr, u32 i, char * txt) { if(CONDITION(i)==0xF) { @@ -3069,7 +3069,7 @@ char * OP_STC_P_PREIND(u32 adr, u32 i, char * txt) return txt; } -char * OP_STC_M_PREIND(u32 adr, u32 i, char * txt) +static char * OP_STC_M_PREIND(u32 adr, u32 i, char * txt) { if(CONDITION(i)==0xF) { @@ -3080,7 +3080,7 @@ char * OP_STC_M_PREIND(u32 adr, u32 i, char * txt) return txt; } -char * OP_STC_P_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STC_P_POSTIND(u32 adr, u32 i, char * txt) { if(CONDITION(i)==0xF) { @@ -3091,7 +3091,7 @@ char * OP_STC_P_POSTIND(u32 adr, u32 i, char * txt) return txt; } -char * OP_STC_M_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_STC_M_POSTIND(u32 adr, u32 i, char * txt) { if(CONDITION(i)==0xF) { @@ -3102,7 +3102,7 @@ char * OP_STC_M_POSTIND(u32 adr, u32 i, char * txt) return txt; } -char * OP_STC_OPTION(u32 adr, u32 i, char * txt) +static char * OP_STC_OPTION(u32 adr, u32 i, char * txt) { if(CONDITION(i)==0xF) { @@ -3115,7 +3115,7 @@ char * OP_STC_OPTION(u32 adr, u32 i, char * txt) //---------------------LDC---------------------------------- -char * OP_LDC_P_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDC_P_IMM_OFF(u32 adr, u32 i, char * txt) { if(CONDITION(i)==0xF) { @@ -3126,7 +3126,7 @@ char * OP_LDC_P_IMM_OFF(u32 adr, u32 i, char * txt) return txt; } -char * OP_LDC_M_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDC_M_IMM_OFF(u32 adr, u32 i, char * txt) { if(CONDITION(i)==0xF) { @@ -3137,7 +3137,7 @@ char * OP_LDC_M_IMM_OFF(u32 adr, u32 i, char * txt) return txt; } -char * OP_LDC_P_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDC_P_PREIND(u32 adr, u32 i, char * txt) { if(CONDITION(i)==0xF) { @@ -3148,7 +3148,7 @@ char * OP_LDC_P_PREIND(u32 adr, u32 i, char * txt) return txt; } -char * OP_LDC_M_PREIND(u32 adr, u32 i, char * txt) +static char * OP_LDC_M_PREIND(u32 adr, u32 i, char * txt) { if(CONDITION(i)==0xF) { @@ -3159,7 +3159,7 @@ char * OP_LDC_M_PREIND(u32 adr, u32 i, char * txt) return txt; } -char * OP_LDC_P_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDC_P_POSTIND(u32 adr, u32 i, char * txt) { if(CONDITION(i)==0xF) { @@ -3170,7 +3170,7 @@ char * OP_LDC_P_POSTIND(u32 adr, u32 i, char * txt) return txt; } -char * OP_LDC_M_POSTIND(u32 adr, u32 i, char * txt) +static char * OP_LDC_M_POSTIND(u32 adr, u32 i, char * txt) { if(CONDITION(i)==0xF) { @@ -3181,7 +3181,7 @@ char * OP_LDC_M_POSTIND(u32 adr, u32 i, char * txt) return txt; } -char * OP_LDC_OPTION(u32 adr, u32 i, char * txt) +static char * OP_LDC_OPTION(u32 adr, u32 i, char * txt) { if(CONDITION(i)==0xF) { @@ -3194,7 +3194,7 @@ char * OP_LDC_OPTION(u32 adr, u32 i, char * txt) //----------------MCR----------------------- -char * OP_MCR(u32 adr, u32 i, char * txt) +static char * OP_MCR(u32 adr, u32 i, char * txt) { if(CONDITION(i)==0xF) { @@ -3207,7 +3207,7 @@ char * OP_MCR(u32 adr, u32 i, char * txt) //----------------MRC----------------------- -char * OP_MRC(u32 adr, u32 i, char * txt) +static char * OP_MRC(u32 adr, u32 i, char * txt) { if(CONDITION(i)==0xF) { @@ -3220,14 +3220,14 @@ char * OP_MRC(u32 adr, u32 i, char * txt) //--------------SWI-------------------------- -char * OP_SWI(u32 adr, u32 i, char * txt) +static char * OP_SWI(u32 adr, u32 i, char * txt) { sprintf(txt, "SWI%s %X",Condition[CONDITION(i)], (int)((i&0xFFFFFF)>>16)); return txt; } //----------------BKPT------------------------- -char * OP_BKPT(u32 adr, u32 i, char * txt) +static char * OP_BKPT(u32 adr, u32 i, char * txt) { sprintf(txt, "BKPT #%X",(int)(((i>>4)&0xFFF)|(i&0xF))); return txt; @@ -3246,406 +3246,406 @@ char * OP_CDP(u32 adr, u32 i, char * txt) //------------------------------------------------------------ #define REG_NUM(i, n) (((i)>>n)&0x7) -char * OP_UND_THUMB(u32 adr, u32 i, char * txt) +static char * OP_UND_THUMB(u32 adr, u32 i, char * txt) { sprintf(txt, "----"); return txt; } -char * OP_LSL_0(u32 adr, u32 i, char * txt) +static char * OP_LSL_0(u32 adr, u32 i, char * txt) { sprintf(txt, "LSL %s, %s, #0", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_LSL(u32 adr, u32 i, char * txt) +static char * OP_LSL(u32 adr, u32 i, char * txt) { sprintf(txt, "LSL %s, %s, #%X", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], (int)((i>>6) & 0x1F)); return txt; } -char * OP_LSR_0(u32 adr, u32 i, char * txt) +static char * OP_LSR_0(u32 adr, u32 i, char * txt) { sprintf(txt, "LSR %s, %s, #0", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_LSR(u32 adr, u32 i, char * txt) +static char * OP_LSR(u32 adr, u32 i, char * txt) { sprintf(txt, "LSR %s, %s, #%X", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], (int)((i>>6) & 0x1F)); return txt; } -char * OP_ASR_0(u32 adr, u32 i, char * txt) +static char * OP_ASR_0(u32 adr, u32 i, char * txt) { sprintf(txt, "ASR %s, %s, #0", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_ASR(u32 adr, u32 i, char * txt) +static char * OP_ASR(u32 adr, u32 i, char * txt) { sprintf(txt, "ASR %s, %s, #%X", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], (int)((i>>6) & 0x1F)); return txt; } -char * OP_ADD_REG(u32 adr, u32 i, char * txt) +static char * OP_ADD_REG(u32 adr, u32 i, char * txt) { sprintf(txt, "ADD %s, %s, %s", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], Registre[REG_NUM(i, 6)]); return txt; } -char * OP_SUB_REG(u32 adr, u32 i, char * txt) +static char * OP_SUB_REG(u32 adr, u32 i, char * txt) { sprintf(txt, "SUB %s, %s, %s", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], Registre[REG_NUM(i, 6)]); return txt; } -char * OP_ADD_IMM3(u32 adr, u32 i, char * txt) +static char * OP_ADD_IMM3(u32 adr, u32 i, char * txt) { sprintf(txt, "ADD %s, %s, #%X", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], (int)REG_NUM(i, 6)); return txt; } -char * OP_SUB_IMM3(u32 adr, u32 i, char * txt) +static char * OP_SUB_IMM3(u32 adr, u32 i, char * txt) { sprintf(txt, "SUB %s, %s, #%X", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], (int)REG_NUM(i, 6)); return txt; } -char * OP_MOV_IMM8(u32 adr, u32 i, char * txt) +static char * OP_MOV_IMM8(u32 adr, u32 i, char * txt) { sprintf(txt, "MOV %s, #%X", Registre[REG_NUM(i, 8)], (int)(i&0xFF)); return txt; } -char * OP_CMP_IMM8(u32 adr, u32 i, char * txt) +static char * OP_CMP_IMM8(u32 adr, u32 i, char * txt) { sprintf(txt, "CMP %s, #%X", Registre[REG_NUM(i, 8)], (int)(i&0xFF)); return txt; } -char * OP_ADD_IMM8(u32 adr, u32 i, char * txt) +static char * OP_ADD_IMM8(u32 adr, u32 i, char * txt) { sprintf(txt, "ADD %s, #%X", Registre[REG_NUM(i, 8)], (int)(i&0xFF)); return txt; } -char * OP_SUB_IMM8(u32 adr, u32 i, char * txt) +static char * OP_SUB_IMM8(u32 adr, u32 i, char * txt) { sprintf(txt, "SUB %s, #%X", Registre[REG_NUM(i, 8)], (int)(i&0xFF)); return txt; } -char * OP_AND(u32 adr, u32 i, char * txt) +static char * OP_AND(u32 adr, u32 i, char * txt) { sprintf(txt, "AND %s, %s", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_EOR(u32 adr, u32 i, char * txt) +static char * OP_EOR(u32 adr, u32 i, char * txt) { sprintf(txt, "EOR %s, %s", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_LSL_REG(u32 adr, u32 i, char * txt) +static char * OP_LSL_REG(u32 adr, u32 i, char * txt) { sprintf(txt, "LSL %s, %s", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_LSR_REG(u32 adr, u32 i, char * txt) +static char * OP_LSR_REG(u32 adr, u32 i, char * txt) { sprintf(txt, "LSR %s, %s", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_ASR_REG(u32 adr, u32 i, char * txt) +static char * OP_ASR_REG(u32 adr, u32 i, char * txt) { sprintf(txt, "ASR %s, %s", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_ADC_REG(u32 adr, u32 i, char * txt) +static char * OP_ADC_REG(u32 adr, u32 i, char * txt) { sprintf(txt, "ADC %s, %s", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_SBC_REG(u32 adr, u32 i, char * txt) +static char * OP_SBC_REG(u32 adr, u32 i, char * txt) { sprintf(txt, "SBC %s, %s", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_ROR_REG(u32 adr, u32 i, char * txt) +static char * OP_ROR_REG(u32 adr, u32 i, char * txt) { sprintf(txt, "ROR %s, %s", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_TST(u32 adr, u32 i, char * txt) +static char * OP_TST(u32 adr, u32 i, char * txt) { sprintf(txt, "TST %s, %s", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_NEG(u32 adr, u32 i, char * txt) +static char * OP_NEG(u32 adr, u32 i, char * txt) { sprintf(txt, "NEG %s, %s", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_CMP(u32 adr, u32 i, char * txt) +static char * OP_CMP(u32 adr, u32 i, char * txt) { sprintf(txt, "CMP %s, %s", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_CMN(u32 adr, u32 i, char * txt) +static char * OP_CMN(u32 adr, u32 i, char * txt) { sprintf(txt, "CMN %s, %s", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_ORR(u32 adr, u32 i, char * txt) +static char * OP_ORR(u32 adr, u32 i, char * txt) { sprintf(txt, "ORR %s, %s", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_MUL_REG(u32 adr, u32 i, char * txt) +static char * OP_MUL_REG(u32 adr, u32 i, char * txt) { sprintf(txt, "MUL %s, %s", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_BIC(u32 adr, u32 i, char * txt) +static char * OP_BIC(u32 adr, u32 i, char * txt) { sprintf(txt, "BIC %s, %s", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_MVN(u32 adr, u32 i, char * txt) +static char * OP_MVN(u32 adr, u32 i, char * txt) { sprintf(txt, "MVN %s, %s", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)]); return txt; } -char * OP_ADD_SPE(u32 adr, u32 i, char * txt) +static char * OP_ADD_SPE(u32 adr, u32 i, char * txt) { u8 Rd = (i&7) | ((i>>4)&8); sprintf(txt, "ADD %s, %s", Registre[Rd], Registre[REG_POS(i, 3)]); return txt; } -char * OP_CMP_SPE(u32 adr, u32 i, char * txt) +static char * OP_CMP_SPE(u32 adr, u32 i, char * txt) { u8 Rd = (i&7) | ((i>>4)&8); sprintf(txt, "CMP %s, %s", Registre[Rd], Registre[REG_POS(i, 3)]); return txt; } -char * OP_MOV_SPE(u32 adr, u32 i, char * txt) +static char * OP_MOV_SPE(u32 adr, u32 i, char * txt) { u8 Rd = (i&7) | ((i>>4)&8); sprintf(txt, "MOV %s, %s", Registre[Rd], Registre[REG_POS(i, 3)]); return txt; } -char * OP_BX_THUMB(u32 adr, u32 i, char * txt) +static char * OP_BX_THUMB(u32 adr, u32 i, char * txt) { sprintf(txt, "BX %s", Registre[REG_POS(i, 3)]); return txt; } -char * OP_BLX_THUMB(u32 adr, u32 i, char * txt) +static char * OP_BLX_THUMB(u32 adr, u32 i, char * txt) { sprintf(txt, "BLX %s", Registre[REG_POS(i, 3)]); return txt; } -char * OP_LDR_PCREL(u32 adr, u32 i, char * txt) +static char * OP_LDR_PCREL(u32 adr, u32 i, char * txt) { sprintf(txt, "LDR %s, [PC, #%X]", Registre[REG_NUM(i, 8)], (int)((i&0xFF)<<2)); return txt; } -char * OP_STR_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_STR_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STR %s, [%s, %s]", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], Registre[REG_NUM(i, 6)]); return txt; } -char * OP_STRH_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRH_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STRH %s, [%s, %s]", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], Registre[REG_NUM(i, 6)]); return txt; } -char * OP_STRB_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRB_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STRB %s, [%s, %s]", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], Registre[REG_NUM(i, 6)]); return txt; } -char * OP_LDRSB_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSB_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSB %s, [%s, %s]", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], Registre[REG_NUM(i, 6)]); return txt; } -char * OP_LDR_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDR_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDR %s, [%s, %s]", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], Registre[REG_NUM(i, 6)]); return txt; } -char * OP_LDRH_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRH_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRH %s, [%s, %s]", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], Registre[REG_NUM(i, 6)]); return txt; } -char * OP_LDRB_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRB_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRB %s, [%s, %s]", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], Registre[REG_NUM(i, 6)]); return txt; } -char * OP_LDRSH_REG_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRSH_REG_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRSH %s, [%s, %s]", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], Registre[REG_NUM(i, 6)]); return txt; } -char * OP_STR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STR_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STR %s, [%s, #%X]", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], (int)((i>>4)&0x7C)); return txt; } -char * OP_LDR_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDR_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDR %s, [%s, #%X]", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], (int)((i>>4)&0x7C)); return txt; } -char * OP_STRB_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRB_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STRB %s, [%s, #%X]", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], (int)((i>>6)&0x1F)); return txt; } -char * OP_LDRB_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRB_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRB %s, [%s, #%X]", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], (int)((i>>6)&0x1F)); return txt; } -char * OP_STRH_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_STRH_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "STRH %s, [%s, #%X]", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], (int)((i>>5)&0x3E)); return txt; } -char * OP_LDRH_IMM_OFF(u32 adr, u32 i, char * txt) +static char * OP_LDRH_IMM_OFF(u32 adr, u32 i, char * txt) { sprintf(txt, "LDRH %s, [%s, #%X]", Registre[REG_NUM(i, 0)], Registre[REG_NUM(i, 3)], (int)((i>>5)&0x3E)); return txt; } -char * OP_STR_SPREL(u32 adr, u32 i, char * txt) +static char * OP_STR_SPREL(u32 adr, u32 i, char * txt) { sprintf(txt, "STR %s, [SP, #%X]", Registre[REG_NUM(i, 8)], (int)((i&0xFF)<<2)); return txt; } -char * OP_LDR_SPREL(u32 adr, u32 i, char * txt) +static char * OP_LDR_SPREL(u32 adr, u32 i, char * txt) { sprintf(txt, "LDR %s, [SP, #%X]", Registre[REG_NUM(i, 8)], (int)((i&0xFF)<<2)); return txt; } -char * OP_ADD_2PC(u32 adr, u32 i, char * txt) +static char * OP_ADD_2PC(u32 adr, u32 i, char * txt) { sprintf(txt, "ADD %s, PC, #%X", Registre[REG_NUM(i, 8)], (int)((i&0xFF)<<2)); return txt; } -char * OP_ADD_2SP(u32 adr, u32 i, char * txt) +static char * OP_ADD_2SP(u32 adr, u32 i, char * txt) { sprintf(txt, "ADD %s, SP, #%X", Registre[REG_NUM(i, 8)], (int)((i&0xFF)<<2)); return txt; } -char * OP_ADJUST_P_SP(u32 adr, u32 i, char * txt) +static char * OP_ADJUST_P_SP(u32 adr, u32 i, char * txt) { sprintf(txt, "ADD SP, #%X", (int)((i&0x7F)<<2)); return txt; } -char * OP_ADJUST_M_SP(u32 adr, u32 i, char * txt) +static char * OP_ADJUST_M_SP(u32 adr, u32 i, char * txt) { sprintf(txt, "SUB SP, #%X", (int)((i&0x7F)<<2)); return txt; } -char * OP_PUSH(u32 adr, u32 i, char * txt) +static char * OP_PUSH(u32 adr, u32 i, char * txt) { RegList(8); sprintf(txt, "PUSH {%s}", lreg); return txt; } -char * OP_PUSH_LR(u32 adr, u32 i, char * txt) +static char * OP_PUSH_LR(u32 adr, u32 i, char * txt) { RegList(8); sprintf(txt, "PUSH {%s, LR}", lreg); return txt; } -char * OP_POP(u32 adr, u32 i, char * txt) +static char * OP_POP(u32 adr, u32 i, char * txt) { RegList(8); sprintf(txt, "POP {%s}", lreg); return txt; } -char * OP_POP_PC(u32 adr, u32 i, char * txt) +static char * OP_POP_PC(u32 adr, u32 i, char * txt) { RegList(8); sprintf(txt, "POP {%s, PC}", lreg); return txt; } -char * OP_BKPT_THUMB(u32 adr, u32 i, char * txt) +static char * OP_BKPT_THUMB(u32 adr, u32 i, char * txt) { sprintf(txt, "BKPT"); return txt; } -char * OP_STMIA_THUMB(u32 adr, u32 i, char * txt) +static char * OP_STMIA_THUMB(u32 adr, u32 i, char * txt) { RegList(8); sprintf(txt, "STMIA %s!, {%s}", Registre[REG_NUM(i, 8)], lreg); return txt; } -char * OP_LDMIA_THUMB(u32 adr, u32 i, char * txt) +static char * OP_LDMIA_THUMB(u32 adr, u32 i, char * txt) { RegList(8); sprintf(txt, "LDMIA %s!, {%s}", Registre[REG_NUM(i, 8)], lreg); return txt; } -char * OP_B_COND(u32 adr, u32 i, char * txt) +static char * OP_B_COND(u32 adr, u32 i, char * txt) { sprintf(txt, "B%s #%X", Condition[(i>>8)&0xF], (int)(adr+(((signed long)((signed char)(i&0xFF)))<<1)+4)); return txt; } -char * OP_SWI_THUMB(u32 adr, u32 i, char * txt) +static char * OP_SWI_THUMB(u32 adr, u32 i, char * txt) { sprintf(txt, "SWI #%X", (int)(i & 0xFF)); return txt; @@ -3653,7 +3653,7 @@ char * OP_SWI_THUMB(u32 adr, u32 i, char * txt) #define SIGNEEXT_IMM11(i) (((i)&0x7FF) | (BIT10(i) * 0xFFFFF800)) -char * OP_B_UNCOND(u32 adr, u32 i, char * txt) +static char * OP_B_UNCOND(u32 adr, u32 i, char * txt) { sprintf(txt, "B #%X", (int)(adr+(SIGNEEXT_IMM11(i)<<1)+4)); return txt; @@ -3661,13 +3661,13 @@ char * OP_B_UNCOND(u32 adr, u32 i, char * txt) u32 part = 0; -char * OP_BLX(u32 adr, u32 i, char * txt) +static char * OP_BLX(u32 adr, u32 i, char * txt) { sprintf(txt, "BLX #%X", (int)(part + ((i&0x7FF)<<1))&0xFFFFFFFC); return txt; } -char * OP_BL_10(u32 adr, u32 i, char * txt) +static char * OP_BL_10(u32 adr, u32 i, char * txt) { part = adr+4 + (SIGNEEXT_IMM11(i)<<12); sprintf(txt, "CALCUL LA PARTIE HAUTE DE L'ADRESSE"); @@ -3675,7 +3675,7 @@ char * OP_BL_10(u32 adr, u32 i, char * txt) } -char * OP_BL_THUMB(u32 adr, u32 i, char * txt) +static char * OP_BL_THUMB(u32 adr, u32 i, char * txt) { sprintf(txt, "BL #%X", (int)(part + ((i&0x7FF)<<1))&0xFFFFFFFC); return txt; diff --git a/desmume/src/arm_instructions.c b/desmume/src/arm_instructions.c index eb6683332..4b3fa4452 100644 --- a/desmume/src/arm_instructions.c +++ b/desmume/src/arm_instructions.c @@ -222,7 +222,7 @@ s8 OFlag; extern BOOL execute; -u32 FASTCALL OP_UND(armcpu_t *cpu) +static u32 FASTCALL OP_UND(armcpu_t *cpu) { u32 i = cpu->instruction; LOG("Undefined instruction: %08X\n", i); @@ -257,126 +257,126 @@ u32 FASTCALL OP_UND(armcpu_t *cpu) cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ return a; -u32 FASTCALL OP_AND_LSL_IMM(register armcpu_t *cpu) +static u32 FASTCALL OP_AND_LSL_IMM(register armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; OP_AND(1, 3); } -u32 FASTCALL OP_AND_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_AND_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_REG; OP_AND(2, 4); } -u32 FASTCALL OP_AND_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_AND_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; OP_AND(1, 3); } -u32 FASTCALL OP_AND_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_AND_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_REG; OP_AND(2, 4); } -u32 FASTCALL OP_AND_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_AND_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; OP_AND(1, 3); } -u32 FASTCALL OP_AND_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_AND_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_REG; OP_AND(2, 4); } -u32 FASTCALL OP_AND_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_AND_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; OP_AND(1, 3); } -u32 FASTCALL OP_AND_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_AND_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_REG; OP_AND(2, 4); } -u32 FASTCALL OP_AND_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_AND_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; IMM_VALUE; OP_AND(1, 3); } -u32 FASTCALL OP_AND_S_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_AND_S_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSL_IMM; OP_ANDS(2, 4); } -u32 FASTCALL OP_AND_S_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_AND_S_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSL_REG; OP_ANDS(3, 5); } -u32 FASTCALL OP_AND_S_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_AND_S_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSR_IMM; OP_ANDS(2, 4); } -u32 FASTCALL OP_AND_S_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_AND_S_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSR_REG; OP_ANDS(3, 5); } -u32 FASTCALL OP_AND_S_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_AND_S_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_ASR_IMM; OP_ANDS(2, 4); } -u32 FASTCALL OP_AND_S_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_AND_S_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_ASR_REG; OP_ANDS(3, 5); } -u32 FASTCALL OP_AND_S_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_AND_S_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_ROR_IMM; OP_ANDS(2, 4); } -u32 FASTCALL OP_AND_S_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_AND_S_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_ROR_REG; OP_ANDS(3, 5); } -u32 FASTCALL OP_AND_S_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_AND_S_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; S_IMM_VALUE; @@ -408,126 +408,126 @@ u32 FASTCALL OP_AND_S_IMM_VAL(armcpu_t *cpu) cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ return a; -u32 FASTCALL OP_EOR_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_EOR_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; OP_EOR(1, 3); } -u32 FASTCALL OP_EOR_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_EOR_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_REG; OP_EOR(2, 4); } -u32 FASTCALL OP_EOR_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_EOR_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; OP_EOR(1, 3); } -u32 FASTCALL OP_EOR_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_EOR_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_REG; OP_EOR(2, 4); } -u32 FASTCALL OP_EOR_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_EOR_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; OP_EOR(1, 3); } -u32 FASTCALL OP_EOR_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_EOR_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_REG; OP_EOR(2, 4); } -u32 FASTCALL OP_EOR_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_EOR_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; OP_EOR(1, 3); } -u32 FASTCALL OP_EOR_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_EOR_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_REG; OP_EOR(2, 4); } -u32 FASTCALL OP_EOR_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_EOR_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; IMM_VALUE; OP_EOR(1, 3); } -u32 FASTCALL OP_EOR_S_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_EOR_S_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSL_IMM; OP_EORS(2, 4); } -u32 FASTCALL OP_EOR_S_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_EOR_S_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSL_REG; OP_EORS(3, 5); } -u32 FASTCALL OP_EOR_S_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_EOR_S_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSR_IMM; OP_EORS(2, 4); } -u32 FASTCALL OP_EOR_S_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_EOR_S_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSR_REG; OP_EORS(3, 5); } -u32 FASTCALL OP_EOR_S_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_EOR_S_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_ASR_IMM; OP_EORS(2, 4); } -u32 FASTCALL OP_EOR_S_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_EOR_S_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_ASR_REG; OP_EORS(3, 5); } -u32 FASTCALL OP_EOR_S_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_EOR_S_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_ROR_IMM; OP_EORS(2, 4); } -u32 FASTCALL OP_EOR_S_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_EOR_S_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_ROR_REG; OP_EORS(3, 5); } -u32 FASTCALL OP_EOR_S_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_EOR_S_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; S_IMM_VALUE; @@ -560,70 +560,70 @@ u32 FASTCALL OP_EOR_S_IMM_VAL(armcpu_t *cpu) cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\ return a; -u32 FASTCALL OP_SUB_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; OP_SUB(1, 3); } -u32 FASTCALL OP_SUB_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_REG; OP_SUB(2, 4); } -u32 FASTCALL OP_SUB_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; OP_SUB(1, 3); } -u32 FASTCALL OP_SUB_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_REG; OP_SUB(2, 4); } -u32 FASTCALL OP_SUB_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; OP_SUB(1, 3); } -u32 FASTCALL OP_SUB_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_REG; OP_SUB(2, 4); } -u32 FASTCALL OP_SUB_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; OP_SUB(1, 3); } -u32 FASTCALL OP_SUB_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_REG; OP_SUB(2, 4); } -u32 FASTCALL OP_SUB_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; IMM_VALUE; OP_SUB(1, 3); } -u32 FASTCALL OP_SUB_S_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_S_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -631,7 +631,7 @@ u32 FASTCALL OP_SUB_S_LSL_IMM(armcpu_t *cpu) OPSUBS(2, 4); } -u32 FASTCALL OP_SUB_S_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_S_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -639,7 +639,7 @@ u32 FASTCALL OP_SUB_S_LSL_REG(armcpu_t *cpu) OPSUBS(3, 5); } -u32 FASTCALL OP_SUB_S_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_S_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -647,7 +647,7 @@ u32 FASTCALL OP_SUB_S_LSR_IMM(armcpu_t *cpu) OPSUBS(2, 4); } -u32 FASTCALL OP_SUB_S_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_S_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -655,7 +655,7 @@ u32 FASTCALL OP_SUB_S_LSR_REG(armcpu_t *cpu) OPSUBS(3, 5); } -u32 FASTCALL OP_SUB_S_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_S_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -663,7 +663,7 @@ u32 FASTCALL OP_SUB_S_ASR_IMM(armcpu_t *cpu) OPSUBS(2, 4); } -u32 FASTCALL OP_SUB_S_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_S_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -671,7 +671,7 @@ u32 FASTCALL OP_SUB_S_ASR_REG(armcpu_t *cpu) OPSUBS(3, 5); } -u32 FASTCALL OP_SUB_S_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_S_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -679,7 +679,7 @@ u32 FASTCALL OP_SUB_S_ROR_IMM(armcpu_t *cpu) OPSUBS(2, 4); } -u32 FASTCALL OP_SUB_S_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_S_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -687,7 +687,7 @@ u32 FASTCALL OP_SUB_S_ROR_REG(armcpu_t *cpu) OPSUBS(3, 5); } -u32 FASTCALL OP_SUB_S_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_S_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -721,70 +721,70 @@ u32 FASTCALL OP_SUB_S_IMM_VAL(armcpu_t *cpu) cpu->CPSR.bits.V = SIGNED_UNDERFLOW(shift_op, v, cpu->R[REG_POS(i,12)]);\ return a; -u32 FASTCALL OP_RSB_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_RSB_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; OP_RSB(1, 3); } -u32 FASTCALL OP_RSB_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_RSB_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_REG; OP_RSB(2, 4); } -u32 FASTCALL OP_RSB_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_RSB_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; OP_RSB(1, 3); } -u32 FASTCALL OP_RSB_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_RSB_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_REG; OP_RSB(2, 4); } -u32 FASTCALL OP_RSB_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_RSB_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; OP_RSB(1, 3); } -u32 FASTCALL OP_RSB_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_RSB_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_REG; OP_RSB(2, 4); } -u32 FASTCALL OP_RSB_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_RSB_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; OP_RSB(1, 3); } -u32 FASTCALL OP_RSB_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_RSB_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_REG; OP_RSB(2, 4); } -u32 FASTCALL OP_RSB_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_RSB_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; IMM_VALUE; OP_RSB(1, 3); } -u32 FASTCALL OP_RSB_S_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_RSB_S_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -792,7 +792,7 @@ u32 FASTCALL OP_RSB_S_LSL_IMM(armcpu_t *cpu) OP_RSBS(2, 4); } -u32 FASTCALL OP_RSB_S_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_RSB_S_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -800,7 +800,7 @@ u32 FASTCALL OP_RSB_S_LSL_REG(armcpu_t *cpu) OP_RSBS(3, 5); } -u32 FASTCALL OP_RSB_S_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_RSB_S_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -808,7 +808,7 @@ u32 FASTCALL OP_RSB_S_LSR_IMM(armcpu_t *cpu) OP_RSBS(2, 4); } -u32 FASTCALL OP_RSB_S_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_RSB_S_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -816,7 +816,7 @@ u32 FASTCALL OP_RSB_S_LSR_REG(armcpu_t *cpu) OP_RSBS(3, 5); } -u32 FASTCALL OP_RSB_S_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_RSB_S_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -824,7 +824,7 @@ u32 FASTCALL OP_RSB_S_ASR_IMM(armcpu_t *cpu) OP_RSBS(2, 4); } -u32 FASTCALL OP_RSB_S_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_RSB_S_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -832,7 +832,7 @@ u32 FASTCALL OP_RSB_S_ASR_REG(armcpu_t *cpu) OP_RSBS(3, 5); } -u32 FASTCALL OP_RSB_S_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_RSB_S_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -840,7 +840,7 @@ u32 FASTCALL OP_RSB_S_ROR_IMM(armcpu_t *cpu) OP_RSBS(2, 4); } -u32 FASTCALL OP_RSB_S_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_RSB_S_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -848,7 +848,7 @@ u32 FASTCALL OP_RSB_S_ROR_REG(armcpu_t *cpu) OP_RSBS(3, 5); } -u32 FASTCALL OP_RSB_S_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_RSB_S_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -866,63 +866,63 @@ u32 FASTCALL OP_RSB_S_IMM_VAL(armcpu_t *cpu) }\ return a; -u32 FASTCALL OP_ADD_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; OP_ADD(1, 3); } -u32 FASTCALL OP_ADD_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_REG; OP_ADD(2, 4); } -u32 FASTCALL OP_ADD_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; OP_ADD(1, 3); } -u32 FASTCALL OP_ADD_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_REG; OP_ADD(2, 4); } -u32 FASTCALL OP_ADD_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; OP_ADD(1, 3); } -u32 FASTCALL OP_ADD_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_REG; OP_ADD(2, 4); } -u32 FASTCALL OP_ADD_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; OP_ADD(1, 3); } -u32 FASTCALL OP_ADD_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_REG; OP_ADD(2, 4); } -u32 FASTCALL OP_ADD_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; IMM_VALUE; @@ -945,7 +945,7 @@ u32 FASTCALL OP_ADD_IMM_VAL(armcpu_t *cpu) cpu->CPSR.bits.V = SIGNED_OVERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\ return a; -u32 FASTCALL OP_ADD_S_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_S_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -953,7 +953,7 @@ u32 FASTCALL OP_ADD_S_LSL_IMM(armcpu_t *cpu) OP_ADDS(2, 4); } -u32 FASTCALL OP_ADD_S_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_S_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -961,7 +961,7 @@ u32 FASTCALL OP_ADD_S_LSL_REG(armcpu_t *cpu) OP_ADDS(3, 5); } -u32 FASTCALL OP_ADD_S_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_S_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -969,7 +969,7 @@ u32 FASTCALL OP_ADD_S_LSR_IMM(armcpu_t *cpu) OP_ADDS(2, 4); } -u32 FASTCALL OP_ADD_S_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_S_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -977,7 +977,7 @@ u32 FASTCALL OP_ADD_S_LSR_REG(armcpu_t *cpu) OP_ADDS(3, 5); } -u32 FASTCALL OP_ADD_S_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_S_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -985,7 +985,7 @@ u32 FASTCALL OP_ADD_S_ASR_IMM(armcpu_t *cpu) OP_ADDS(2, 4); } -u32 FASTCALL OP_ADD_S_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_S_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -993,7 +993,7 @@ u32 FASTCALL OP_ADD_S_ASR_REG(armcpu_t *cpu) OP_ADDS(3, 5); } -u32 FASTCALL OP_ADD_S_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_S_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1001,7 +1001,7 @@ u32 FASTCALL OP_ADD_S_ROR_IMM(armcpu_t *cpu) OP_ADDS(2, 4); } -u32 FASTCALL OP_ADD_S_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_S_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1009,7 +1009,7 @@ u32 FASTCALL OP_ADD_S_ROR_REG(armcpu_t *cpu) OP_ADDS(3, 5); } -u32 FASTCALL OP_ADD_S_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_S_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1027,63 +1027,63 @@ u32 FASTCALL OP_ADD_S_IMM_VAL(armcpu_t *cpu) }\ return a; -u32 FASTCALL OP_ADC_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; OP_ADC(1, 3); } -u32 FASTCALL OP_ADC_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_REG; OP_ADC(2, 4); } -u32 FASTCALL OP_ADC_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; OP_ADC(1, 3); } -u32 FASTCALL OP_ADC_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_REG; OP_ADC(2, 4); } -u32 FASTCALL OP_ADC_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; OP_ADC(1, 3); } -u32 FASTCALL OP_ADC_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_REG; OP_ADC(2, 4); } -u32 FASTCALL OP_ADC_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; OP_ADC(1, 3); } -u32 FASTCALL OP_ADC_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_REG; OP_ADC(2, 4); } -u32 FASTCALL OP_ADC_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; IMM_VALUE; @@ -1107,7 +1107,7 @@ u32 FASTCALL OP_ADC_IMM_VAL(armcpu_t *cpu) cpu->CPSR.bits.V = SIGNED_OVERFLOW(shift_op, cpu->CPSR.bits.C, tmp) | SIGNED_OVERFLOW(v, tmp, cpu->R[REG_POS(i,12)]);\ return a; -u32 FASTCALL OP_ADC_S_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_S_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1115,7 +1115,7 @@ u32 FASTCALL OP_ADC_S_LSL_IMM(armcpu_t *cpu) OP_ADCS(2, 4); } -u32 FASTCALL OP_ADC_S_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_S_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1123,7 +1123,7 @@ u32 FASTCALL OP_ADC_S_LSL_REG(armcpu_t *cpu) OP_ADCS(3, 5); } -u32 FASTCALL OP_ADC_S_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_S_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1131,7 +1131,7 @@ u32 FASTCALL OP_ADC_S_LSR_IMM(armcpu_t *cpu) OP_ADCS(2, 4); } -u32 FASTCALL OP_ADC_S_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_S_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1139,7 +1139,7 @@ u32 FASTCALL OP_ADC_S_LSR_REG(armcpu_t *cpu) OP_ADCS(3, 5); } -u32 FASTCALL OP_ADC_S_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_S_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1147,7 +1147,7 @@ u32 FASTCALL OP_ADC_S_ASR_IMM(armcpu_t *cpu) OP_ADCS(2, 4); } -u32 FASTCALL OP_ADC_S_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_S_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1155,7 +1155,7 @@ u32 FASTCALL OP_ADC_S_ASR_REG(armcpu_t *cpu) OP_ADCS(3, 5); } -u32 FASTCALL OP_ADC_S_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_S_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1163,7 +1163,7 @@ u32 FASTCALL OP_ADC_S_ROR_IMM(armcpu_t *cpu) OP_ADCS(2, 4); } -u32 FASTCALL OP_ADC_S_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_S_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1171,7 +1171,7 @@ u32 FASTCALL OP_ADC_S_ROR_REG(armcpu_t *cpu) OP_ADCS(3, 5); } -u32 FASTCALL OP_ADC_S_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_S_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1189,63 +1189,63 @@ u32 FASTCALL OP_ADC_S_IMM_VAL(armcpu_t *cpu) }\ return a; -u32 FASTCALL OP_SBC_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; OP_SBC(1, 3); } -u32 FASTCALL OP_SBC_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_REG; OP_SBC(2, 4); } -u32 FASTCALL OP_SBC_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; OP_SBC(1, 3); } -u32 FASTCALL OP_SBC_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_REG; OP_SBC(2, 4); } -u32 FASTCALL OP_SBC_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; OP_SBC(1, 3); } -u32 FASTCALL OP_SBC_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_REG; OP_SBC(2, 4); } -u32 FASTCALL OP_SBC_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; OP_SBC(1, 3); } -u32 FASTCALL OP_SBC_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_REG; OP_SBC(2, 4); } -u32 FASTCALL OP_SBC_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; IMM_VALUE; @@ -1269,7 +1269,7 @@ u32 FASTCALL OP_SBC_IMM_VAL(armcpu_t *cpu) cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, (!cpu->CPSR.bits.C), tmp) | SIGNED_UNDERFLOW(tmp, shift_op, cpu->R[REG_POS(i,12)]);\ return a; -u32 FASTCALL OP_SBC_S_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_S_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1277,7 +1277,7 @@ u32 FASTCALL OP_SBC_S_LSL_IMM(armcpu_t *cpu) OP_SBCS(2, 4); } -u32 FASTCALL OP_SBC_S_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_S_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1285,7 +1285,7 @@ u32 FASTCALL OP_SBC_S_LSL_REG(armcpu_t *cpu) OP_SBCS(3, 5); } -u32 FASTCALL OP_SBC_S_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_S_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1293,7 +1293,7 @@ u32 FASTCALL OP_SBC_S_LSR_IMM(armcpu_t *cpu) OP_SBCS(2, 4); } -u32 FASTCALL OP_SBC_S_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_S_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1301,7 +1301,7 @@ u32 FASTCALL OP_SBC_S_LSR_REG(armcpu_t *cpu) OP_SBCS(3, 5); } -u32 FASTCALL OP_SBC_S_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_S_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1309,7 +1309,7 @@ u32 FASTCALL OP_SBC_S_ASR_IMM(armcpu_t *cpu) OP_SBCS(2, 4); } -u32 FASTCALL OP_SBC_S_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_S_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1317,7 +1317,7 @@ u32 FASTCALL OP_SBC_S_ASR_REG(armcpu_t *cpu) OP_SBCS(3, 5); } -u32 FASTCALL OP_SBC_S_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_S_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1325,7 +1325,7 @@ u32 FASTCALL OP_SBC_S_ROR_IMM(armcpu_t *cpu) OP_SBCS(2, 4); } -u32 FASTCALL OP_SBC_S_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_S_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1333,7 +1333,7 @@ u32 FASTCALL OP_SBC_S_ROR_REG(armcpu_t *cpu) OP_SBCS(3, 5); } -u32 FASTCALL OP_SBC_S_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_S_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1351,63 +1351,63 @@ u32 FASTCALL OP_SBC_S_IMM_VAL(armcpu_t *cpu) }\ return a; -u32 FASTCALL OP_RSC_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_RSC_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; OP_RSC(1, 3); } -u32 FASTCALL OP_RSC_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_RSC_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_REG; OP_RSC(2, 4); } -u32 FASTCALL OP_RSC_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_RSC_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; OP_RSC(1, 3); } -u32 FASTCALL OP_RSC_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_RSC_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_REG; OP_RSC(2, 4); } -u32 FASTCALL OP_RSC_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_RSC_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; OP_RSC(1, 3); } -u32 FASTCALL OP_RSC_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_RSC_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_REG; OP_RSC(2, 4); } -u32 FASTCALL OP_RSC_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_RSC_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; OP_RSC(1, 3); } -u32 FASTCALL OP_RSC_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_RSC_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_REG; OP_RSC(2, 4); } -u32 FASTCALL OP_RSC_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_RSC_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; IMM_VALUE; @@ -1431,7 +1431,7 @@ u32 FASTCALL OP_RSC_IMM_VAL(armcpu_t *cpu) cpu->CPSR.bits.V = SIGNED_UNDERFLOW(shift_op, (!cpu->CPSR.bits.C), tmp) | SIGNED_UNDERFLOW(tmp, v, cpu->R[REG_POS(i,12)]);\ return a; -u32 FASTCALL OP_RSC_S_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_RSC_S_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1439,7 +1439,7 @@ u32 FASTCALL OP_RSC_S_LSL_IMM(armcpu_t *cpu) OP_RSCS(2,4); } -u32 FASTCALL OP_RSC_S_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_RSC_S_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1447,7 +1447,7 @@ u32 FASTCALL OP_RSC_S_LSL_REG(armcpu_t *cpu) OP_RSCS(3,5); } -u32 FASTCALL OP_RSC_S_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_RSC_S_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1455,7 +1455,7 @@ u32 FASTCALL OP_RSC_S_LSR_IMM(armcpu_t *cpu) OP_RSCS(2,4); } -u32 FASTCALL OP_RSC_S_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_RSC_S_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1463,7 +1463,7 @@ u32 FASTCALL OP_RSC_S_LSR_REG(armcpu_t *cpu) OP_RSCS(3,5); } -u32 FASTCALL OP_RSC_S_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_RSC_S_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1471,7 +1471,7 @@ u32 FASTCALL OP_RSC_S_ASR_IMM(armcpu_t *cpu) OP_RSCS(2,4); } -u32 FASTCALL OP_RSC_S_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_RSC_S_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1479,7 +1479,7 @@ u32 FASTCALL OP_RSC_S_ASR_REG(armcpu_t *cpu) OP_RSCS(3,5); } -u32 FASTCALL OP_RSC_S_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_RSC_S_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1487,7 +1487,7 @@ u32 FASTCALL OP_RSC_S_ROR_IMM(armcpu_t *cpu) OP_RSCS(2,4); } -u32 FASTCALL OP_RSC_S_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_RSC_S_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1495,7 +1495,7 @@ u32 FASTCALL OP_RSC_S_ROR_REG(armcpu_t *cpu) OP_RSCS(3,5); } -u32 FASTCALL OP_RSC_S_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_RSC_S_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; @@ -1511,63 +1511,63 @@ u32 FASTCALL OP_RSC_S_IMM_VAL(armcpu_t *cpu) cpu->CPSR.bits.Z = (tmp==0);\ return a; -u32 FASTCALL OP_TST_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_TST_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSL_IMM; OP_TST(1); } -u32 FASTCALL OP_TST_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_TST_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSL_REG; OP_TST(2); } -u32 FASTCALL OP_TST_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_TST_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSR_IMM; OP_TST(1); } -u32 FASTCALL OP_TST_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_TST_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSR_REG; OP_TST(2); } -u32 FASTCALL OP_TST_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_TST_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_ASR_IMM; OP_TST(1); } -u32 FASTCALL OP_TST_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_TST_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_ASR_REG; OP_TST(2); } -u32 FASTCALL OP_TST_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_TST_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_ROR_IMM; OP_TST(1); } -u32 FASTCALL OP_TST_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_TST_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_ROR_REG; OP_TST(2); } -u32 FASTCALL OP_TST_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_TST_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; S_IMM_VALUE; @@ -1582,63 +1582,63 @@ u32 FASTCALL OP_TST_IMM_VAL(armcpu_t *cpu) cpu->CPSR.bits.Z = (tmp==0);\ return a; -u32 FASTCALL OP_TEQ_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_TEQ_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSL_IMM; OP_TEQ(1); } -u32 FASTCALL OP_TEQ_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_TEQ_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSL_REG; OP_TEQ(2); } -u32 FASTCALL OP_TEQ_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_TEQ_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSR_IMM; OP_TEQ(1); } -u32 FASTCALL OP_TEQ_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_TEQ_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSR_REG; OP_TEQ(2); } -u32 FASTCALL OP_TEQ_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_TEQ_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_ASR_IMM; OP_TEQ(1); } -u32 FASTCALL OP_TEQ_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_TEQ_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_ASR_REG; OP_TEQ(2); } -u32 FASTCALL OP_TEQ_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_TEQ_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_ROR_IMM; OP_TEQ(1); } -u32 FASTCALL OP_TEQ_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_TEQ_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_ROR_REG; OP_TEQ(2); } -u32 FASTCALL OP_TEQ_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_TEQ_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; S_IMM_VALUE; @@ -1654,63 +1654,63 @@ u32 FASTCALL OP_TEQ_IMM_VAL(armcpu_t *cpu) cpu->CPSR.bits.V = SIGNED_UNDERFLOW(cpu->R[REG_POS(i,16)], shift_op, tmp);\ return a; -u32 FASTCALL OP_CMP_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_CMP_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; OP_CMP(1); } -u32 FASTCALL OP_CMP_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_CMP_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_REG; OP_CMP(2); } -u32 FASTCALL OP_CMP_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_CMP_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; OP_CMP(1); } -u32 FASTCALL OP_CMP_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_CMP_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_REG; OP_CMP(2); } -u32 FASTCALL OP_CMP_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_CMP_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; OP_CMP(1); } -u32 FASTCALL OP_CMP_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_CMP_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_REG; OP_CMP(2); } -u32 FASTCALL OP_CMP_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_CMP_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; OP_CMP(1); } -u32 FASTCALL OP_CMP_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_CMP_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_REG; OP_CMP(2); } -u32 FASTCALL OP_CMP_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_CMP_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; IMM_VALUE; @@ -1726,63 +1726,63 @@ u32 FASTCALL OP_CMP_IMM_VAL(armcpu_t *cpu) cpu->CPSR.bits.V = SIGNED_OVERFLOW(cpu->R[REG_POS(i,16)], shift_op, tmp);\ return a; -u32 FASTCALL OP_CMN_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_CMN_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; OP_CMN(1); } -u32 FASTCALL OP_CMN_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_CMN_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_REG; OP_CMN(2); } -u32 FASTCALL OP_CMN_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_CMN_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; OP_CMN(1); } -u32 FASTCALL OP_CMN_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_CMN_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_REG; OP_CMN(2); } -u32 FASTCALL OP_CMN_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_CMN_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; OP_CMN(1); } -u32 FASTCALL OP_CMN_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_CMN_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_REG; OP_CMN(2); } -u32 FASTCALL OP_CMN_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_CMN_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; OP_CMN(1); } -u32 FASTCALL OP_CMN_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_CMN_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_REG; OP_CMN(2); } -u32 FASTCALL OP_CMN_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_CMN_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; IMM_VALUE; @@ -1799,70 +1799,70 @@ u32 FASTCALL OP_CMN_IMM_VAL(armcpu_t *cpu) }\ return a; -u32 FASTCALL OP_ORR_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ORR_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; OP_ORR(1, 3); } -u32 FASTCALL OP_ORR_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ORR_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_REG; OP_ORR(2, 4); } -u32 FASTCALL OP_ORR_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ORR_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; OP_ORR(1, 3); } -u32 FASTCALL OP_ORR_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ORR_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_REG; OP_ORR(2, 4); } -u32 FASTCALL OP_ORR_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ORR_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; OP_ORR(1, 3); } -u32 FASTCALL OP_ORR_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ORR_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_REG; OP_ORR(2, 4); } -u32 FASTCALL OP_ORR_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ORR_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; OP_ORR(1, 3); } -u32 FASTCALL OP_ORR_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ORR_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_REG; OP_ORR(2, 4); } -u32 FASTCALL OP_ORR_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_ORR_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; IMM_VALUE; OP_ORR(1, 3); } -u32 FASTCALL OP_ORR_S_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ORR_S_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSL_IMM; @@ -1882,7 +1882,7 @@ u32 FASTCALL OP_ORR_S_LSL_IMM(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_ORR_S_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ORR_S_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSL_REG; @@ -1902,7 +1902,7 @@ u32 FASTCALL OP_ORR_S_LSL_REG(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_ORR_S_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ORR_S_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSR_IMM; @@ -1922,7 +1922,7 @@ u32 FASTCALL OP_ORR_S_LSR_IMM(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_ORR_S_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ORR_S_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSR_REG; @@ -1942,7 +1942,7 @@ u32 FASTCALL OP_ORR_S_LSR_REG(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_ORR_S_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ORR_S_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_ASR_IMM; @@ -1962,7 +1962,7 @@ u32 FASTCALL OP_ORR_S_ASR_IMM(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_ORR_S_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ORR_S_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_ASR_REG; @@ -1982,7 +1982,7 @@ u32 FASTCALL OP_ORR_S_ASR_REG(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_ORR_S_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_ORR_S_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_ROR_IMM; @@ -2002,7 +2002,7 @@ u32 FASTCALL OP_ORR_S_ROR_IMM(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_ORR_S_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ORR_S_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_ROR_REG; @@ -2022,7 +2022,7 @@ u32 FASTCALL OP_ORR_S_ROR_REG(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_ORR_S_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_ORR_S_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; S_IMM_VALUE; @@ -2066,126 +2066,126 @@ u32 FASTCALL OP_ORR_S_IMM_VAL(armcpu_t *cpu) cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ return a;\ -u32 FASTCALL OP_MOV_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; OP_MOV(1,3); } -u32 FASTCALL OP_MOV_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_REG; OP_MOV(2,4); } -u32 FASTCALL OP_MOV_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; OP_MOV(1,3); } -u32 FASTCALL OP_MOV_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_REG; OP_MOV(2,4); } -u32 FASTCALL OP_MOV_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; OP_MOV(1,3); } -u32 FASTCALL OP_MOV_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_REG; OP_MOV(2,4); } -u32 FASTCALL OP_MOV_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; OP_MOV(2,4); } -u32 FASTCALL OP_MOV_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_REG; OP_MOV(2,4); } -u32 FASTCALL OP_MOV_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; IMM_VALUE; OP_MOV(1,3); } -u32 FASTCALL OP_MOV_S_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_S_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSL_IMM; OP_MOV_S(2,4); } -u32 FASTCALL OP_MOV_S_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_S_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSL_REG; OP_MOV_S(3,5); } -u32 FASTCALL OP_MOV_S_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_S_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSR_IMM; OP_MOV_S(2,4); } -u32 FASTCALL OP_MOV_S_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_S_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSR_REG; OP_MOV_S(3,5); } -u32 FASTCALL OP_MOV_S_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_S_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_ASR_IMM; OP_MOV_S(2,4); } -u32 FASTCALL OP_MOV_S_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_S_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_ASR_REG; OP_MOV_S(3,5); } -u32 FASTCALL OP_MOV_S_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_S_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_ROR_IMM; OP_MOV_S(2,4); } -u32 FASTCALL OP_MOV_S_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_S_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_ROR_REG; OP_MOV_S(3,5); } -u32 FASTCALL OP_MOV_S_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_S_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; S_IMM_VALUE; @@ -2216,126 +2216,126 @@ u32 FASTCALL OP_MOV_S_IMM_VAL(armcpu_t *cpu) cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ return a; -u32 FASTCALL OP_BIC_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_BIC_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; OPP_BIC(1,3); } -u32 FASTCALL OP_BIC_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_BIC_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_REG; OPP_BIC(2,4); } -u32 FASTCALL OP_BIC_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_BIC_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; OPP_BIC(1,3); } -u32 FASTCALL OP_BIC_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_BIC_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_REG; OPP_BIC(2,4); } -u32 FASTCALL OP_BIC_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_BIC_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; OPP_BIC(1,3); } -u32 FASTCALL OP_BIC_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_BIC_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_REG; OPP_BIC(2,4); } -u32 FASTCALL OP_BIC_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_BIC_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; OPP_BIC(1,3); } -u32 FASTCALL OP_BIC_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_BIC_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_REG; OPP_BIC(2,4); } -u32 FASTCALL OP_BIC_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_BIC_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; IMM_VALUE; OPP_BIC(1,3); } -u32 FASTCALL OP_BIC_S_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_BIC_S_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSL_IMM; OPP_BIC_S(2,4); } -u32 FASTCALL OP_BIC_S_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_BIC_S_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSL_REG; OPP_BIC_S(3,5); } -u32 FASTCALL OP_BIC_S_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_BIC_S_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSR_IMM; OPP_BIC_S(2,4); } -u32 FASTCALL OP_BIC_S_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_BIC_S_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSR_REG; OPP_BIC_S(3,5); } -u32 FASTCALL OP_BIC_S_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_BIC_S_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_ASR_IMM; OPP_BIC_S(2,4); } -u32 FASTCALL OP_BIC_S_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_BIC_S_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_ASR_REG; OPP_BIC_S(3,5); } -u32 FASTCALL OP_BIC_S_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_BIC_S_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_ROR_IMM; OPP_BIC_S(2,4); } -u32 FASTCALL OP_BIC_S_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_BIC_S_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_ROR_REG; OPP_BIC_S(3,5); } -u32 FASTCALL OP_BIC_S_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_BIC_S_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; S_IMM_VALUE; @@ -2366,126 +2366,126 @@ u32 FASTCALL OP_BIC_S_IMM_VAL(armcpu_t *cpu) cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ return a; -u32 FASTCALL OP_MVN_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_MVN_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; OPP_MVN(1,3); } -u32 FASTCALL OP_MVN_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_MVN_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_REG; OPP_MVN(2,4); } -u32 FASTCALL OP_MVN_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_MVN_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; OPP_MVN(1,3); } -u32 FASTCALL OP_MVN_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_MVN_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_REG; OPP_MVN(2,4); } -u32 FASTCALL OP_MVN_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_MVN_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; OPP_MVN(1,3); } -u32 FASTCALL OP_MVN_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_MVN_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_REG; OPP_MVN(2,4); } -u32 FASTCALL OP_MVN_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_MVN_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; OPP_MVN(1,3); } -u32 FASTCALL OP_MVN_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_MVN_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_REG; OPP_MVN(2,4); } -u32 FASTCALL OP_MVN_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_MVN_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; IMM_VALUE; OPP_MVN(1,3); } -u32 FASTCALL OP_MVN_S_LSL_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_MVN_S_LSL_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSL_IMM; OPP_MVN_S(2,4); } -u32 FASTCALL OP_MVN_S_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_MVN_S_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSL_REG; OPP_MVN_S(3,5); } -u32 FASTCALL OP_MVN_S_LSR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_MVN_S_LSR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSR_IMM; OPP_MVN_S(2,4); } -u32 FASTCALL OP_MVN_S_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_MVN_S_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_LSR_REG; OPP_MVN_S(3,5); } -u32 FASTCALL OP_MVN_S_ASR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_MVN_S_ASR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_ASR_IMM; OPP_MVN_S(2,4); } -u32 FASTCALL OP_MVN_S_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_MVN_S_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_ASR_REG; OPP_MVN_S(3,5); } -u32 FASTCALL OP_MVN_S_ROR_IMM(armcpu_t *cpu) +static u32 FASTCALL OP_MVN_S_ROR_IMM(armcpu_t *cpu) { u32 i = cpu->instruction; S_ROR_IMM; OPP_MVN_S(2,4); } -u32 FASTCALL OP_MVN_S_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_MVN_S_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; S_ROR_REG; OPP_MVN_S(3,5); } -u32 FASTCALL OP_MVN_S_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_MVN_S_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; S_IMM_VALUE; @@ -2504,7 +2504,7 @@ u32 FASTCALL OP_MVN_S_IMM_VAL(armcpu_t *cpu) return b+2;\ return a;\ -u32 FASTCALL OP_MUL(armcpu_t *cpu) +static u32 FASTCALL OP_MUL(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,0)]; @@ -2512,7 +2512,7 @@ u32 FASTCALL OP_MUL(armcpu_t *cpu) OPP_M(5,2); } -u32 FASTCALL OP_MLA(armcpu_t *cpu) +static u32 FASTCALL OP_MLA(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,0)]; @@ -2523,7 +2523,7 @@ u32 FASTCALL OP_MLA(armcpu_t *cpu) OPP_M(6,3); } -u32 FASTCALL OP_MUL_S(armcpu_t *cpu) +static u32 FASTCALL OP_MUL_S(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,0)]; @@ -2535,7 +2535,7 @@ u32 FASTCALL OP_MUL_S(armcpu_t *cpu) OPP_M(6,3); } -u32 FASTCALL OP_MLA_S(armcpu_t *cpu) +static u32 FASTCALL OP_MLA_S(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,0)]; @@ -2547,7 +2547,7 @@ u32 FASTCALL OP_MLA_S(armcpu_t *cpu) //----------UMUL-------------------------- -u32 FASTCALL OP_UMULL(armcpu_t *cpu) +static u32 FASTCALL OP_UMULL(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,0)]; @@ -2559,7 +2559,7 @@ u32 FASTCALL OP_UMULL(armcpu_t *cpu) OPP_M(6,3); } -u32 FASTCALL OP_UMLAL(armcpu_t *cpu) +static u32 FASTCALL OP_UMLAL(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,0)]; @@ -2571,7 +2571,7 @@ u32 FASTCALL OP_UMLAL(armcpu_t *cpu) OPP_M(7,4); } -u32 FASTCALL OP_UMULL_S(armcpu_t *cpu) +static u32 FASTCALL OP_UMULL_S(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,0)]; @@ -2586,7 +2586,7 @@ u32 FASTCALL OP_UMULL_S(armcpu_t *cpu) OPP_M(7,4); } -u32 FASTCALL OP_UMLAL_S(armcpu_t *cpu) +static u32 FASTCALL OP_UMLAL_S(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_POS(i,0)]; @@ -2603,7 +2603,7 @@ u32 FASTCALL OP_UMLAL_S(armcpu_t *cpu) //----------SMUL-------------------------- -u32 FASTCALL OP_SMULL(armcpu_t *cpu) +static u32 FASTCALL OP_SMULL(armcpu_t *cpu) { u32 i = cpu->instruction; s64 v = (s32)cpu->R[REG_POS(i,0)]; @@ -2618,7 +2618,7 @@ u32 FASTCALL OP_SMULL(armcpu_t *cpu) OPP_M(6,3); } -u32 FASTCALL OP_SMLAL(armcpu_t *cpu) +static u32 FASTCALL OP_SMLAL(armcpu_t *cpu) { u32 i = cpu->instruction; @@ -2638,7 +2638,7 @@ u32 FASTCALL OP_SMLAL(armcpu_t *cpu) OPP_M(7,4); } -u32 FASTCALL OP_SMULL_S(armcpu_t *cpu) +static u32 FASTCALL OP_SMULL_S(armcpu_t *cpu) { u32 i = cpu->instruction; s64 v = (s32)cpu->R[REG_POS(i,0)]; @@ -2656,7 +2656,7 @@ u32 FASTCALL OP_SMULL_S(armcpu_t *cpu) OPP_M(7,4); } -u32 FASTCALL OP_SMLAL_S(armcpu_t *cpu) +static u32 FASTCALL OP_SMLAL_S(armcpu_t *cpu) { u32 i = cpu->instruction; s64 v = (s32)cpu->R[REG_POS(i,0)]; @@ -2676,7 +2676,7 @@ u32 FASTCALL OP_SMLAL_S(armcpu_t *cpu) //---------------SWP------------------------------ -u32 FASTCALL OP_SWP(armcpu_t *cpu) +static u32 FASTCALL OP_SWP(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -2688,7 +2688,7 @@ u32 FASTCALL OP_SWP(armcpu_t *cpu) return 4 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]*2; } -u32 FASTCALL OP_SWPB(armcpu_t *cpu) +static u32 FASTCALL OP_SWPB(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -2701,7 +2701,7 @@ u32 FASTCALL OP_SWPB(armcpu_t *cpu) //------------LDRH----------------------------- -u32 FASTCALL OP_LDRH_P_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRH_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; @@ -2710,7 +2710,7 @@ u32 FASTCALL OP_LDRH_P_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRH_M_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRH_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; @@ -2719,7 +2719,7 @@ u32 FASTCALL OP_LDRH_M_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRH_P_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRH_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; @@ -2728,7 +2728,7 @@ u32 FASTCALL OP_LDRH_P_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRH_M_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRH_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; @@ -2737,7 +2737,7 @@ u32 FASTCALL OP_LDRH_M_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; @@ -2747,7 +2747,7 @@ u32 FASTCALL OP_LDRH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; @@ -2757,7 +2757,7 @@ u32 FASTCALL OP_LDRH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRH_PRE_INDE_P_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRH_PRE_INDE_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; @@ -2767,7 +2767,7 @@ u32 FASTCALL OP_LDRH_PRE_INDE_P_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRH_PRE_INDE_M_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRH_PRE_INDE_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; @@ -2777,7 +2777,7 @@ u32 FASTCALL OP_LDRH_PRE_INDE_M_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRH_POS_INDE_P_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRH_POS_INDE_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -2787,7 +2787,7 @@ u32 FASTCALL OP_LDRH_POS_INDE_P_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRH_POS_INDE_M_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRH_POS_INDE_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -2797,7 +2797,7 @@ u32 FASTCALL OP_LDRH_POS_INDE_M_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRH_POS_INDE_P_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRH_POS_INDE_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -2807,7 +2807,7 @@ u32 FASTCALL OP_LDRH_POS_INDE_P_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRH_POS_INDE_M_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRH_POS_INDE_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -2819,7 +2819,7 @@ u32 FASTCALL OP_LDRH_POS_INDE_M_REG_OFF(armcpu_t *cpu) //------------STRH----------------------------- -u32 FASTCALL OP_STRH_P_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRH_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; @@ -2828,7 +2828,7 @@ u32 FASTCALL OP_STRH_P_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRH_M_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRH_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; @@ -2837,7 +2837,7 @@ u32 FASTCALL OP_STRH_M_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRH_P_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRH_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; @@ -2846,7 +2846,7 @@ u32 FASTCALL OP_STRH_P_REG_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRH_M_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRH_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; @@ -2855,7 +2855,7 @@ u32 FASTCALL OP_STRH_M_REG_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; @@ -2865,7 +2865,7 @@ u32 FASTCALL OP_STRH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; @@ -2875,7 +2875,7 @@ u32 FASTCALL OP_STRH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRH_PRE_INDE_P_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRH_PRE_INDE_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; @@ -2885,7 +2885,7 @@ u32 FASTCALL OP_STRH_PRE_INDE_P_REG_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRH_PRE_INDE_M_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRH_PRE_INDE_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; @@ -2895,7 +2895,7 @@ u32 FASTCALL OP_STRH_PRE_INDE_M_REG_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRH_POS_INDE_P_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRH_POS_INDE_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -2905,7 +2905,7 @@ u32 FASTCALL OP_STRH_POS_INDE_P_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRH_POS_INDE_M_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRH_POS_INDE_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -2915,7 +2915,7 @@ u32 FASTCALL OP_STRH_POS_INDE_M_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRH_POS_INDE_P_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRH_POS_INDE_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -2925,7 +2925,7 @@ u32 FASTCALL OP_STRH_POS_INDE_P_REG_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRH_POS_INDE_M_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRH_POS_INDE_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -2937,7 +2937,7 @@ u32 FASTCALL OP_STRH_POS_INDE_M_REG_OFF(armcpu_t *cpu) //----------------LDRSH-------------------------- -u32 FASTCALL OP_LDRSH_P_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSH_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; @@ -2946,7 +2946,7 @@ u32 FASTCALL OP_LDRSH_P_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSH_M_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSH_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; @@ -2955,7 +2955,7 @@ u32 FASTCALL OP_LDRSH_M_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSH_P_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSH_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; @@ -2964,7 +2964,7 @@ u32 FASTCALL OP_LDRSH_P_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSH_M_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSH_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; @@ -2973,7 +2973,7 @@ u32 FASTCALL OP_LDRSH_M_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; @@ -2983,7 +2983,7 @@ u32 FASTCALL OP_LDRSH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; @@ -2993,7 +2993,7 @@ u32 FASTCALL OP_LDRSH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSH_PRE_INDE_P_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSH_PRE_INDE_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; @@ -3003,7 +3003,7 @@ u32 FASTCALL OP_LDRSH_PRE_INDE_P_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSH_PRE_INDE_M_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSH_PRE_INDE_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; @@ -3013,7 +3013,7 @@ u32 FASTCALL OP_LDRSH_PRE_INDE_M_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSH_POS_INDE_P_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSH_POS_INDE_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -3023,7 +3023,7 @@ u32 FASTCALL OP_LDRSH_POS_INDE_P_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSH_POS_INDE_M_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSH_POS_INDE_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -3033,7 +3033,7 @@ u32 FASTCALL OP_LDRSH_POS_INDE_M_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSH_POS_INDE_P_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSH_POS_INDE_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -3043,7 +3043,7 @@ u32 FASTCALL OP_LDRSH_POS_INDE_P_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSH_POS_INDE_M_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSH_POS_INDE_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -3055,7 +3055,7 @@ u32 FASTCALL OP_LDRSH_POS_INDE_M_REG_OFF(armcpu_t *cpu) //----------------------LDRSB---------------------- -u32 FASTCALL OP_LDRSB_P_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSB_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; @@ -3064,7 +3064,7 @@ u32 FASTCALL OP_LDRSB_P_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSB_M_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSB_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; @@ -3073,7 +3073,7 @@ u32 FASTCALL OP_LDRSB_M_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSB_P_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSB_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; @@ -3082,7 +3082,7 @@ u32 FASTCALL OP_LDRSB_P_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSB_M_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSB_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; @@ -3091,7 +3091,7 @@ u32 FASTCALL OP_LDRSB_M_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSB_PRE_INDE_P_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSB_PRE_INDE_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; @@ -3101,7 +3101,7 @@ u32 FASTCALL OP_LDRSB_PRE_INDE_P_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSB_PRE_INDE_M_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSB_PRE_INDE_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; @@ -3111,7 +3111,7 @@ u32 FASTCALL OP_LDRSB_PRE_INDE_M_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSB_PRE_INDE_P_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSB_PRE_INDE_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; @@ -3121,7 +3121,7 @@ u32 FASTCALL OP_LDRSB_PRE_INDE_P_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSB_PRE_INDE_M_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSB_PRE_INDE_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; @@ -3131,7 +3131,7 @@ u32 FASTCALL OP_LDRSB_PRE_INDE_M_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSB_POS_INDE_P_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSB_POS_INDE_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -3141,7 +3141,7 @@ u32 FASTCALL OP_LDRSB_POS_INDE_P_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSB_POS_INDE_M_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSB_POS_INDE_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -3151,7 +3151,7 @@ u32 FASTCALL OP_LDRSB_POS_INDE_M_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSB_POS_INDE_P_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSB_POS_INDE_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -3161,7 +3161,7 @@ u32 FASTCALL OP_LDRSB_POS_INDE_P_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSB_POS_INDE_M_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSB_POS_INDE_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -3173,14 +3173,14 @@ u32 FASTCALL OP_LDRSB_POS_INDE_M_REG_OFF(armcpu_t *cpu) //--------------MRS-------------------------------- -u32 FASTCALL OP_MRS_CPSR(armcpu_t *cpu) +static u32 FASTCALL OP_MRS_CPSR(armcpu_t *cpu) { cpu->R[REG_POS(cpu->instruction,12)] = cpu->CPSR.val; return 1; } -u32 FASTCALL OP_MRS_SPSR(armcpu_t *cpu) +static u32 FASTCALL OP_MRS_SPSR(armcpu_t *cpu) { cpu->R[REG_POS(cpu->instruction,12)] = cpu->SPSR.val; @@ -3189,7 +3189,7 @@ u32 FASTCALL OP_MRS_SPSR(armcpu_t *cpu) //--------------MSR-------------------------------- -u32 FASTCALL OP_MSR_CPSR(armcpu_t *cpu) +static u32 FASTCALL OP_MSR_CPSR(armcpu_t *cpu) { u32 i = cpu->instruction; u32 operand = cpu->R[REG_POS(i,0)]; @@ -3212,7 +3212,7 @@ u32 FASTCALL OP_MSR_CPSR(armcpu_t *cpu) return 1; } -u32 FASTCALL OP_MSR_SPSR(armcpu_t *cpu) +static u32 FASTCALL OP_MSR_SPSR(armcpu_t *cpu) { u32 i = cpu->instruction; u32 operand = cpu->R[REG_POS(i,0)]; @@ -3234,7 +3234,7 @@ u32 FASTCALL OP_MSR_SPSR(armcpu_t *cpu) return 1; } -u32 FASTCALL OP_MSR_CPSR_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_MSR_CPSR_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; IMM_VALUE; @@ -3260,7 +3260,7 @@ u32 FASTCALL OP_MSR_CPSR_IMM_VAL(armcpu_t *cpu) return 1; } -u32 FASTCALL OP_MSR_SPSR_IMM_VAL(armcpu_t *cpu) +static u32 FASTCALL OP_MSR_SPSR_IMM_VAL(armcpu_t *cpu) { u32 i = cpu->instruction; IMM_VALUE; @@ -3284,7 +3284,7 @@ u32 FASTCALL OP_MSR_SPSR_IMM_VAL(armcpu_t *cpu) //-----------------BRANCH-------------------------- -u32 FASTCALL OP_BX(armcpu_t *cpu) +static u32 FASTCALL OP_BX(armcpu_t *cpu) { u32 tmp = cpu->R[REG_POS(cpu->instruction, 0)]; @@ -3294,7 +3294,7 @@ u32 FASTCALL OP_BX(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_BLX_REG(armcpu_t *cpu) +static u32 FASTCALL OP_BLX_REG(armcpu_t *cpu) { u32 tmp = cpu->R[REG_POS(cpu->instruction, 0)]; @@ -3307,7 +3307,7 @@ u32 FASTCALL OP_BLX_REG(armcpu_t *cpu) #define SIGNEXTEND_24(i) (((s32)((i)<<8))>>8) -u32 FASTCALL OP_B(armcpu_t *cpu) +static u32 FASTCALL OP_B(armcpu_t *cpu) { u32 off = SIGNEXTEND_24(cpu->instruction); if(CONDITION(cpu->instruction)==0xF) @@ -3320,7 +3320,7 @@ u32 FASTCALL OP_B(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_BL(armcpu_t *cpu) +static u32 FASTCALL OP_BL(armcpu_t *cpu) { u32 off = SIGNEXTEND_24(cpu->instruction); if(CONDITION(cpu->instruction)==0xF) @@ -3345,7 +3345,7 @@ u8 CLZ_TAB[16]= 4, 4, 4, 4, 4, 4, 4, 4 // 1XXX }; -u32 FASTCALL OP_CLZ(armcpu_t *cpu) +static u32 FASTCALL OP_CLZ(armcpu_t *cpu) { u32 i = cpu->instruction; u32 Rm = cpu->R[REG_POS(i,0)]; @@ -3379,7 +3379,7 @@ u32 FASTCALL OP_CLZ(armcpu_t *cpu) //--------------------QADD--QSUB------------------------------ -u32 FASTCALL OP_QADD(armcpu_t *cpu) +static u32 FASTCALL OP_QADD(armcpu_t *cpu) { u32 i = cpu->instruction; u32 res = cpu->R[REG_POS(i,16)]+cpu->R[REG_POS(i,0)]; @@ -3401,7 +3401,7 @@ u32 FASTCALL OP_QADD(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_QSUB(armcpu_t *cpu) +static u32 FASTCALL OP_QSUB(armcpu_t *cpu) { u32 i = cpu->instruction; u32 res = cpu->R[REG_POS(i,0)]-cpu->R[REG_POS(i,16)]; @@ -3423,7 +3423,7 @@ u32 FASTCALL OP_QSUB(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_QDADD(armcpu_t *cpu) +static u32 FASTCALL OP_QDADD(armcpu_t *cpu) { u32 i = cpu->instruction; u32 mul = cpu->R[REG_POS(i,16)]<<1; @@ -3454,7 +3454,7 @@ u32 FASTCALL OP_QDADD(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_QDSUB(armcpu_t *cpu) +static u32 FASTCALL OP_QDSUB(armcpu_t *cpu) { u32 i = cpu->instruction; u32 mul = cpu->R[REG_POS(i,16)]<<1; @@ -3490,7 +3490,7 @@ u32 FASTCALL OP_QDSUB(armcpu_t *cpu) #define HWORD(i) ((s32)(((s32)(i))>>16)) #define LWORD(i) (s32)(((s32)((i)<<16))>>16) -u32 FASTCALL OP_SMUL_B_B(armcpu_t *cpu) +static u32 FASTCALL OP_SMUL_B_B(armcpu_t *cpu) { u32 i = cpu->instruction; @@ -3499,7 +3499,7 @@ u32 FASTCALL OP_SMUL_B_B(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_SMUL_B_T(armcpu_t *cpu) +static u32 FASTCALL OP_SMUL_B_T(armcpu_t *cpu) { u32 i = cpu->instruction; @@ -3508,7 +3508,7 @@ u32 FASTCALL OP_SMUL_B_T(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_SMUL_T_B(armcpu_t *cpu) +static u32 FASTCALL OP_SMUL_T_B(armcpu_t *cpu) { u32 i = cpu->instruction; @@ -3517,7 +3517,7 @@ u32 FASTCALL OP_SMUL_T_B(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_SMUL_T_T(armcpu_t *cpu) +static u32 FASTCALL OP_SMUL_T_T(armcpu_t *cpu) { u32 i = cpu->instruction; @@ -3528,7 +3528,7 @@ u32 FASTCALL OP_SMUL_T_T(armcpu_t *cpu) //-----------SMLA---------------------------- -u32 FASTCALL OP_SMLA_B_B(armcpu_t *cpu) +static u32 FASTCALL OP_SMLA_B_B(armcpu_t *cpu) { u32 i = cpu->instruction; u32 tmp = (u32)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); @@ -3543,7 +3543,7 @@ u32 FASTCALL OP_SMLA_B_B(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_SMLA_B_T(armcpu_t *cpu) +static u32 FASTCALL OP_SMLA_B_T(armcpu_t *cpu) { u32 i = cpu->instruction; u32 tmp = (u32)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); @@ -3558,7 +3558,7 @@ u32 FASTCALL OP_SMLA_B_T(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_SMLA_T_B(armcpu_t *cpu) +static u32 FASTCALL OP_SMLA_T_B(armcpu_t *cpu) { u32 i = cpu->instruction; u32 tmp = (u32)(HWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); @@ -3573,7 +3573,7 @@ u32 FASTCALL OP_SMLA_T_B(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_SMLA_T_T(armcpu_t *cpu) +static u32 FASTCALL OP_SMLA_T_T(armcpu_t *cpu) { u32 i = cpu->instruction; u32 tmp = (u32)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); @@ -3590,7 +3590,7 @@ u32 FASTCALL OP_SMLA_T_T(armcpu_t *cpu) //--------------SMLAL--------------------------------------- -u32 FASTCALL OP_SMLAL_B_B(armcpu_t *cpu) +static u32 FASTCALL OP_SMLAL_B_B(armcpu_t *cpu) { u32 i = cpu->instruction; s64 tmp = (s64)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); @@ -3604,7 +3604,7 @@ u32 FASTCALL OP_SMLAL_B_B(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_SMLAL_B_T(armcpu_t *cpu) +static u32 FASTCALL OP_SMLAL_B_T(armcpu_t *cpu) { u32 i = cpu->instruction; s64 tmp = (s64)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); @@ -3618,7 +3618,7 @@ u32 FASTCALL OP_SMLAL_B_T(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_SMLAL_T_B(armcpu_t *cpu) +static u32 FASTCALL OP_SMLAL_T_B(armcpu_t *cpu) { u32 i = cpu->instruction; s64 tmp = (s64)(HWORD(cpu->R[REG_POS(i,0)])* (s64)LWORD(cpu->R[REG_POS(i,8)])); @@ -3632,7 +3632,7 @@ u32 FASTCALL OP_SMLAL_T_B(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_SMLAL_T_T(armcpu_t *cpu) +static u32 FASTCALL OP_SMLAL_T_T(armcpu_t *cpu) { u32 i = cpu->instruction; s64 tmp = (s64)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); @@ -3648,7 +3648,7 @@ u32 FASTCALL OP_SMLAL_T_T(armcpu_t *cpu) //--------------SMULW-------------------- -u32 FASTCALL OP_SMULW_B(armcpu_t *cpu) +static u32 FASTCALL OP_SMULW_B(armcpu_t *cpu) { u32 i = cpu->instruction; s64 tmp = (s64)LWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); @@ -3660,7 +3660,7 @@ u32 FASTCALL OP_SMULW_B(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_SMULW_T(armcpu_t *cpu) +static u32 FASTCALL OP_SMULW_T(armcpu_t *cpu) { u32 i = cpu->instruction; s64 tmp = (s64)HWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); @@ -3673,7 +3673,7 @@ u32 FASTCALL OP_SMULW_T(armcpu_t *cpu) } //--------------SMLAW------------------- -u32 FASTCALL OP_SMLAW_B(armcpu_t *cpu) +static u32 FASTCALL OP_SMLAW_B(armcpu_t *cpu) { u32 i = cpu->instruction; s64 tmp = (s64)LWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); @@ -3691,7 +3691,7 @@ u32 FASTCALL OP_SMLAW_B(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_SMLAW_T(armcpu_t *cpu) +static u32 FASTCALL OP_SMLAW_T(armcpu_t *cpu) { u32 i = cpu->instruction; s64 tmp = (s64)HWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); @@ -3710,7 +3710,7 @@ u32 FASTCALL OP_SMLAW_T(armcpu_t *cpu) //------------LDR--------------------------- -u32 FASTCALL OP_LDR_P_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; @@ -3731,7 +3731,7 @@ u32 FASTCALL OP_LDR_P_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_M_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; @@ -3753,7 +3753,7 @@ u32 FASTCALL OP_LDR_M_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_P_LSL_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -3776,7 +3776,7 @@ u32 FASTCALL OP_LDR_P_LSL_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_M_LSL_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -3799,7 +3799,7 @@ u32 FASTCALL OP_LDR_M_LSL_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_P_LSR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -3822,7 +3822,7 @@ u32 FASTCALL OP_LDR_P_LSR_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_M_LSR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -3845,7 +3845,7 @@ u32 FASTCALL OP_LDR_M_LSR_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_P_ASR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -3868,7 +3868,7 @@ u32 FASTCALL OP_LDR_P_ASR_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_M_ASR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -3891,7 +3891,7 @@ u32 FASTCALL OP_LDR_M_ASR_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_P_ROR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -3914,7 +3914,7 @@ u32 FASTCALL OP_LDR_P_ROR_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_M_ROR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -3938,7 +3938,7 @@ u32 FASTCALL OP_LDR_M_ROR_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_P_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_P_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; @@ -3962,7 +3962,7 @@ u32 FASTCALL OP_LDR_P_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_M_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_M_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; @@ -3986,7 +3986,7 @@ u32 FASTCALL OP_LDR_M_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -4011,7 +4011,7 @@ u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -4036,7 +4036,7 @@ u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -4061,7 +4061,7 @@ u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -4086,7 +4086,7 @@ u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -4111,7 +4111,7 @@ u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -4136,7 +4136,7 @@ u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -4161,7 +4161,7 @@ u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -4186,7 +4186,7 @@ u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -4211,7 +4211,7 @@ u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND(armcpu_t *cpu) } //------------------------------------------------------------ -u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND2(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND2(armcpu_t *cpu) { u32 i = cpu->instruction; @@ -4240,7 +4240,7 @@ u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND2(armcpu_t *cpu) //------------------------------------------------------------ -u32 FASTCALL OP_LDR_M_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_M_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -4264,7 +4264,7 @@ u32 FASTCALL OP_LDR_M_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -4289,7 +4289,7 @@ u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -4314,7 +4314,7 @@ u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -4339,7 +4339,7 @@ u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -4364,7 +4364,7 @@ u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -4389,7 +4389,7 @@ u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -4414,7 +4414,7 @@ u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -4439,7 +4439,7 @@ u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -4466,7 +4466,7 @@ u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) //-----------------LDRB------------------------------------------- -u32 FASTCALL OP_LDRB_P_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; @@ -4476,7 +4476,7 @@ u32 FASTCALL OP_LDRB_P_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_M_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; @@ -4486,7 +4486,7 @@ u32 FASTCALL OP_LDRB_M_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -4497,7 +4497,7 @@ u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -4508,7 +4508,7 @@ u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -4519,7 +4519,7 @@ u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -4530,7 +4530,7 @@ u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -4541,7 +4541,7 @@ u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -4552,7 +4552,7 @@ u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -4563,7 +4563,7 @@ u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -4575,7 +4575,7 @@ u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_P_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_P_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; @@ -4586,7 +4586,7 @@ u32 FASTCALL OP_LDRB_P_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_M_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_M_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; @@ -4597,7 +4597,7 @@ u32 FASTCALL OP_LDRB_M_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -4609,7 +4609,7 @@ u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -4621,7 +4621,7 @@ u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -4633,7 +4633,7 @@ u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -4645,7 +4645,7 @@ u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -4657,7 +4657,7 @@ u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -4669,7 +4669,7 @@ u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -4681,7 +4681,7 @@ u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -4693,7 +4693,7 @@ u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_P_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_P_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -4704,7 +4704,7 @@ u32 FASTCALL OP_LDRB_P_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_M_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_M_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -4715,7 +4715,7 @@ u32 FASTCALL OP_LDRB_M_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -4727,7 +4727,7 @@ u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -4739,7 +4739,7 @@ u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -4751,7 +4751,7 @@ u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -4763,7 +4763,7 @@ u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -4775,7 +4775,7 @@ u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -4787,7 +4787,7 @@ u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -4799,7 +4799,7 @@ u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -4813,7 +4813,7 @@ u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) //----------------------STR-------------------------------- -u32 FASTCALL OP_STR_P_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STR_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; @@ -4822,7 +4822,7 @@ u32 FASTCALL OP_STR_P_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_M_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STR_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; @@ -4831,7 +4831,7 @@ u32 FASTCALL OP_STR_M_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_P_LSL_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STR_P_LSL_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -4841,7 +4841,7 @@ u32 FASTCALL OP_STR_P_LSL_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_M_LSL_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STR_M_LSL_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -4851,7 +4851,7 @@ u32 FASTCALL OP_STR_M_LSL_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_P_LSR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STR_P_LSR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -4861,7 +4861,7 @@ u32 FASTCALL OP_STR_P_LSR_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_M_LSR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STR_M_LSR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -4871,7 +4871,7 @@ u32 FASTCALL OP_STR_M_LSR_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_P_ASR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STR_P_ASR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -4881,7 +4881,7 @@ u32 FASTCALL OP_STR_P_ASR_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_M_ASR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STR_M_ASR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -4891,7 +4891,7 @@ u32 FASTCALL OP_STR_M_ASR_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_P_ROR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STR_P_ROR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -4901,7 +4901,7 @@ u32 FASTCALL OP_STR_P_ROR_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_M_ROR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STR_M_ROR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -4912,7 +4912,7 @@ u32 FASTCALL OP_STR_M_ROR_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_P_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_P_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; @@ -4922,7 +4922,7 @@ u32 FASTCALL OP_STR_P_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_M_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_M_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; @@ -4932,7 +4932,7 @@ u32 FASTCALL OP_STR_M_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -4943,7 +4943,7 @@ u32 FASTCALL OP_STR_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -4954,7 +4954,7 @@ u32 FASTCALL OP_STR_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -4965,7 +4965,7 @@ u32 FASTCALL OP_STR_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -4976,7 +4976,7 @@ u32 FASTCALL OP_STR_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -4987,7 +4987,7 @@ u32 FASTCALL OP_STR_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -4998,7 +4998,7 @@ u32 FASTCALL OP_STR_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -5009,7 +5009,7 @@ u32 FASTCALL OP_STR_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -5020,7 +5020,7 @@ u32 FASTCALL OP_STR_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_P_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_P_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -5030,7 +5030,7 @@ u32 FASTCALL OP_STR_P_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_M_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_M_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -5040,7 +5040,7 @@ u32 FASTCALL OP_STR_M_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -5051,7 +5051,7 @@ u32 FASTCALL OP_STR_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -5062,7 +5062,7 @@ u32 FASTCALL OP_STR_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -5073,7 +5073,7 @@ u32 FASTCALL OP_STR_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -5084,7 +5084,7 @@ u32 FASTCALL OP_STR_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -5095,7 +5095,7 @@ u32 FASTCALL OP_STR_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -5106,7 +5106,7 @@ u32 FASTCALL OP_STR_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -5117,7 +5117,7 @@ u32 FASTCALL OP_STR_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -5130,7 +5130,7 @@ u32 FASTCALL OP_STR_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) //-----------------------STRB------------------------------------- -u32 FASTCALL OP_STRB_P_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; @@ -5139,7 +5139,7 @@ u32 FASTCALL OP_STRB_P_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_M_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; @@ -5148,7 +5148,7 @@ u32 FASTCALL OP_STRB_M_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_P_LSL_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -5158,7 +5158,7 @@ u32 FASTCALL OP_STRB_P_LSL_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_M_LSL_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -5168,7 +5168,7 @@ u32 FASTCALL OP_STRB_M_LSL_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_P_LSR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -5178,7 +5178,7 @@ u32 FASTCALL OP_STRB_P_LSR_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_M_LSR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -5188,7 +5188,7 @@ u32 FASTCALL OP_STRB_M_LSR_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_P_ASR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -5198,7 +5198,7 @@ u32 FASTCALL OP_STRB_P_ASR_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_M_ASR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -5208,7 +5208,7 @@ u32 FASTCALL OP_STRB_M_ASR_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_P_ROR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -5218,7 +5218,7 @@ u32 FASTCALL OP_STRB_P_ROR_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_M_ROR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -5228,7 +5228,7 @@ u32 FASTCALL OP_STRB_M_ROR_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_P_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_P_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; @@ -5238,7 +5238,7 @@ u32 FASTCALL OP_STRB_P_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_M_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_M_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; @@ -5248,7 +5248,7 @@ u32 FASTCALL OP_STRB_M_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -5259,7 +5259,7 @@ u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -5270,7 +5270,7 @@ u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -5281,7 +5281,7 @@ u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -5292,7 +5292,7 @@ u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -5303,7 +5303,7 @@ u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -5314,7 +5314,7 @@ u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -5325,7 +5325,7 @@ u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -5336,7 +5336,7 @@ u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_P_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_P_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -5346,7 +5346,7 @@ u32 FASTCALL OP_STRB_P_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_M_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_M_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; @@ -5356,7 +5356,7 @@ u32 FASTCALL OP_STRB_M_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -5367,7 +5367,7 @@ u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSL_IMM; @@ -5378,7 +5378,7 @@ u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -5389,7 +5389,7 @@ u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; LSR_IMM; @@ -5400,7 +5400,7 @@ u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -5411,7 +5411,7 @@ u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; ASR_IMM; @@ -5422,7 +5422,7 @@ u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -5433,7 +5433,7 @@ u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; ROR_IMM; @@ -5446,7 +5446,7 @@ u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) //-----------------------LDRBT------------------------------------- -u32 FASTCALL OP_LDRBT_P_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRBT_P_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5463,7 +5463,7 @@ u32 FASTCALL OP_LDRBT_P_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5482,7 +5482,7 @@ u32 FASTCALL OP_LDRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRBT_P_REG_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRBT_P_REG_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5502,7 +5502,7 @@ u32 FASTCALL OP_LDRBT_P_REG_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5522,7 +5522,7 @@ u32 FASTCALL OP_LDRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRBT_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRBT_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5543,7 +5543,7 @@ u32 FASTCALL OP_LDRBT_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRBT_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRBT_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5564,7 +5564,7 @@ u32 FASTCALL OP_LDRBT_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRBT_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRBT_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5585,7 +5585,7 @@ u32 FASTCALL OP_LDRBT_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRBT_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRBT_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5606,7 +5606,7 @@ u32 FASTCALL OP_LDRBT_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRBT_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRBT_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5627,7 +5627,7 @@ u32 FASTCALL OP_LDRBT_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRBT_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRBT_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5648,7 +5648,7 @@ u32 FASTCALL OP_LDRBT_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5671,7 +5671,7 @@ u32 FASTCALL OP_LDRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) //----------------------STRBT---------------------------- -u32 FASTCALL OP_STRBT_P_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRBT_P_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5689,7 +5689,7 @@ u32 FASTCALL OP_STRBT_P_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5707,7 +5707,7 @@ u32 FASTCALL OP_STRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRBT_P_REG_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRBT_P_REG_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5725,7 +5725,7 @@ u32 FASTCALL OP_STRBT_P_REG_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRBT_M_REG_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRBT_M_REG_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5743,7 +5743,7 @@ u32 FASTCALL OP_STRBT_M_REG_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5762,7 +5762,7 @@ u32 FASTCALL OP_STRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRBT_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRBT_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5781,7 +5781,7 @@ u32 FASTCALL OP_STRBT_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRBT_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRBT_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5800,7 +5800,7 @@ u32 FASTCALL OP_STRBT_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRBT_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRBT_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5819,7 +5819,7 @@ u32 FASTCALL OP_STRBT_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRBT_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRBT_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5838,7 +5838,7 @@ u32 FASTCALL OP_STRBT_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRBT_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRBT_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5857,7 +5857,7 @@ u32 FASTCALL OP_STRBT_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRBT_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRBT_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5876,7 +5876,7 @@ u32 FASTCALL OP_STRBT_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -5925,7 +5925,7 @@ u32 FASTCALL OP_STRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) c += waitState[(start>>24)&0xF];\ } -u32 FASTCALL OP_LDMIA(armcpu_t *cpu) +static u32 FASTCALL OP_LDMIA(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -5963,7 +5963,7 @@ u32 FASTCALL OP_LDMIA(armcpu_t *cpu) return c + 2; } -u32 FASTCALL OP_LDMIB(armcpu_t *cpu) +static u32 FASTCALL OP_LDMIB(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6002,7 +6002,7 @@ u32 FASTCALL OP_LDMIB(armcpu_t *cpu) return c + 2; } -u32 FASTCALL OP_LDMDA(armcpu_t *cpu) +static u32 FASTCALL OP_LDMDA(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6040,7 +6040,7 @@ u32 FASTCALL OP_LDMDA(armcpu_t *cpu) return c + 2; } -u32 FASTCALL OP_LDMDB(armcpu_t *cpu) +static u32 FASTCALL OP_LDMDB(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6078,7 +6078,7 @@ u32 FASTCALL OP_LDMDB(armcpu_t *cpu) return c + 2; } -u32 FASTCALL OP_LDMIA_W(armcpu_t *cpu) +static u32 FASTCALL OP_LDMIA_W(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6117,7 +6117,7 @@ u32 FASTCALL OP_LDMIA_W(armcpu_t *cpu) return c + 2; } -u32 FASTCALL OP_LDMIB_W(armcpu_t *cpu) +static u32 FASTCALL OP_LDMIB_W(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6156,7 +6156,7 @@ u32 FASTCALL OP_LDMIB_W(armcpu_t *cpu) return c + 2; } -u32 FASTCALL OP_LDMDA_W(armcpu_t *cpu) +static u32 FASTCALL OP_LDMDA_W(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6195,7 +6195,7 @@ u32 FASTCALL OP_LDMDA_W(armcpu_t *cpu) return c + 2; } -u32 FASTCALL OP_LDMDB_W(armcpu_t *cpu) +static u32 FASTCALL OP_LDMDB_W(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6234,7 +6234,7 @@ u32 FASTCALL OP_LDMDB_W(armcpu_t *cpu) return c + 2; } -u32 FASTCALL OP_LDMIA2(armcpu_t *cpu) +static u32 FASTCALL OP_LDMIA2(armcpu_t *cpu) { u32 i = cpu->instruction; u32 oldmode; @@ -6286,7 +6286,7 @@ u32 FASTCALL OP_LDMIA2(armcpu_t *cpu) return c + 2; } -u32 FASTCALL OP_LDMIB2(armcpu_t *cpu) +static u32 FASTCALL OP_LDMIB2(armcpu_t *cpu) { u32 i = cpu->instruction; u32 oldmode; @@ -6338,7 +6338,7 @@ u32 FASTCALL OP_LDMIB2(armcpu_t *cpu) return c + 2; } -u32 FASTCALL OP_LDMDA2(armcpu_t *cpu) +static u32 FASTCALL OP_LDMDA2(armcpu_t *cpu) { u32 i = cpu->instruction; @@ -6397,7 +6397,7 @@ u32 FASTCALL OP_LDMDA2(armcpu_t *cpu) return c + 2; } -u32 FASTCALL OP_LDMDB2(armcpu_t *cpu) +static u32 FASTCALL OP_LDMDB2(armcpu_t *cpu) { u32 i = cpu->instruction; @@ -6455,7 +6455,7 @@ u32 FASTCALL OP_LDMDB2(armcpu_t *cpu) return 2 + c; } -u32 FASTCALL OP_LDMIA2_W(armcpu_t *cpu) +static u32 FASTCALL OP_LDMIA2_W(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6508,7 +6508,7 @@ u32 FASTCALL OP_LDMIA2_W(armcpu_t *cpu) return c + 2; } -u32 FASTCALL OP_LDMIB2_W(armcpu_t *cpu) +static u32 FASTCALL OP_LDMIB2_W(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6562,7 +6562,7 @@ u32 FASTCALL OP_LDMIB2_W(armcpu_t *cpu) return c + 2; } -u32 FASTCALL OP_LDMDA2_W(armcpu_t *cpu) +static u32 FASTCALL OP_LDMDA2_W(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6619,7 +6619,7 @@ u32 FASTCALL OP_LDMDA2_W(armcpu_t *cpu) return c + 2; } -u32 FASTCALL OP_LDMDB2_W(armcpu_t *cpu) +static u32 FASTCALL OP_LDMDB2_W(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6679,7 +6679,7 @@ u32 FASTCALL OP_LDMDB2_W(armcpu_t *cpu) //------------------------------STM---------------------------------- -u32 FASTCALL OP_STMIA(armcpu_t *cpu) +static u32 FASTCALL OP_STMIA(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6699,7 +6699,7 @@ u32 FASTCALL OP_STMIA(armcpu_t *cpu) return c + 1; } -u32 FASTCALL OP_STMIB(armcpu_t *cpu) +static u32 FASTCALL OP_STMIB(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6719,7 +6719,7 @@ u32 FASTCALL OP_STMIB(armcpu_t *cpu) return c + 1; } -u32 FASTCALL OP_STMDA(armcpu_t *cpu) +static u32 FASTCALL OP_STMDA(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6739,7 +6739,7 @@ u32 FASTCALL OP_STMDA(armcpu_t *cpu) return c + 1; } -u32 FASTCALL OP_STMDB(armcpu_t *cpu) +static u32 FASTCALL OP_STMDB(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6759,7 +6759,7 @@ u32 FASTCALL OP_STMDB(armcpu_t *cpu) return c + 1; } -u32 FASTCALL OP_STMIA_W(armcpu_t *cpu) +static u32 FASTCALL OP_STMIA_W(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6781,7 +6781,7 @@ u32 FASTCALL OP_STMIA_W(armcpu_t *cpu) return c + 1; } -u32 FASTCALL OP_STMIB_W(armcpu_t *cpu) +static u32 FASTCALL OP_STMIB_W(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6802,7 +6802,7 @@ u32 FASTCALL OP_STMIB_W(armcpu_t *cpu) return c + 1; } -u32 FASTCALL OP_STMDA_W(armcpu_t *cpu) +static u32 FASTCALL OP_STMDA_W(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6824,7 +6824,7 @@ u32 FASTCALL OP_STMDA_W(armcpu_t *cpu) return c + 1; } -u32 FASTCALL OP_STMDB_W(armcpu_t *cpu) +static u32 FASTCALL OP_STMDB_W(armcpu_t *cpu) { u32 i = cpu->instruction; u32 c = 0; @@ -6845,7 +6845,7 @@ u32 FASTCALL OP_STMDB_W(armcpu_t *cpu) return c + 1; } -u32 FASTCALL OP_STMIA2(armcpu_t *cpu) +static u32 FASTCALL OP_STMIA2(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -6873,7 +6873,7 @@ u32 FASTCALL OP_STMIA2(armcpu_t *cpu) return c + 1; } -u32 FASTCALL OP_STMIB2(armcpu_t *cpu) +static u32 FASTCALL OP_STMIB2(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -6901,7 +6901,7 @@ u32 FASTCALL OP_STMIB2(armcpu_t *cpu) return c + 1; } -u32 FASTCALL OP_STMDA2(armcpu_t *cpu) +static u32 FASTCALL OP_STMDA2(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -6929,7 +6929,7 @@ u32 FASTCALL OP_STMDA2(armcpu_t *cpu) return c + 1; } -u32 FASTCALL OP_STMDB2(armcpu_t *cpu) +static u32 FASTCALL OP_STMDB2(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -6955,7 +6955,7 @@ u32 FASTCALL OP_STMDB2(armcpu_t *cpu) return c + 1; } -u32 FASTCALL OP_STMIA2_W(armcpu_t *cpu) +static u32 FASTCALL OP_STMIA2_W(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -6984,7 +6984,7 @@ u32 FASTCALL OP_STMIA2_W(armcpu_t *cpu) return c + 1; } -u32 FASTCALL OP_STMIB2_W(armcpu_t *cpu) +static u32 FASTCALL OP_STMIB2_W(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -7011,7 +7011,7 @@ u32 FASTCALL OP_STMIB2_W(armcpu_t *cpu) return c + 1; } -u32 FASTCALL OP_STMDA2_W(armcpu_t *cpu) +static u32 FASTCALL OP_STMDA2_W(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -7041,7 +7041,7 @@ u32 FASTCALL OP_STMDA2_W(armcpu_t *cpu) return c + 1; } -u32 FASTCALL OP_STMDB2_W(armcpu_t *cpu) +static u32 FASTCALL OP_STMDB2_W(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; @@ -7073,7 +7073,7 @@ u32 FASTCALL OP_STMDB2_W(armcpu_t *cpu) //---------------------STC---------------------------------- -u32 FASTCALL OP_STC_P_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STC_P_IMM_OFF(armcpu_t *cpu) { { execute = FALSE; @@ -7081,7 +7081,7 @@ u32 FASTCALL OP_STC_P_IMM_OFF(armcpu_t *cpu) } } -u32 FASTCALL OP_STC_M_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STC_M_IMM_OFF(armcpu_t *cpu) { { execute = FALSE; @@ -7089,7 +7089,7 @@ u32 FASTCALL OP_STC_M_IMM_OFF(armcpu_t *cpu) } } -u32 FASTCALL OP_STC_P_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STC_P_PREIND(armcpu_t *cpu) { { execute = FALSE; @@ -7097,7 +7097,7 @@ u32 FASTCALL OP_STC_P_PREIND(armcpu_t *cpu) } } -u32 FASTCALL OP_STC_M_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_STC_M_PREIND(armcpu_t *cpu) { { execute = FALSE; @@ -7105,7 +7105,7 @@ u32 FASTCALL OP_STC_M_PREIND(armcpu_t *cpu) } } -u32 FASTCALL OP_STC_P_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STC_P_POSTIND(armcpu_t *cpu) { { execute = FALSE; @@ -7113,7 +7113,7 @@ u32 FASTCALL OP_STC_P_POSTIND(armcpu_t *cpu) } } -u32 FASTCALL OP_STC_M_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_STC_M_POSTIND(armcpu_t *cpu) { { execute = FALSE; @@ -7121,7 +7121,7 @@ u32 FASTCALL OP_STC_M_POSTIND(armcpu_t *cpu) } } -u32 FASTCALL OP_STC_OPTION(armcpu_t *cpu) +static u32 FASTCALL OP_STC_OPTION(armcpu_t *cpu) { { execute = FALSE; @@ -7131,7 +7131,7 @@ u32 FASTCALL OP_STC_OPTION(armcpu_t *cpu) //---------------------LDC---------------------------------- -u32 FASTCALL OP_LDC_P_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDC_P_IMM_OFF(armcpu_t *cpu) { { execute = FALSE; @@ -7139,7 +7139,7 @@ u32 FASTCALL OP_LDC_P_IMM_OFF(armcpu_t *cpu) } } -u32 FASTCALL OP_LDC_M_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDC_M_IMM_OFF(armcpu_t *cpu) { { execute = FALSE; @@ -7147,7 +7147,7 @@ u32 FASTCALL OP_LDC_M_IMM_OFF(armcpu_t *cpu) } } -u32 FASTCALL OP_LDC_P_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDC_P_PREIND(armcpu_t *cpu) { { execute = FALSE; @@ -7155,7 +7155,7 @@ u32 FASTCALL OP_LDC_P_PREIND(armcpu_t *cpu) } } -u32 FASTCALL OP_LDC_M_PREIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDC_M_PREIND(armcpu_t *cpu) { { execute = FALSE; @@ -7163,7 +7163,7 @@ u32 FASTCALL OP_LDC_M_PREIND(armcpu_t *cpu) } } -u32 FASTCALL OP_LDC_P_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDC_P_POSTIND(armcpu_t *cpu) { { execute = FALSE; @@ -7171,7 +7171,7 @@ u32 FASTCALL OP_LDC_P_POSTIND(armcpu_t *cpu) } } -u32 FASTCALL OP_LDC_M_POSTIND(armcpu_t *cpu) +static u32 FASTCALL OP_LDC_M_POSTIND(armcpu_t *cpu) { { execute = FALSE; @@ -7179,7 +7179,7 @@ u32 FASTCALL OP_LDC_M_POSTIND(armcpu_t *cpu) } } -u32 FASTCALL OP_LDC_OPTION(armcpu_t *cpu) +static u32 FASTCALL OP_LDC_OPTION(armcpu_t *cpu) { { execute = FALSE; @@ -7189,7 +7189,7 @@ u32 FASTCALL OP_LDC_OPTION(armcpu_t *cpu) //----------------MCR----------------------- -u32 FASTCALL OP_MCR(armcpu_t *cpu) +static u32 FASTCALL OP_MCR(armcpu_t *cpu) { u32 i = cpu->instruction; u32 cpnum = REG_POS(i, 8); @@ -7207,7 +7207,7 @@ u32 FASTCALL OP_MCR(armcpu_t *cpu) //----------------MRC----------------------- -u32 FASTCALL OP_MRC(armcpu_t *cpu) +static u32 FASTCALL OP_MRC(armcpu_t *cpu) { u32 i = cpu->instruction; u32 cpnum = REG_POS(i, 8); @@ -7224,14 +7224,14 @@ u32 FASTCALL OP_MRC(armcpu_t *cpu) } //--------------SWI------------------------------- -u32 FASTCALL OP_SWI(armcpu_t *cpu) +static u32 FASTCALL OP_SWI(armcpu_t *cpu) { u32 swinum = (cpu->instruction>>16)&0x1F; return cpu->swi_tab[swinum](cpu) + 3; } //----------------BKPT------------------------- -u32 FASTCALL OP_BKPT(armcpu_t *cpu) +static u32 FASTCALL OP_BKPT(armcpu_t *cpu) { execute = FALSE; return 4; @@ -7239,7 +7239,7 @@ u32 FASTCALL OP_BKPT(armcpu_t *cpu) //----------------CDP----------------------- -u32 FASTCALL OP_CDP(armcpu_t *cpu) +static u32 FASTCALL OP_CDP(armcpu_t *cpu) { execute = FALSE; return 4; diff --git a/desmume/src/thumb_instructions.c b/desmume/src/thumb_instructions.c index 728560570..3d240b943 100644 --- a/desmume/src/thumb_instructions.c +++ b/desmume/src/thumb_instructions.c @@ -27,13 +27,13 @@ extern BOOL execute; -u32 FASTCALL OP_UND_THUMB(armcpu_t *cpu) +static u32 FASTCALL OP_UND_THUMB(armcpu_t *cpu) { execute = FALSE; return 1; } -u32 FASTCALL OP_LSL_0(armcpu_t *cpu) +static u32 FASTCALL OP_LSL_0(armcpu_t *cpu) { u32 i = cpu->instruction; cpu->R[REG_NUM(i, 0)] = cpu->R[REG_NUM(i, 3)]; @@ -43,7 +43,7 @@ u32 FASTCALL OP_LSL_0(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_LSL(armcpu_t *cpu) +static u32 FASTCALL OP_LSL(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = (i>>6) & 0x1F; @@ -55,7 +55,7 @@ u32 FASTCALL OP_LSL(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_LSR_0(armcpu_t *cpu) +static u32 FASTCALL OP_LSR_0(armcpu_t *cpu) { u32 i = cpu->instruction; // cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 0)]); @@ -67,7 +67,7 @@ u32 FASTCALL OP_LSR_0(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_LSR(armcpu_t *cpu) +static u32 FASTCALL OP_LSR(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = (i>>6) & 0x1F; @@ -79,7 +79,7 @@ u32 FASTCALL OP_LSR(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_ASR_0(armcpu_t *cpu) +static u32 FASTCALL OP_ASR_0(armcpu_t *cpu) { u32 i = cpu->instruction; cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 3)]); @@ -90,7 +90,7 @@ u32 FASTCALL OP_ASR_0(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_ASR(armcpu_t *cpu) +static u32 FASTCALL OP_ASR(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = (i>>6) & 0x1F; @@ -102,7 +102,7 @@ u32 FASTCALL OP_ASR(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_ADD_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 a = cpu->R[REG_NUM(i, 3)]; @@ -116,7 +116,7 @@ u32 FASTCALL OP_ADD_REG(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_SUB_REG(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 a = cpu->R[REG_NUM(i, 3)]; @@ -130,7 +130,7 @@ u32 FASTCALL OP_SUB_REG(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_ADD_IMM3(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_IMM3(armcpu_t *cpu) { u32 i = cpu->instruction; u32 a = cpu->R[REG_NUM(i, 3)]; @@ -143,7 +143,7 @@ u32 FASTCALL OP_ADD_IMM3(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_SUB_IMM3(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_IMM3(armcpu_t *cpu) { u32 i = cpu->instruction; u32 a = cpu->R[REG_NUM(i, 3)]; @@ -156,7 +156,7 @@ u32 FASTCALL OP_SUB_IMM3(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_MOV_IMM8(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_IMM8(armcpu_t *cpu) { u32 i = cpu->instruction; cpu->R[REG_NUM(i, 8)] = i & 0xFF; @@ -166,7 +166,7 @@ u32 FASTCALL OP_MOV_IMM8(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_CMP_IMM8(armcpu_t *cpu) +static u32 FASTCALL OP_CMP_IMM8(armcpu_t *cpu) { u32 i = cpu->instruction; u32 tmp = cpu->R[REG_NUM(i, 8)] - (i & 0xFF); @@ -178,7 +178,7 @@ u32 FASTCALL OP_CMP_IMM8(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_ADD_IMM8(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_IMM8(armcpu_t *cpu) { u32 i = cpu->instruction; u32 tmp = cpu->R[REG_NUM(i, 8)] + (i & 0xFF); @@ -191,7 +191,7 @@ u32 FASTCALL OP_ADD_IMM8(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_SUB_IMM8(armcpu_t *cpu) +static u32 FASTCALL OP_SUB_IMM8(armcpu_t *cpu) { u32 i = cpu->instruction; u32 tmp = cpu->R[REG_NUM(i, 8)] - (i & 0xFF); @@ -204,7 +204,7 @@ u32 FASTCALL OP_SUB_IMM8(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_AND(armcpu_t *cpu) +static u32 FASTCALL OP_AND(armcpu_t *cpu) { u32 i = cpu->instruction; cpu->R[REG_NUM(i, 0)] &= cpu->R[REG_NUM(i, 3)]; @@ -214,7 +214,7 @@ u32 FASTCALL OP_AND(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_EOR(armcpu_t *cpu) +static u32 FASTCALL OP_EOR(armcpu_t *cpu) { u32 i = cpu->instruction; cpu->R[REG_NUM(i, 0)] ^= cpu->R[REG_NUM(i, 3)]; @@ -224,7 +224,7 @@ u32 FASTCALL OP_EOR(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_LSL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_LSL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_NUM(i, 3)]&0xFF; @@ -254,7 +254,7 @@ u32 FASTCALL OP_LSL_REG(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_LSR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_LSR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_NUM(i, 3)]&0xFF; @@ -284,7 +284,7 @@ u32 FASTCALL OP_LSR_REG(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_ASR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ASR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_NUM(i, 3)]&0xFF; @@ -312,7 +312,7 @@ u32 FASTCALL OP_ASR_REG(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_ADC_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ADC_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 a = cpu->R[REG_NUM(i, 0)]; @@ -331,7 +331,7 @@ u32 FASTCALL OP_ADC_REG(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_SBC_REG(armcpu_t *cpu) +static u32 FASTCALL OP_SBC_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 a = cpu->R[REG_NUM(i, 0)]; @@ -349,7 +349,7 @@ u32 FASTCALL OP_SBC_REG(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_ROR_REG(armcpu_t *cpu) +static u32 FASTCALL OP_ROR_REG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 v = cpu->R[REG_NUM(i, 3)]&0xFF; @@ -376,7 +376,7 @@ u32 FASTCALL OP_ROR_REG(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_TST(armcpu_t *cpu) +static u32 FASTCALL OP_TST(armcpu_t *cpu) { u32 i = cpu->instruction; u32 tmp = cpu->R[REG_NUM(i, 0)] & cpu->R[REG_NUM(i, 3)]; @@ -386,7 +386,7 @@ u32 FASTCALL OP_TST(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_NEG(armcpu_t *cpu) +static u32 FASTCALL OP_NEG(armcpu_t *cpu) { u32 i = cpu->instruction; u32 a = cpu->R[REG_NUM(i, 3)]; @@ -400,7 +400,7 @@ u32 FASTCALL OP_NEG(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_CMP(armcpu_t *cpu) +static u32 FASTCALL OP_CMP(armcpu_t *cpu) { u32 i = cpu->instruction; u32 tmp = cpu->R[REG_NUM(i, 0)] -cpu->R[REG_NUM(i, 3)]; @@ -413,7 +413,7 @@ u32 FASTCALL OP_CMP(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_CMN(armcpu_t *cpu) +static u32 FASTCALL OP_CMN(armcpu_t *cpu) { u32 i = cpu->instruction; u32 tmp = cpu->R[REG_NUM(i, 0)] + cpu->R[REG_NUM(i, 3)]; @@ -428,7 +428,7 @@ u32 FASTCALL OP_CMN(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_ORR(armcpu_t *cpu) +static u32 FASTCALL OP_ORR(armcpu_t *cpu) { u32 i = cpu->instruction; cpu->R[REG_NUM(i, 0)] |= cpu->R[REG_NUM(i, 3)]; @@ -438,7 +438,7 @@ u32 FASTCALL OP_ORR(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_MUL_REG(armcpu_t *cpu) +static u32 FASTCALL OP_MUL_REG(armcpu_t *cpu) { u32 i = cpu->instruction; cpu->R[REG_NUM(i, 0)] *= cpu->R[REG_NUM(i, 3)]; @@ -448,7 +448,7 @@ u32 FASTCALL OP_MUL_REG(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_BIC(armcpu_t *cpu) +static u32 FASTCALL OP_BIC(armcpu_t *cpu) { u32 i = cpu->instruction; cpu->R[REG_NUM(i, 0)] &= (~cpu->R[REG_NUM(i, 3)]); @@ -458,7 +458,7 @@ u32 FASTCALL OP_BIC(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_MVN(armcpu_t *cpu) +static u32 FASTCALL OP_MVN(armcpu_t *cpu) { u32 i = cpu->instruction; cpu->R[REG_NUM(i, 0)] = (~cpu->R[REG_NUM(i, 3)]); @@ -468,7 +468,7 @@ u32 FASTCALL OP_MVN(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_ADD_SPE(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_SPE(armcpu_t *cpu) { u32 i = cpu->instruction; u8 Rd = (i&7) | ((i>>4)&8); @@ -480,7 +480,7 @@ u32 FASTCALL OP_ADD_SPE(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_CMP_SPE(armcpu_t *cpu) +static u32 FASTCALL OP_CMP_SPE(armcpu_t *cpu) { u32 i = cpu->instruction; u8 Rn = (i&7) | ((i>>4)&8); @@ -494,7 +494,7 @@ u32 FASTCALL OP_CMP_SPE(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_MOV_SPE(armcpu_t *cpu) +static u32 FASTCALL OP_MOV_SPE(armcpu_t *cpu) { u32 i = cpu->instruction; u8 Rd = (i&7) | ((i>>4)&8); @@ -506,7 +506,7 @@ u32 FASTCALL OP_MOV_SPE(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_BX_THUMB(armcpu_t *cpu) +static u32 FASTCALL OP_BX_THUMB(armcpu_t *cpu) { u32 Rm = cpu->R[REG_POS(cpu->instruction, 3)]; @@ -517,7 +517,7 @@ u32 FASTCALL OP_BX_THUMB(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_BLX_THUMB(armcpu_t *cpu) +static u32 FASTCALL OP_BLX_THUMB(armcpu_t *cpu) { u32 Rm = cpu->R[REG_POS(cpu->instruction, 3)]; @@ -529,7 +529,7 @@ u32 FASTCALL OP_BLX_THUMB(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_LDR_PCREL(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_PCREL(armcpu_t *cpu) { u32 adr = (cpu->R[15]&0xFFFFFFFC) + ((cpu->instruction&0xFF)<<2); @@ -538,7 +538,7 @@ u32 FASTCALL OP_LDR_PCREL(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STR_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 6)] + cpu->R[REG_NUM(i, 3)]; @@ -547,7 +547,7 @@ u32 FASTCALL OP_STR_REG_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRH_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRH_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; @@ -556,7 +556,7 @@ u32 FASTCALL OP_STRH_REG_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; @@ -565,7 +565,7 @@ u32 FASTCALL OP_STRB_REG_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSB_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSB_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; @@ -574,7 +574,7 @@ u32 FASTCALL OP_LDRSB_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; @@ -583,7 +583,7 @@ u32 FASTCALL OP_LDR_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRH_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRH_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; @@ -592,7 +592,7 @@ u32 FASTCALL OP_LDRH_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; @@ -601,7 +601,7 @@ u32 FASTCALL OP_LDRB_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRSH_REG_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRSH_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; @@ -610,7 +610,7 @@ u32 FASTCALL OP_LDRSH_REG_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C); @@ -619,7 +619,7 @@ u32 FASTCALL OP_STR_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C); @@ -628,7 +628,7 @@ u32 FASTCALL OP_LDR_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRB_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRB_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F); @@ -637,7 +637,7 @@ u32 FASTCALL OP_STRB_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRB_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRB_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F); @@ -646,7 +646,7 @@ u32 FASTCALL OP_LDRB_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STRH_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_STRH_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E); @@ -655,7 +655,7 @@ u32 FASTCALL OP_STRH_IMM_OFF(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDRH_IMM_OFF(armcpu_t *cpu) +static u32 FASTCALL OP_LDRH_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E); @@ -664,7 +664,7 @@ u32 FASTCALL OP_LDRH_IMM_OFF(armcpu_t *cpu) return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_STR_SPREL(armcpu_t *cpu) +static u32 FASTCALL OP_STR_SPREL(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[13] + ((i&0xFF)<<2); @@ -673,7 +673,7 @@ u32 FASTCALL OP_STR_SPREL(armcpu_t *cpu) return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_LDR_SPREL(armcpu_t *cpu) +static u32 FASTCALL OP_LDR_SPREL(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[13] + ((i&0xFF)<<2); @@ -682,7 +682,7 @@ u32 FASTCALL OP_LDR_SPREL(armcpu_t *cpu) return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } -u32 FASTCALL OP_ADD_2PC(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_2PC(armcpu_t *cpu) { u32 i = cpu->instruction; cpu->R[REG_NUM(i, 8)] = (cpu->R[15]&0xFFFFFFFC) + ((i&0xFF)<<2); @@ -690,7 +690,7 @@ u32 FASTCALL OP_ADD_2PC(armcpu_t *cpu) return 5; } -u32 FASTCALL OP_ADD_2SP(armcpu_t *cpu) +static u32 FASTCALL OP_ADD_2SP(armcpu_t *cpu) { u32 i = cpu->instruction; cpu->R[REG_NUM(i, 8)] = cpu->R[13] + ((i&0xFF)<<2); @@ -698,21 +698,21 @@ u32 FASTCALL OP_ADD_2SP(armcpu_t *cpu) return 2; } -u32 FASTCALL OP_ADJUST_P_SP(armcpu_t *cpu) +static u32 FASTCALL OP_ADJUST_P_SP(armcpu_t *cpu) { cpu->R[13] += ((cpu->instruction&0x7F)<<2); return 1; } -u32 FASTCALL OP_ADJUST_M_SP(armcpu_t *cpu) +static u32 FASTCALL OP_ADJUST_M_SP(armcpu_t *cpu) { cpu->R[13] -= ((cpu->instruction&0x7F)<<2); return 1; } -u32 FASTCALL OP_PUSH(armcpu_t *cpu) +static u32 FASTCALL OP_PUSH(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[13] - 4; @@ -731,7 +731,7 @@ u32 FASTCALL OP_PUSH(armcpu_t *cpu) return c + 3; } -u32 FASTCALL OP_PUSH_LR(armcpu_t *cpu) +static u32 FASTCALL OP_PUSH_LR(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[13] - 4; @@ -754,7 +754,7 @@ u32 FASTCALL OP_PUSH_LR(armcpu_t *cpu) return c + 4; } -u32 FASTCALL OP_POP(armcpu_t *cpu) +static u32 FASTCALL OP_POP(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[13]; @@ -773,7 +773,7 @@ u32 FASTCALL OP_POP(armcpu_t *cpu) return c + 2; } -u32 FASTCALL OP_POP_PC(armcpu_t *cpu) +static u32 FASTCALL OP_POP_PC(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[13]; @@ -800,12 +800,12 @@ u32 FASTCALL OP_POP_PC(armcpu_t *cpu) return c + 5; } -u32 FASTCALL OP_BKPT_THUMB(armcpu_t *cpu) +static u32 FASTCALL OP_BKPT_THUMB(armcpu_t *cpu) { return 1; } -u32 FASTCALL OP_STMIA_THUMB(armcpu_t *cpu) +static u32 FASTCALL OP_STMIA_THUMB(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 8)]; @@ -823,7 +823,7 @@ u32 FASTCALL OP_STMIA_THUMB(armcpu_t *cpu) return c + 2; } -u32 FASTCALL OP_LDMIA_THUMB(armcpu_t *cpu) +static u32 FASTCALL OP_LDMIA_THUMB(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 8)]; @@ -841,7 +841,7 @@ u32 FASTCALL OP_LDMIA_THUMB(armcpu_t *cpu) return c + 3; } -u32 FASTCALL OP_B_COND(armcpu_t *cpu) +static u32 FASTCALL OP_B_COND(armcpu_t *cpu) { u32 i = cpu->instruction; if(!TEST_COND((i>>8)&0xF, cpu->CPSR)) @@ -852,7 +852,7 @@ u32 FASTCALL OP_B_COND(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_SWI_THUMB(armcpu_t *cpu) +static u32 FASTCALL OP_SWI_THUMB(armcpu_t *cpu) { u32 swinum = cpu->instruction & 0xFF; return cpu->swi_tab[swinum](cpu) + 3; @@ -861,7 +861,7 @@ u32 FASTCALL OP_SWI_THUMB(armcpu_t *cpu) #define SIGNEEXT_IMM11(i) (((i)&0x7FF) | (BIT10(i) * 0xFFFFF800)) -u32 FASTCALL OP_B_UNCOND(armcpu_t *cpu) +static u32 FASTCALL OP_B_UNCOND(armcpu_t *cpu) { u32 i = cpu->instruction; cpu->R[15] += (SIGNEEXT_IMM11(i)<<1); @@ -869,7 +869,7 @@ u32 FASTCALL OP_B_UNCOND(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_BLX(armcpu_t *cpu) +static u32 FASTCALL OP_BLX(armcpu_t *cpu) { u32 i = cpu->instruction; cpu->R[15] = (cpu->R[14] + ((i&0x7FF)<<1))&0xFFFFFFFC; @@ -879,14 +879,14 @@ u32 FASTCALL OP_BLX(armcpu_t *cpu) return 3; } -u32 FASTCALL OP_BL_10(armcpu_t *cpu) +static u32 FASTCALL OP_BL_10(armcpu_t *cpu) { u32 i = cpu->instruction; cpu->R[14] = cpu->R[15] + (SIGNEEXT_IMM11(i)<<12); return 1; } -u32 FASTCALL OP_BL_THUMB(armcpu_t *cpu) +static u32 FASTCALL OP_BL_THUMB(armcpu_t *cpu) { u32 i = cpu->instruction; cpu->R[15] = (cpu->R[14] + ((i&0x7FF)<<1));