From ab61e64ac2969fa743d63919c20c049848cb3aac Mon Sep 17 00:00:00 2001 From: zeromus Date: Tue, 15 Sep 2009 06:20:09 +0000 Subject: [PATCH] unhook all emulation of STRBT and LDRBT which were confusingly only half emulated; I think that they shouldn't be emulated at all. someone prove me wrong. also, fix the FORCEINLINE macro on gcc to do something approximating its intent. maybe it doesn't work on old gccs and we'll have to change it back or conditionalize it differently. --- desmume/src/arm_instructions.cpp | 1146 ++++++++++++++-------------- desmume/src/instruction_tabdef.inc | 192 ++--- desmume/src/types.h | 2 +- 3 files changed, 670 insertions(+), 670 deletions(-) diff --git a/desmume/src/arm_instructions.cpp b/desmume/src/arm_instructions.cpp index d4dadfd81..e0167a061 100644 --- a/desmume/src/arm_instructions.cpp +++ b/desmume/src/arm_instructions.cpp @@ -5705,579 +5705,579 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND() return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } -//-----------------------LDRBT------------------------------------- - -TEMPLATE static u32 FASTCALL OP_LDRBT_P_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - - if(cpu->CPSR.bits.mode==USR) - return 2; - oldmode = armcpu_switchMode(cpu, SYS); - - i = cpu->instruction; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_M_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - - if(cpu->CPSR.bits.mode==USR) - return 2; - oldmode = armcpu_switchMode(cpu, SYS); - - UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_M_IMM_OFF_POSTIND\n"); - - i = cpu->instruction; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_P_REG_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_P_REG_OFF_POSTIND\n"); - - i = cpu->instruction; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr + cpu->R[REG_POS(i,0)]; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_P_LSL_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - oldmode = armcpu_switchMode(cpu, SYS); - - UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_P_LSL_IMM_OFF_POSTIND\n"); - - i = cpu->instruction; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr + shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_M_LSL_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_M_LSL_IMM_OFF_POSTIND\n"); - - i = cpu->instruction; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr - shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_P_LSR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_P_LSR_IMM_OFF_POSTIND\n"); - - i = cpu->instruction; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr + shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_M_LSR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_M_LSR_IMM_OFF_POSTIND\n"); - - i = cpu->instruction; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr - shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_P_ASR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_P_ASR_IMM_OFF_POSTIND\n"); - - - i = cpu->instruction; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr + shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_M_ASR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_M_ASR_IMM_OFF_POSTIND\n"); - - - i = cpu->instruction; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr - shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_P_ROR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_P_ROR_IMM_OFF_POSTIND\n"); - - - i = cpu->instruction; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr + shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_M_ROR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_M_ROR_IMM_OFF_POSTIND\n"); - - - i = cpu->instruction; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr - shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -//----------------------STRBT---------------------------- - -TEMPLATE static u32 FASTCALL OP_STRBT_P_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_M_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_P_REG_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + cpu->R[REG_POS(i,0)]; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_M_REG_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - cpu->R[REG_POS(i,0)]; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_P_LSL_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_M_LSL_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_P_LSR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_M_LSR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_P_ASR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_M_ASR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_P_ROR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_M_ROR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} +////-----------------------LDRBT------------------------------------- +// +//TEMPLATE static u32 FASTCALL OP_LDRBT_P_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 val; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// oldmode = armcpu_switchMode(cpu, SYS); +// +// i = cpu->instruction; +// adr = cpu->R[REG_POS(i,16)]; +// val = READ8(cpu->mem_if->data, adr); +// cpu->R[REG_POS(i,12)] = val; +// cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_LDRBT_M_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 val; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// oldmode = armcpu_switchMode(cpu, SYS); +// +// UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_M_IMM_OFF_POSTIND\n"); +// +// i = cpu->instruction; +// adr = cpu->R[REG_POS(i,16)]; +// val = READ8(cpu->mem_if->data, adr); +// cpu->R[REG_POS(i,12)] = val; +// cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_LDRBT_P_REG_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 val; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_P_REG_OFF_POSTIND\n"); +// +// i = cpu->instruction; +// adr = cpu->R[REG_POS(i,16)]; +// val = READ8(cpu->mem_if->data, adr); +// cpu->R[REG_POS(i,12)] = val; +// cpu->R[REG_POS(i,16)] = adr + cpu->R[REG_POS(i,0)]; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_LDRBT_P_LSL_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 val; +// u32 shift_op; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// oldmode = armcpu_switchMode(cpu, SYS); +// +// UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_P_LSL_IMM_OFF_POSTIND\n"); +// +// i = cpu->instruction; +// LSL_IMM; +// adr = cpu->R[REG_POS(i,16)]; +// val = READ8(cpu->mem_if->data, adr); +// cpu->R[REG_POS(i,12)] = val; +// cpu->R[REG_POS(i,16)] = adr + shift_op; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_LDRBT_M_LSL_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 val; +// u32 shift_op; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_M_LSL_IMM_OFF_POSTIND\n"); +// +// i = cpu->instruction; +// LSL_IMM; +// adr = cpu->R[REG_POS(i,16)]; +// val = READ8(cpu->mem_if->data, adr); +// cpu->R[REG_POS(i,12)] = val; +// cpu->R[REG_POS(i,16)] = adr - shift_op; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_LDRBT_P_LSR_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 val; +// u32 shift_op; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_P_LSR_IMM_OFF_POSTIND\n"); +// +// i = cpu->instruction; +// LSR_IMM; +// adr = cpu->R[REG_POS(i,16)]; +// val = READ8(cpu->mem_if->data, adr); +// cpu->R[REG_POS(i,12)] = val; +// cpu->R[REG_POS(i,16)] = adr + shift_op; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_LDRBT_M_LSR_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 val; +// u32 shift_op; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_M_LSR_IMM_OFF_POSTIND\n"); +// +// i = cpu->instruction; +// LSR_IMM; +// adr = cpu->R[REG_POS(i,16)]; +// val = READ8(cpu->mem_if->data, adr); +// cpu->R[REG_POS(i,12)] = val; +// cpu->R[REG_POS(i,16)] = adr - shift_op; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_LDRBT_P_ASR_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 val; +// u32 shift_op; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_P_ASR_IMM_OFF_POSTIND\n"); +// +// +// i = cpu->instruction; +// ASR_IMM; +// adr = cpu->R[REG_POS(i,16)]; +// val = READ8(cpu->mem_if->data, adr); +// cpu->R[REG_POS(i,12)] = val; +// cpu->R[REG_POS(i,16)] = adr + shift_op; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_LDRBT_M_ASR_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 val; +// u32 shift_op; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_M_ASR_IMM_OFF_POSTIND\n"); +// +// +// i = cpu->instruction; +// ASR_IMM; +// adr = cpu->R[REG_POS(i,16)]; +// val = READ8(cpu->mem_if->data, adr); +// cpu->R[REG_POS(i,12)] = val; +// cpu->R[REG_POS(i,16)] = adr - shift_op; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_LDRBT_P_ROR_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 val; +// u32 shift_op; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_P_ROR_IMM_OFF_POSTIND\n"); +// +// +// i = cpu->instruction; +// ROR_IMM; +// adr = cpu->R[REG_POS(i,16)]; +// val = READ8(cpu->mem_if->data, adr); +// cpu->R[REG_POS(i,12)] = val; +// cpu->R[REG_POS(i,16)] = adr + shift_op; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_LDRBT_M_ROR_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 val; +// u32 shift_op; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// UNTESTEDOPCODELOG("Untested opcode: OP_LDRBT_M_ROR_IMM_OFF_POSTIND\n"); +// +// +// i = cpu->instruction; +// ROR_IMM; +// adr = cpu->R[REG_POS(i,16)]; +// val = READ8(cpu->mem_if->data, adr); +// cpu->R[REG_POS(i,12)] = val; +// cpu->R[REG_POS(i,16)] = adr - shift_op; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +////----------------------STRBT---------------------------- +// +//TEMPLATE static u32 FASTCALL OP_STRBT_P_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// +// i = cpu->instruction; +// adr = cpu->R[REG_POS(i,16)]; +// WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); +// cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_STRBT_M_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// +// i = cpu->instruction; +// adr = cpu->R[REG_POS(i,16)]; +// WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); +// cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_STRBT_P_REG_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// +// i = cpu->instruction; +// adr = cpu->R[REG_POS(i,16)]; +// WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); +// cpu->R[REG_POS(i,16)] = adr + cpu->R[REG_POS(i,0)]; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_STRBT_M_REG_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// +// i = cpu->instruction; +// adr = cpu->R[REG_POS(i,16)]; +// WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); +// cpu->R[REG_POS(i,16)] = adr - cpu->R[REG_POS(i,0)]; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_STRBT_P_LSL_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 shift_op; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// +// i = cpu->instruction; +// LSL_IMM; +// adr = cpu->R[REG_POS(i,16)]; +// WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); +// cpu->R[REG_POS(i,16)] = adr + shift_op; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_STRBT_M_LSL_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 shift_op; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// +// i = cpu->instruction; +// LSL_IMM; +// adr = cpu->R[REG_POS(i,16)]; +// WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); +// cpu->R[REG_POS(i,16)] = adr - shift_op; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_STRBT_P_LSR_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 shift_op; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// +// i = cpu->instruction; +// LSR_IMM; +// adr = cpu->R[REG_POS(i,16)]; +// WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); +// cpu->R[REG_POS(i,16)] = adr + shift_op; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_STRBT_M_LSR_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 shift_op; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// +// i = cpu->instruction; +// LSR_IMM; +// adr = cpu->R[REG_POS(i,16)]; +// WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); +// cpu->R[REG_POS(i,16)] = adr - shift_op; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_STRBT_P_ASR_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 shift_op; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// +// i = cpu->instruction; +// ASR_IMM; +// adr = cpu->R[REG_POS(i,16)]; +// WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); +// cpu->R[REG_POS(i,16)] = adr + shift_op; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_STRBT_M_ASR_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 shift_op; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// +// i = cpu->instruction; +// ASR_IMM; +// adr = cpu->R[REG_POS(i,16)]; +// WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); +// cpu->R[REG_POS(i,16)] = adr - shift_op; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_STRBT_P_ROR_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 shift_op; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// +// i = cpu->instruction; +// ROR_IMM; +// adr = cpu->R[REG_POS(i,16)]; +// WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); +// cpu->R[REG_POS(i,16)] = adr + shift_op; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} +// +//TEMPLATE static u32 FASTCALL OP_STRBT_M_ROR_IMM_OFF_POSTIND() +//{ +// u32 oldmode; +// u32 i; +// u32 adr; +// u32 shift_op; +// +// if(cpu->CPSR.bits.mode==USR) +// return 2; +// +// oldmode = armcpu_switchMode(cpu, SYS); +// +// +// i = cpu->instruction; +// ROR_IMM; +// adr = cpu->R[REG_POS(i,16)]; +// WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); +// cpu->R[REG_POS(i,16)] = adr - shift_op; +// +// armcpu_switchMode(cpu, oldmode); +// +// return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +//} //---------------------LDM----------------------------- diff --git a/desmume/src/instruction_tabdef.inc b/desmume/src/instruction_tabdef.inc index 45eac2813..503734de2 100644 --- a/desmume/src/instruction_tabdef.inc +++ b/desmume/src/instruction_tabdef.inc @@ -1265,39 +1265,39 @@ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND), //010 0010 1 1101 TABDECL( OP_LDRB_M_IMM_OFF_POSTIND), //010 0010 1 1110 TABDECL( OP_LDRB_M_IMM_OFF_POSTIND), //010 0010 1 1111 //------------------------------------------ -TABDECL( OP_STRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_STRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_STRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_STRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_STRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_STRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_STRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_STRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_STRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_STRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_STRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_STRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_STRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_STRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_STRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_STRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 -TABDECL( OP_LDRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_LDRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_LDRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_LDRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_LDRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_LDRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_LDRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_LDRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_LDRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_LDRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_LDRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_LDRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_LDRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_LDRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_LDRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 -TABDECL( OP_LDRBT_M_IMM_OFF_POSTIND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 +TABDECL( OP_UND), //010 0011 0 0000 //------------------------------------------ TABDECL( OP_STR_P_IMM_OFF_POSTIND), //010 0100 0 0000 TABDECL( OP_STR_P_IMM_OFF_POSTIND), //010 0100 0 0000 @@ -1401,39 +1401,39 @@ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND), //010 0100 0 0000 TABDECL( OP_LDRB_P_IMM_OFF_POSTIND), //010 0100 0 0000 TABDECL( OP_LDRB_P_IMM_OFF_POSTIND), //010 0110 1 1111 //------------------------------------------ -TABDECL( OP_STRBT_P_IMM_OFF_POSTIND), //010 0111 0 0000 -TABDECL( OP_STRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_STRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_STRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_STRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_STRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_STRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_STRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_STRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_STRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_STRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_STRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_STRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_STRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_STRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_STRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0111 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 -TABDECL( OP_LDRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_LDRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_LDRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_LDRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_LDRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_LDRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_LDRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_LDRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_LDRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_LDRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_LDRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_LDRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_LDRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_LDRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_LDRBT_P_IMM_OFF_POSTIND), //010 0100 0 0000 -TABDECL( OP_LDRBT_P_IMM_OFF_POSTIND), //010 0111 1 1111 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0100 0 0000 +TABDECL( OP_UND), //010 0111 1 1111 //------------------------------------------ TABDECL( OP_STR_M_IMM_OFF), //010 1000 0 0000 TABDECL( OP_STR_M_IMM_OFF), @@ -1808,38 +1808,38 @@ TABDECL( OP_UND), TABDECL( OP_LDRB_M_ROR_IMM_OFF_POSTIND), TABDECL( OP_UND), //011 0010 1 1111 //------------------------------------------ -TABDECL( OP_STRBT_M_LSL_IMM_OFF_POSTIND), //011 0011 0 0000 +TABDECL( OP_UND), //011 0011 0 0000 +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), TABDECL( OP_UND), -TABDECL( OP_STRBT_M_LSR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_STRBT_M_ASR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_STRBT_M_ROR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_STRBT_M_LSL_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_STRBT_M_LSR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_STRBT_M_ASR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_STRBT_M_ROR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_LDRBT_M_LSL_IMM_OFF_POSTIND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), TABDECL( OP_UND), -TABDECL( OP_LDRBT_M_LSR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_LDRBT_M_ASR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_LDRBT_M_ROR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_LDRBT_M_LSL_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_LDRBT_M_LSR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_LDRBT_M_ASR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_LDRBT_M_ROR_IMM_OFF_POSTIND), TABDECL( OP_UND), //011 0011 1 1111 //------------------------------------------ TABDECL( OP_STR_P_LSL_IMM_OFF_POSTIND), //011 0100 0 0000 @@ -1944,38 +1944,38 @@ TABDECL( OP_UND), TABDECL( OP_LDRB_P_ROR_IMM_OFF_POSTIND), TABDECL( OP_UND), //------------------------------------------ -TABDECL( OP_STRBT_P_LSL_IMM_OFF_POSTIND), //011 0111 0 0000 +TABDECL( OP_UND), //011 0111 0 0000 //0x6E0 +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), TABDECL( OP_UND), -TABDECL( OP_STRBT_P_LSR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_STRBT_P_ASR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_STRBT_P_ROR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_STRBT_P_LSL_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_STRBT_P_LSR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_STRBT_P_ASR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_STRBT_P_ROR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_LDRBT_P_LSL_IMM_OFF_POSTIND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), +TABDECL( OP_UND), TABDECL( OP_UND), -TABDECL( OP_LDRBT_P_LSR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_LDRBT_P_ASR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_LDRBT_P_ROR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_LDRBT_P_LSL_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_LDRBT_P_LSR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_LDRBT_P_ASR_IMM_OFF_POSTIND), TABDECL( OP_UND), -TABDECL( OP_LDRBT_P_ROR_IMM_OFF_POSTIND), TABDECL( OP_UND), //------------------------------------------ TABDECL( OP_STR_M_LSL_IMM_OFF), //011 1000 0 0000 diff --git a/desmume/src/types.h b/desmume/src/types.h index 8c5c49324..27c6e28f6 100644 --- a/desmume/src/types.h +++ b/desmume/src/types.h @@ -96,7 +96,7 @@ #define FORCEINLINE __forceinline #define MSC_FORCEINLINE __forceinline #else -#define FORCEINLINE INLINE +#define FORCEINLINE inline __attribute__((always_inline)) #define MSC_FORCEINLINE #endif #endif