From a80fa6d4ded74f9cb6712d3ce591dc44b912f6e4 Mon Sep 17 00:00:00 2001 From: rogerman Date: Tue, 13 Dec 2016 14:31:45 -0800 Subject: [PATCH] MMU: Only report writing to undefined registers when the value being written is non-zero. --- desmume/src/MMU.cpp | 90 +++++++++++++++++++++++++-------------------- 1 file changed, 50 insertions(+), 40 deletions(-) diff --git a/desmume/src/MMU.cpp b/desmume/src/MMU.cpp index eea359f4a..d26ea0b4a 100644 --- a/desmume/src/MMU.cpp +++ b/desmume/src/MMU.cpp @@ -2694,10 +2694,15 @@ bool validateIORegsWrite(u32 addr, u8 size, u32 val) return true; default: + { #ifdef DEVELOPER - printf("MMU9 write%02d to undefined register %08Xh = %08Xh (PC:%08X)\n", size, addr, val, ARMPROC.instruct_adr); + if (val != 0) + { + printf("MMU9 write%02d to undefined register %08Xh = %08Xh (PC:%08X)\n", size, addr, val, ARMPROC.instruct_adr); + } #endif return false; + } } } @@ -2790,10 +2795,15 @@ bool validateIORegsWrite(u32 addr, u8 size, u32 val) return true; default: + { #ifdef DEVELOPER - printf("MMU7 write%02d to undefined register %08Xh = %08Xh (PC:%08X)\n", size, addr, val, ARMPROC.instruct_adr); + if (val != 0) + { + printf("MMU7 write%02d to undefined register %08Xh = %08Xh (PC:%08X)\n", size, addr, val, ARMPROC.instruct_adr); + } #endif return false; + } } } @@ -4846,22 +4856,22 @@ u8 FASTCALL _MMU_ARM9_read08(u32 adr) case eng_3D_GXSTAT: return MMU_new.gxstat.read(8,adr); - case REG_TM0CNTL+0: return _MMU_ARM9_read16(adr); - case REG_TM0CNTL+1: return _MMU_ARM9_read16(adr-1)>>8; - case REG_TM0CNTL+2: return _MMU_ARM9_read16(adr); - case REG_TM0CNTL+3: return _MMU_ARM9_read16(adr-1)>>8; - case REG_TM1CNTL+0: return _MMU_ARM9_read16(adr); - case REG_TM1CNTL+1: return _MMU_ARM9_read16(adr-1)>>8; - case REG_TM1CNTL+2: return _MMU_ARM9_read16(adr); - case REG_TM1CNTL+3: return _MMU_ARM9_read16(adr-1)>>8; - case REG_TM2CNTL+0: return _MMU_ARM9_read16(adr); - case REG_TM2CNTL+1: return _MMU_ARM9_read16(adr-1)>>8; - case REG_TM2CNTL+2: return _MMU_ARM9_read16(adr); - case REG_TM2CNTL+3: return _MMU_ARM9_read16(adr-1)>>8; - case REG_TM3CNTL+0: return _MMU_ARM9_read16(adr); - case REG_TM3CNTL+1: return _MMU_ARM9_read16(adr-1)>>8; - case REG_TM3CNTL+2: return _MMU_ARM9_read16(adr); - case REG_TM3CNTL+3: return _MMU_ARM9_read16(adr-1)>>8; + case REG_TM0CNTL+0: return _MMU_ARM9_read16(adr); + case REG_TM0CNTL+1: return _MMU_ARM9_read16(adr-1)>>8; + case REG_TM0CNTL+2: return _MMU_ARM9_read16(adr); + case REG_TM0CNTL+3: return _MMU_ARM9_read16(adr-1)>>8; + case REG_TM1CNTL+0: return _MMU_ARM9_read16(adr); + case REG_TM1CNTL+1: return _MMU_ARM9_read16(adr-1)>>8; + case REG_TM1CNTL+2: return _MMU_ARM9_read16(adr); + case REG_TM1CNTL+3: return _MMU_ARM9_read16(adr-1)>>8; + case REG_TM2CNTL+0: return _MMU_ARM9_read16(adr); + case REG_TM2CNTL+1: return _MMU_ARM9_read16(adr-1)>>8; + case REG_TM2CNTL+2: return _MMU_ARM9_read16(adr); + case REG_TM2CNTL+3: return _MMU_ARM9_read16(adr-1)>>8; + case REG_TM3CNTL+0: return _MMU_ARM9_read16(adr); + case REG_TM3CNTL+1: return _MMU_ARM9_read16(adr-1)>>8; + case REG_TM3CNTL+2: return _MMU_ARM9_read16(adr); + case REG_TM3CNTL+3: return _MMU_ARM9_read16(adr-1)>>8; case REG_KEYINPUT: LagFrameFlag=0; @@ -5584,21 +5594,21 @@ u8 FASTCALL _MMU_ARM7_read08(u32 adr) case REG_WRAMSTAT: return MMU.WRAMCNT; - case REG_TM0CNTL+0: return _MMU_ARM7_read16(adr); - case REG_TM0CNTL+1: return _MMU_ARM7_read16(adr-1)>>8; - case REG_TM0CNTL+2: return _MMU_ARM7_read16(adr); - case REG_TM0CNTL+3: return _MMU_ARM7_read16(adr-1)>>8; - case REG_TM1CNTL+0: return _MMU_ARM7_read16(adr); - case REG_TM1CNTL+1: return _MMU_ARM7_read16(adr-1)>>8; - case REG_TM1CNTL+2: return _MMU_ARM7_read16(adr); - case REG_TM1CNTL+3: return _MMU_ARM7_read16(adr-1)>>8; - case REG_TM2CNTL+0: return _MMU_ARM7_read16(adr); - case REG_TM2CNTL+1: return _MMU_ARM7_read16(adr-1)>>8; - case REG_TM2CNTL+2: return _MMU_ARM7_read16(adr); - case REG_TM2CNTL+3: return _MMU_ARM7_read16(adr-1)>>8; - case REG_TM3CNTL+0: return _MMU_ARM7_read16(adr); - case REG_TM3CNTL+1: return _MMU_ARM7_read16(adr-1)>>8; - case REG_TM3CNTL+2: return _MMU_ARM7_read16(adr); + case REG_TM0CNTL+0: return _MMU_ARM7_read16(adr); + case REG_TM0CNTL+1: return _MMU_ARM7_read16(adr-1)>>8; + case REG_TM0CNTL+2: return _MMU_ARM7_read16(adr); + case REG_TM0CNTL+3: return _MMU_ARM7_read16(adr-1)>>8; + case REG_TM1CNTL+0: return _MMU_ARM7_read16(adr); + case REG_TM1CNTL+1: return _MMU_ARM7_read16(adr-1)>>8; + case REG_TM1CNTL+2: return _MMU_ARM7_read16(adr); + case REG_TM1CNTL+3: return _MMU_ARM7_read16(adr-1)>>8; + case REG_TM2CNTL+0: return _MMU_ARM7_read16(adr); + case REG_TM2CNTL+1: return _MMU_ARM7_read16(adr-1)>>8; + case REG_TM2CNTL+2: return _MMU_ARM7_read16(adr); + case REG_TM2CNTL+3: return _MMU_ARM7_read16(adr-1)>>8; + case REG_TM3CNTL+0: return _MMU_ARM7_read16(adr); + case REG_TM3CNTL+1: return _MMU_ARM7_read16(adr-1)>>8; + case REG_TM3CNTL+2: return _MMU_ARM7_read16(adr); case REG_TM3CNTL+3: return _MMU_ARM7_read16(adr-1)>>8; } @@ -5747,13 +5757,13 @@ u32 FASTCALL _MMU_ARM7_read32(u32 adr) case REG_IPCFIFORECV : return IPC_FIFOrecv(ARMCPU_ARM7); - case REG_TM0CNTL : - case REG_TM1CNTL : - case REG_TM2CNTL : - case REG_TM3CNTL : - { - u32 hi = T1ReadWord(MMU.ARM9_REG, (adr + 2) & 0xFF); - return (hi<<16)|read_timer(ARMCPU_ARM9,(adr&0xF)>>2); + case REG_TM0CNTL : + case REG_TM1CNTL : + case REG_TM2CNTL : + case REG_TM3CNTL : + { + u32 hi = T1ReadWord(MMU.ARM9_REG, (adr + 2) & 0xFF); + return (hi<<16)|read_timer(ARMCPU_ARM9,(adr&0xF)>>2); } //case REG_GCROMCTRL: