From 85615190d6331f4a4269d77e061b107d3eaec10c Mon Sep 17 00:00:00 2001 From: shashclp Date: Sun, 2 Mar 2008 23:32:42 +0000 Subject: [PATCH] - Removed "execute=FALSE" and added logging instead, so games don't freeze but we still know that those opcode implementations might be faulty --- desmume/src/arm_instructions.c | 57 +++++++++++++++++++++++----------- 1 file changed, 39 insertions(+), 18 deletions(-) diff --git a/desmume/src/arm_instructions.c b/desmume/src/arm_instructions.c index dd978d600..40418c733 100644 --- a/desmume/src/arm_instructions.c +++ b/desmume/src/arm_instructions.c @@ -5861,7 +5861,9 @@ static u32 FASTCALL OP_LDRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu) if(cpu->CPSR.bits.mode==USR) return 2; oldmode = armcpu_switchMode(cpu, SYS); - execute = FALSE; + + //execute = FALSE; + LOG("Untested opcode: OP_LDRBT_M_IMM_OFF_POSTIND\n"); i = cpu->instruction; @@ -5886,7 +5888,8 @@ static u32 FASTCALL OP_LDRBT_P_REG_OFF_POSTIND(armcpu_t *cpu) return 2; oldmode = armcpu_switchMode(cpu, SYS); - execute = FALSE; + //execute = FALSE; + LOG("Untested opcode: OP_LDRBT_P_REG_OFF_POSTIND"); i = cpu->instruction; @@ -5911,7 +5914,8 @@ static u32 FASTCALL OP_LDRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) if(cpu->CPSR.bits.mode==USR) return 2; oldmode = armcpu_switchMode(cpu, SYS); - execute = FALSE; + //execute = FALSE; + LOG("Untested opcode: OP_LDRBT_P_LSL_IMM_OFF_POSTIND"); i = cpu->instruction; @@ -5938,7 +5942,8 @@ static u32 FASTCALL OP_LDRBT_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) return 2; oldmode = armcpu_switchMode(cpu, SYS); - execute = FALSE; + //execute = FALSE; + LOG("Untested opcode: OP_LDRBT_M_LSL_IMM_OFF_POSTIND"); i = cpu->instruction; @@ -5965,7 +5970,8 @@ static u32 FASTCALL OP_LDRBT_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2; oldmode = armcpu_switchMode(cpu, SYS); - execute = FALSE; + //execute = FALSE; + LOG("Untested opcode: OP_LDRBT_P_LSR_IMM_OFF_POSTIND"); i = cpu->instruction; @@ -5992,7 +5998,8 @@ static u32 FASTCALL OP_LDRBT_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2; oldmode = armcpu_switchMode(cpu, SYS); - execute = FALSE; + //execute = FALSE; + LOG("Untested opcode: OP_LDRBT_M_LSR_IMM_OFF_POSTIND"); i = cpu->instruction; @@ -6019,7 +6026,8 @@ static u32 FASTCALL OP_LDRBT_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2; oldmode = armcpu_switchMode(cpu, SYS); - execute = FALSE; + //execute = FALSE; + LOG("Untested opcode: OP_LDRBT_P_ASR_IMM_OFF_POSTIND"); i = cpu->instruction; @@ -6046,7 +6054,8 @@ static u32 FASTCALL OP_LDRBT_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2; oldmode = armcpu_switchMode(cpu, SYS); - execute = FALSE; + //execute = FALSE; + LOG("Untested opcode: OP_LDRBT_M_ASR_IMM_OFF_POSTIND"); i = cpu->instruction; @@ -6073,7 +6082,8 @@ static u32 FASTCALL OP_LDRBT_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2; oldmode = armcpu_switchMode(cpu, SYS); - execute = FALSE; + //execute = FALSE; + LOG("Untested opcode: OP_LDRBT_P_ROR_IMM_OFF_POSTIND"); i = cpu->instruction; @@ -6100,7 +6110,8 @@ static u32 FASTCALL OP_LDRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) return 2; oldmode = armcpu_switchMode(cpu, SYS); - execute = FALSE; + //execute = FALSE; + LOG("Untested opcode: OP_LDRBT_M_ROR_IMM_OFF_POSTIND"); i = cpu->instruction; @@ -6829,7 +6840,9 @@ static u32 FASTCALL OP_LDMIB2(armcpu_t *cpu) u32 start = cpu->R[REG_POS(i,16)]; u32 * registres; u32 * waitState; - execute = FALSE; + //execute = FALSE; + LOG("Untested opcode: OP_LDMIB2"); + if(BIT15(i)==0) { if(cpu->CPSR.bits.mode==USR) @@ -6886,7 +6899,9 @@ static u32 FASTCALL OP_LDMDA2(armcpu_t *cpu) u32 * waitState; u32 start = cpu->R[REG_POS(i,16)]; - execute = FALSE; + //execute = FALSE; + LOG("Untested opcode: OP_LDMDA2"); + if(BIT15(i)==0) { if(cpu->CPSR.bits.mode==USR) @@ -7395,7 +7410,8 @@ static u32 FASTCALL OP_STMIA2(armcpu_t *cpu) start = cpu->R[REG_POS(i,16)]; oldmode = armcpu_switchMode(cpu, SYS); - execute = FALSE; + //execute = FALSE; + LOG("Untested opcode: OP_STMIA2"); for(b=0; b<16; ++b) { @@ -7425,7 +7441,8 @@ static u32 FASTCALL OP_STMIB2(armcpu_t *cpu) start = cpu->R[REG_POS(i,16)]; oldmode = armcpu_switchMode(cpu, SYS); - execute = FALSE; + //execute = FALSE; + LOG("Untested opcode: OP_STMIB2"); for(b=0; b<16; ++b) { @@ -7455,7 +7472,8 @@ static u32 FASTCALL OP_STMDA2(armcpu_t *cpu) start = cpu->R[REG_POS(i,16)]; oldmode = armcpu_switchMode(cpu, SYS); - execute = FALSE; + //execute = FALSE; + LOG("Untested opcode: OP_STMDA2"); for(b=0; b<16; ++b) { @@ -7512,7 +7530,8 @@ static u32 FASTCALL OP_STMIA2_W(armcpu_t *cpu) start = cpu->R[REG_POS(i,16)]; oldmode = armcpu_switchMode(cpu, SYS); - execute = FALSE; + //execute = FALSE; + LOG("Untested opcode: OP_STMIA2_W"); for(b=0; b<16; ++b) { @@ -7571,7 +7590,8 @@ static u32 FASTCALL OP_STMDA2_W(armcpu_t *cpu) c = 0; start = cpu->R[REG_POS(i,16)]; oldmode = armcpu_switchMode(cpu, SYS); - execute = FALSE; + //execute = FALSE; + LOG("Untested opcode: OP_STMDA2_W"); for(b=0; b<16; ++b) { @@ -7604,7 +7624,8 @@ static u32 FASTCALL OP_STMDB2_W(armcpu_t *cpu) start = cpu->R[REG_POS(i,16)]; oldmode = armcpu_switchMode(cpu, SYS); - execute = FALSE; + //execute = FALSE; + LOG("Untested opcode: OP_STMDB2_W"); for(b=0; b<16; ++b) {