diff --git a/desmume/ChangeLog b/desmume/ChangeLog index 523cc81b8..01130caac 100644 --- a/desmume/ChangeLog +++ b/desmume/ChangeLog @@ -1,4 +1,5 @@ -0.8 -> ? +0.8 -> 0.9 + There have been so many changes that this list can hardly be considered complete. General/Core: - Added "high-level" check for DMAs and Timer for minor (really minor) speed up [shash] - Changed instruction execution to 16 at a time blocks (tested and stable) [shash] @@ -9,18 +10,21 @@ - Some fixes in core (New SMB don't freeze now) [CrazyMax] - Some optimizations in code [CrazyMax] - Make matrix 4x4 multiply routines use W-coordinate. [zeromus] - - Add many matrix and vector functions to matrix.c [zeromus] + - Add many matrix and vector functions to matrix.cpp [zeromus] - Convert to c++! - Added gfx3d module which emulates the whole GE as part of the core emu. Moved the windows/cocoa OGLRender to the emu core and replace ogl_collector. Now every platform shares the same 3d code. [zeromus] - Add in some crude interpolation in the SPU (conditionally compiled) so that I can bear to listen to it. [zeromus] + - Experiment: always one silent SPU core at 44.1khz synched with emu for more precision. + The audible core runs with the host, causing music to slow down but not tear or pitch bend. [zeromus] - Change savestate code to support loosely bound chunks and more easily other parts of the emu (GE, GPU). The savestate format is changed, but from now on it is in principle more resilient (it will continue to break though) [zeromus] - - Remove 16MB of WRAM at 0x01****** from arm9. Maped to unusued instead. What was this? [zeromus] + - Remove 16MB of WRAM at 0x01****** from arm9. Maped to unused instead. What was this? [zeromus] - Change SPU to run two spus in parallel. SPU_core is the official one. SPU_user produces output. This lets us do inaccurate things with SPU_user which might sound better while being more accurate with SPU_core. [zeromus] - Add RTC implementations (not fully) [CrazyMax] - Rewrite VRAM mapping control and render (old save states broken) [CrazyMax] + - Add a GUI hud system; start adding some HUD elements Mac OS X port: - Fixed: Filenames and paths with unicode characters now work. [Jeff] - Fixed: Load state from file button works again. [Jeff] @@ -54,14 +58,12 @@ - Defer rendering until after flush. This was a necessary architectural change, as it permits savestate for the display list, and allows us eventually to separate the GE emulation from the rendering [zeromus] - Fix the 2d/3d compositing well enough for NSMB to fix bugs, but it is still bad [zeromus] - - Reorganize 3d code to defer rendering to vblank. eliminates tearing, and maybe some texturing artifacts. - also possibly helps performance a bit by letting the hardware pipeline work some more before blocking for - framebuffer read. [zeromus] + - Reorganize 3d code to defer rendering to after vblank. eliminates tearing, and maybe some texturing artifacts. [zeromus] - Tweak optimization flags and change entire source code to use fastcall [zeromus] - Add opengl state caching. This is of dubious performance assistance, but it is easy to take out so I am leaving it for now. [zeromus] - Add MMU->GPU signal for when vram mappings change, which allows it to assume textures are unchanged unless vram has changed [zeromus] - Added a bunch of crazy templates to the cpu and mmu which speed up a the emu little by optimizing variable accesses [zeromus] - - Add an arm9 cpu load average calculator [zeromus] + - Add an arm9 cpu load average calculator similar to no$ [zeromus] ? Fix a bug in texture transformation mode 1 [zeromus] - Fix the buggy auto frameskip logic which made the emu slow to a crawl. Now it runs fast! [zeromus] - Fix resizing, rotate & aspect ration of main window. Add save window position and parameters [CrazyMax] diff --git a/desmume/src/MMU.cpp b/desmume/src/MMU.cpp index a100f160c..5de081a43 100644 --- a/desmume/src/MMU.cpp +++ b/desmume/src/MMU.cpp @@ -123,111 +123,113 @@ char szRomBaseName[512]; MMU_struct MMU; -u8 * MMU_ARM9_MEM_MAP[256]={ -/* 0X*/ DUP16(ARM9Mem.ARM9_ITCM), -/* 1X*/ //DUP16(ARM9Mem.ARM9_ITCM) -/* 1X*/ DUP16(MMU.UNUSED_RAM), -/* 2X*/ DUP16(ARM9Mem.MAIN_MEM), -/* 3X*/ DUP16(MMU.SWIRAM), -/* 4X*/ DUP16(ARM9Mem.ARM9_REG), -/* 5X*/ DUP16(ARM9Mem.ARM9_VMEM), -/* 6X*/ DUP2(ARM9Mem.ARM9_ABG), - DUP2(ARM9Mem.ARM9_BBG), - DUP2(ARM9Mem.ARM9_AOBJ), - DUP2(ARM9Mem.ARM9_BOBJ), - DUP8(ARM9Mem.ARM9_LCD), -/* 7X*/ DUP16(ARM9Mem.ARM9_OAM), -/* 8X*/ DUP16(NULL), -/* 9X*/ DUP16(NULL), -/* AX*/ DUP16(MMU.CART_RAM), -/* BX*/ DUP16(MMU.UNUSED_RAM), -/* CX*/ DUP16(MMU.UNUSED_RAM), -/* DX*/ DUP16(MMU.UNUSED_RAM), -/* EX*/ DUP16(MMU.UNUSED_RAM), -/* FX*/ DUP16(ARM9Mem.ARM9_BIOS) -}; - -u32 MMU_ARM9_MEM_MASK[256]={ -/* 0X*/ DUP16(0x00007FFF), -/* 1X*/ //DUP16(0x00007FFF) -/* 1X*/ DUP16(0x00000003), -/* 2X*/ DUP16(0x003FFFFF), -/* 3X*/ DUP16(0x00007FFF), -/* 4X*/ DUP16(0x00FFFFFF), -/* 5X*/ DUP16(0x000007FF), -/* 6X*/ DUP2(0x0007FFFF), - DUP2(0x0001FFFF), - DUP2(0x0003FFFF), - DUP2(0x0001FFFF), - DUP8(0x000FFFFF), -/* 7X*/ DUP16(0x000007FF), -/* 8X*/ DUP16(ROM_MASK), -/* 9X*/ DUP16(ROM_MASK), -/* AX*/ DUP16(0x0000FFFF), -/* BX*/ DUP16(0x00000003), -/* CX*/ DUP16(0x00000003), -/* DX*/ DUP16(0x00000003), -/* EX*/ DUP16(0x00000003), -/* FX*/ DUP16(0x00007FFF) +u8 * MMU_struct::MMU_MEM[2][256] = { + //arm9 + { + /* 0X*/ DUP16(ARM9Mem.ARM9_ITCM), + /* 1X*/ //DUP16(ARM9Mem.ARM9_ITCM) + /* 1X*/ DUP16(MMU.UNUSED_RAM), + /* 2X*/ DUP16(ARM9Mem.MAIN_MEM), + /* 3X*/ DUP16(MMU.SWIRAM), + /* 4X*/ DUP16(ARM9Mem.ARM9_REG), + /* 5X*/ DUP16(ARM9Mem.ARM9_VMEM), + /* 6X*/ DUP2(ARM9Mem.ARM9_ABG), + DUP2(ARM9Mem.ARM9_BBG), + DUP2(ARM9Mem.ARM9_AOBJ), + DUP2(ARM9Mem.ARM9_BOBJ), + DUP8(ARM9Mem.ARM9_LCD), + /* 7X*/ DUP16(ARM9Mem.ARM9_OAM), + /* 8X*/ DUP16(NULL), + /* 9X*/ DUP16(NULL), + /* AX*/ DUP16(MMU.CART_RAM), + /* BX*/ DUP16(MMU.UNUSED_RAM), + /* CX*/ DUP16(MMU.UNUSED_RAM), + /* DX*/ DUP16(MMU.UNUSED_RAM), + /* EX*/ DUP16(MMU.UNUSED_RAM), + /* FX*/ DUP16(ARM9Mem.ARM9_BIOS) + }, + //arm7 + { + /* 0X*/ DUP16(MMU.ARM7_BIOS), + /* 1X*/ DUP16(MMU.UNUSED_RAM), + /* 2X*/ DUP16(ARM9Mem.MAIN_MEM), + /* 3X*/ DUP8(MMU.SWIRAM), + DUP8(MMU.ARM7_ERAM), + /* 4X*/ DUP8(MMU.ARM7_REG), + DUP8(MMU.ARM7_WIRAM), + /* 5X*/ DUP16(MMU.UNUSED_RAM), + /* 6X*/ DUP16(ARM9Mem.ARM9_ABG), + /* 7X*/ DUP16(MMU.UNUSED_RAM), + /* 8X*/ DUP16(NULL), + /* 9X*/ DUP16(NULL), + /* AX*/ DUP16(MMU.CART_RAM), + /* BX*/ DUP16(MMU.UNUSED_RAM), + /* CX*/ DUP16(MMU.UNUSED_RAM), + /* DX*/ DUP16(MMU.UNUSED_RAM), + /* EX*/ DUP16(MMU.UNUSED_RAM), + /* FX*/ DUP16(MMU.UNUSED_RAM) + } }; -u8 * MMU_ARM7_MEM_MAP[256]={ -/* 0X*/ DUP16(MMU.ARM7_BIOS), -/* 1X*/ DUP16(MMU.UNUSED_RAM), -/* 2X*/ DUP16(ARM9Mem.MAIN_MEM), -/* 3X*/ DUP8(MMU.SWIRAM), - DUP8(MMU.ARM7_ERAM), -/* 4X*/ DUP8(MMU.ARM7_REG), - DUP8(MMU.ARM7_WIRAM), -/* 5X*/ DUP16(MMU.UNUSED_RAM), -/* 6X*/ DUP16(ARM9Mem.ARM9_ABG), -/* 7X*/ DUP16(MMU.UNUSED_RAM), -/* 8X*/ DUP16(NULL), -/* 9X*/ DUP16(NULL), -/* AX*/ DUP16(MMU.CART_RAM), -/* BX*/ DUP16(MMU.UNUSED_RAM), -/* CX*/ DUP16(MMU.UNUSED_RAM), -/* DX*/ DUP16(MMU.UNUSED_RAM), -/* EX*/ DUP16(MMU.UNUSED_RAM), -/* FX*/ DUP16(MMU.UNUSED_RAM) +u32 MMU_struct::MMU_MASK[2][256] = { + //arm9 + { + /* 0X*/ DUP16(0x00007FFF), + /* 1X*/ //DUP16(0x00007FFF) + /* 1X*/ DUP16(0x00000003), + /* 2X*/ DUP16(0x003FFFFF), + /* 3X*/ DUP16(0x00007FFF), + /* 4X*/ DUP16(0x00FFFFFF), + /* 5X*/ DUP16(0x000007FF), + /* 6X*/ DUP2(0x0007FFFF), + DUP2(0x0001FFFF), + DUP2(0x0003FFFF), + DUP2(0x0001FFFF), + DUP8(0x000FFFFF), + /* 7X*/ DUP16(0x000007FF), + /* 8X*/ DUP16(ROM_MASK), + /* 9X*/ DUP16(ROM_MASK), + /* AX*/ DUP16(0x0000FFFF), + /* BX*/ DUP16(0x00000003), + /* CX*/ DUP16(0x00000003), + /* DX*/ DUP16(0x00000003), + /* EX*/ DUP16(0x00000003), + /* FX*/ DUP16(0x00007FFF) + }, + //arm7 + { + /* 0X*/ DUP16(0x00003FFF), + /* 1X*/ DUP16(0x00000003), + /* 2X*/ DUP16(0x003FFFFF), + /* 3X*/ DUP8(0x00007FFF), + DUP8(0x0000FFFF), + /* 4X*/ DUP8(0x00FFFFFF), + DUP8(0x0000FFFF), + /* 5X*/ DUP16(0x00000003), + /* 6X*/ DUP16(0x0003FFFF), + /* 7X*/ DUP16(0x00000003), + /* 8X*/ DUP16(ROM_MASK), + /* 9X*/ DUP16(ROM_MASK), + /* AX*/ DUP16(0x0000FFFF), + /* BX*/ DUP16(0x00000003), + /* CX*/ DUP16(0x00000003), + /* DX*/ DUP16(0x00000003), + /* EX*/ DUP16(0x00000003), + /* FX*/ DUP16(0x00000003) + } }; -u32 MMU_ARM7_MEM_MASK[256]={ -/* 0X*/ DUP16(0x00003FFF), -/* 1X*/ DUP16(0x00000003), -/* 2X*/ DUP16(0x003FFFFF), -/* 3X*/ DUP8(0x00007FFF), - DUP8(0x0000FFFF), -/* 4X*/ DUP8(0x00FFFFFF), - DUP8(0x0000FFFF), -/* 5X*/ DUP16(0x00000003), -/* 6X*/ DUP16(0x0003FFFF), -/* 7X*/ DUP16(0x00000003), -/* 8X*/ DUP16(ROM_MASK), -/* 9X*/ DUP16(ROM_MASK), -/* AX*/ DUP16(0x0000FFFF), -/* BX*/ DUP16(0x00000003), -/* CX*/ DUP16(0x00000003), -/* DX*/ DUP16(0x00000003), -/* EX*/ DUP16(0x00000003), -/* FX*/ DUP16(0x00000003) + +TWaitState MMU_struct::MMU_WAIT16[2][16] = { + { 1, 1, 1, 1, 1, 1, 1, 1, 5, 5, 5, 1, 1, 1, 1, 1 }, //arm9 + { 1, 1, 1, 1, 1, 1, 1, 1, 5, 5, 5, 1, 1, 1, 1, 1 }, //arm7 }; -u32 MMU_ARM9_WAIT16[16]={ - 1, 1, 1, 1, 1, 1, 1, 1, 5, 5, 5, 1, 1, 1, 1, 1, +TWaitState MMU_struct::MMU_WAIT32[2][16] = { + { 1, 1, 1, 1, 1, 2, 2, 1, 8, 8, 5, 1, 1, 1, 1, 1 }, //arm9 + { 1, 1, 1, 1, 1, 1, 1, 1, 8, 8, 5, 1, 1, 1, 1, 1 }, //arm7 }; -u32 MMU_ARM9_WAIT32[16]={ - 1, 1, 1, 1, 1, 2, 2, 1, 8, 8, 5, 1, 1, 1, 1, 1, -}; - -u32 MMU_ARM7_WAIT16[16]={ - 1, 1, 1, 1, 1, 1, 1, 1, 5, 5, 5, 1, 1, 1, 1, 1, -}; - -u32 MMU_ARM7_WAIT32[16]={ - 1, 1, 1, 1, 1, 1, 1, 1, 8, 8, 5, 1, 1, 1, 1, 1, -}; u32 gxIRQ = 0; @@ -256,23 +258,14 @@ void MMU_Init(void) { for(i = 0x80; i<0xA0; ++i) { - MMU_ARM9_MEM_MAP[i] = MMU.CART_ROM; - MMU_ARM7_MEM_MAP[i] = MMU.CART_ROM; + MMU_struct::MMU_MEM[0][i] = MMU.CART_ROM; + MMU_struct::MMU_MEM[1][i] = MMU.CART_ROM; } - MMU.MMU_MEM[0] = MMU_ARM9_MEM_MAP; - MMU.MMU_MEM[1] = MMU_ARM7_MEM_MAP; - MMU.MMU_MASK[0]= MMU_ARM9_MEM_MASK; - MMU.MMU_MASK[1] = MMU_ARM7_MEM_MASK; MMU.DTCMRegion = 0x027C0000; MMU.ITCMRegion = 0x00000000; - MMU.MMU_WAIT16[0] = MMU_ARM9_WAIT16; - MMU.MMU_WAIT16[1] = MMU_ARM7_WAIT16; - MMU.MMU_WAIT32[0] = MMU_ARM9_WAIT32; - MMU.MMU_WAIT32[1] = MMU_ARM7_WAIT32; - FIFOclear(&MMU.fifos[0]); FIFOclear(&MMU.fifos[1]); @@ -422,10 +415,9 @@ u8 *MMU_RenderMapToLCD(u32 vram_addr) return NULL; } -static INLINE BOOL MMU_LCDmap(u32 *addr) +static FORCEINLINE bool MMU_LCDmap(u32 &addr) { - u32 vram_addr = (u32)*addr; - + u32 vram_addr = addr; if ((vram_addr >= 0x6000000) && (vram_addr <= 0x67FFFFF)) { vram_addr &= 0x0FFFFFF; @@ -433,16 +425,16 @@ static INLINE BOOL MMU_LCDmap(u32 *addr) vram_addr &= 0x01FFFFF; u8 engine_offset = (vram_addr >> 14); u8 block = MMU.VRAM_MAP[engine][engine_offset]; - if (block == 7) return TRUE; + if (block == 7) return true; //INFO("VRAM %i: engine=%i (offset=%i), map address = 0x%X, MMU address = 0x%X\n", block, engine, engine_offset, vram_addr, *addr); vram_addr -= MMU.LCD_VRAM_ADDR[block]; vram_addr += LCDdata[block][0]; - *addr = vram_addr; + addr = vram_addr; } - return FALSE; + return false; } -static INLINE void MMU_VRAMmapControl(u8 block, u8 VRAMBankCnt) +static inline void MMU_VRAMmapControl(u8 block, u8 VRAMBankCnt) { if (!(VRAMBankCnt & 0x80)) return; if (!(VRAMBankCnt & 0x07)) return; @@ -602,10 +594,10 @@ void MMU_setRom(u8 * rom, u32 mask) for(i = 0x80; i<0xA0; ++i) { - MMU_ARM9_MEM_MAP[i] = rom; - MMU_ARM7_MEM_MAP[i] = rom; - MMU_ARM9_MEM_MASK[i] = mask; - MMU_ARM7_MEM_MASK[i] = mask; + MMU_struct::MMU_MEM[0][i] = rom; + MMU_struct::MMU_MEM[1][i] = rom; + MMU_struct::MMU_MASK[0][i] = mask; + MMU_struct::MMU_MASK[1][i] = mask; } rom_mask = mask; } @@ -617,10 +609,10 @@ void MMU_unsetRom() for(i = 0x80; i<0xA0; ++i) { - MMU_ARM9_MEM_MAP[i] = MMU.UNUSED_RAM; - MMU_ARM7_MEM_MAP[i] = MMU.UNUSED_RAM; - MMU_ARM9_MEM_MASK[i] = ROM_MASK; - MMU_ARM7_MEM_MASK[i] = ROM_MASK; + MMU_struct::MMU_MEM[0][i] = MMU.UNUSED_RAM; + MMU_struct::MMU_MEM[1][i] = MMU.UNUSED_RAM; + MMU_struct::MMU_MASK[0][i] = ROM_MASK; + MMU_struct::MMU_MASK[1][i] = ROM_MASK; } rom_mask = ROM_MASK; } @@ -659,7 +651,7 @@ u8 FASTCALL _MMU_read8(u32 adr) } #endif - if (MMU_LCDmap(&adr)) return (0); + if (MMU_LCDmap(adr)) return (0); mmu_log_debug(adr, proc, "read08"); @@ -693,7 +685,7 @@ u16 FASTCALL _MMU_read16(u32 adr) adr &= 0x0FFFFFFF; - if (MMU_LCDmap(&adr)) return (0); + if (MMU_LCDmap(adr)) return (0); if(adr&0x04000000) { @@ -766,7 +758,7 @@ u32 FASTCALL _MMU_read32(u32 adr) return (unsigned long)cflash_read(adr); adr &= 0x0FFFFFFF; - if (MMU_LCDmap(&adr)) return (0); + if (MMU_LCDmap(adr)) return (0); if((adr >> 24) == 4) { @@ -950,7 +942,7 @@ void FASTCALL _MMU_write8(u32 adr, u8 val) return ; } - if (MMU_LCDmap(&adr)) return; + if (MMU_LCDmap(adr)) return; switch(adr) { @@ -1171,7 +1163,7 @@ void FASTCALL _MMU_write16(u32 adr, u16 val) } } - if (MMU_LCDmap(&adr)) return; + if (MMU_LCDmap(adr)) return; if((adr >> 24) == 4) { @@ -1842,7 +1834,7 @@ void FASTCALL _MMU_write32(u32 adr, u32 val) } } - if (MMU_LCDmap(&adr)) return; + if (MMU_LCDmap(adr)) return; if ((adr & 0xFF800000) == 0x04800000) { /* access to non regular hw registers */ diff --git a/desmume/src/MMU.h b/desmume/src/MMU.h index 6967efa32..62a5f6f23 100644 --- a/desmume/src/MMU.h +++ b/desmume/src/MMU.h @@ -42,7 +42,9 @@ extern char szRomBaseName[512]; //#define IPCFIFO 0 //#define MAIN_MEMORY_DISP_FIFO 2 -typedef struct { +typedef const u32 TWaitState; + +struct MMU_struct { //ARM7 mem u8 ARM7_BIOS[0x4000]; u8 ARM7_ERAM[0x10000]; @@ -69,16 +71,16 @@ typedef struct { //(also since the emulator doesn't prevent unaligned accesses) u8 MORE_UNUSED_RAM[4]; - u8 * * MMU_MEM[2]; - u32 * MMU_MASK[2]; + static u8 * MMU_MEM[2][256]; + static u32 MMU_MASK[2][256]; u8 ARM9_RW_MODE; FIFO fifos[2]; // 0 - ARM9 FIFO // 1 - ARM7 FIFO - u32 * MMU_WAIT16[2]; - u32 * MMU_WAIT32[2]; + static TWaitState MMU_WAIT16[2][16]; + static TWaitState MMU_WAIT32[2][16]; u32 DTCMRegion; u32 ITCMRegion; @@ -105,7 +107,7 @@ typedef struct { u32 CheckTimers; u32 CheckDMAs; -} MMU_struct; +}; extern MMU_struct MMU; diff --git a/desmume/src/NDSSystem.cpp b/desmume/src/NDSSystem.cpp index a62a8e3eb..1861a15b2 100644 --- a/desmume/src/NDSSystem.cpp +++ b/desmume/src/NDSSystem.cpp @@ -21,6 +21,7 @@ #include #include +#include #include "NDSSystem.h" #include "render3D.h" @@ -869,16 +870,26 @@ int NDS_LoadFirmware(const char *filename) } #define INDEX(i) ((((i)>>16)&0xFF0)|(((i)>>4)&0xF)) -u32 -NDS_exec(s32 nb, BOOL force) + + +template +u32 NDS_exec(s32 nb) { int i, j; nb += nds.cycles;//(nds.cycles>>26)<<26; + + //increase this to execute more instructions in each batch (reducing overhead) + //the value of 4 seems to optimize speed.. do lower values increase precision? + const int INSTRUCTIONS_PER_BATCH = 4; + + //decreasing this should increase precision at the cost of speed + //the traditional value was somewhere between 100 and 400 depending on circumstances + const int CYCLES_TO_WAIT_FOR_IRQ = 400; - for(; (nb >= nds.cycles) && ((force)||(execute)); ) + for(; (nb >= nds.cycles) && ((FORCE)||(execute)); ) { - for (j = 0; j < 4 && (!force) && (execute); j++) + for (j = 0; j < INSTRUCTIONS_PER_BATCH && (!FORCE) && (execute); j++) { if(nds.ARM9Cycle<=nds.cycles) { @@ -895,18 +906,17 @@ NDS_exec(s32 nb, BOOL force) LOG(logbuf); } #endif - for (i = 0; i < 4 && (!force) && (execute); i++) + for (i = 0; i < INSTRUCTIONS_PER_BATCH && (!FORCE) && (execute); i++) { if(NDS_ARM9.waitIRQ) { - nds.ARM9Cycle += 100; - nds.idleCycles += 100; + nds.ARM9Cycle += CYCLES_TO_WAIT_FOR_IRQ; + nds.idleCycles += CYCLES_TO_WAIT_FOR_IRQ; + break; //it is rather pointless to do this more than once } else - //nds.ARM9Cycle += NDS_ARM9.exec(); - //nds.ARM9Cycle += armcpu_exec(&NDS_ARM9); - nds.ARM9Cycle += armcpu_exec<0>(); + nds.ARM9Cycle += armcpu_exec(); } #ifdef _WIN32 - DisassemblerTools_Refresh(0); + DisassemblerTools_Refresh(ARMCPU_ARM9); #endif } @@ -933,26 +943,27 @@ NDS_exec(s32 nb, BOOL force) LOG(logbuf); } #endif - for (i = 0; i < 4 && (!force) && (execute); i++) + for (i = 0; i < INSTRUCTIONS_PER_BATCH && (!FORCE) && (execute); i++) { if(NDS_ARM7.waitIRQ) - nds.ARM7Cycle += 100; + { + nds.ARM7Cycle += CYCLES_TO_WAIT_FOR_IRQ; + break; //it is rather pointless to do this more than once + } else - //nds.ARM7Cycle += (NDS_ARM7.exec()<<1); - //nds.ARM7Cycle += (armcpu_exec(&NDS_ARM7)<<1); - nds.ARM7Cycle += (armcpu_exec<1>()<<1); + nds.ARM7Cycle += (armcpu_exec()<<1); } #ifdef _WIN32 - DisassemblerTools_Refresh(1); + DisassemblerTools_Refresh(ARMCPU_ARM7); #endif } } - nds.cycles = (nds.ARM9Cycle=nds.nextHBlank) + + if(nds.cycles>=nds.nextHBlank) { if(!nds.lignerendu) { @@ -1041,8 +1052,8 @@ NDS_exec(s32 nb, BOOL force) nds.lignerendu = FALSE; if(nds.VCount==192) { - gfx3d_VBlankSignal(); //osdA->update(); //================================= this is don't correct, need swap engine + gfx3d_VBlankSignal(); T1WriteWord(ARM9Mem.ARM9_REG, 4, T1ReadWord(ARM9Mem.ARM9_REG, 4) | 1); T1WriteWord(MMU.ARM7_REG, 4, T1ReadWord(MMU.ARM7_REG, 4) | 1); @@ -1072,8 +1083,10 @@ NDS_exec(s32 nb, BOOL force) if(MMU.DMAStartTime[1][3] == 1) MMU_doDMA(1, 3); } - else - if(nds.VCount==263) + else if(nds.VCount==214) { + gfx3d_VBlankEndSignal(); + } + else if(nds.VCount==263) { //osd->update(); //osdB->update(); //================================= this is don't correct, need swap engine @@ -1086,7 +1099,7 @@ NDS_exec(s32 nb, BOOL force) nds.cycles -= (560190<<1); nds.ARM9Cycle -= (560190<<1); nds.ARM7Cycle -= (560190<<1); - nb -= (560190<<1); + nb -= (560190<<1); if (MMU.CheckTimers) { @@ -1581,6 +1594,9 @@ NDS_exec(s32 nb, BOOL force) } } + + + } return nds.cycles; @@ -1688,3 +1704,7 @@ void NDS_setPad(bool R,bool L,bool D,bool U,bool T,bool S,bool B,bool A,bool Y,b // TODO: low power IRQ } + +//these templates needed to be instantiated manually +template u32 NDS_exec(s32 nb); +template u32 NDS_exec(s32 nb); diff --git a/desmume/src/NDSSystem.h b/desmume/src/NDSSystem.h index 3f01bb4da..217486496 100644 --- a/desmume/src/NDSSystem.h +++ b/desmume/src/NDSSystem.h @@ -201,8 +201,11 @@ int NDS_ImportSave(const char *filename); int NDS_WriteBMP(const char *filename); int NDS_LoadFirmware(const char *filename); int NDS_CreateDummyFirmware( struct NDS_fw_config_data *user_settings); -u32 -NDS_exec(s32 nb, BOOL force); + +template +u32 NDS_exec(s32 nb); + +inline u32 NDS_exec(s32 nb) { return NDS_exec(nb); } static INLINE void NDS_ARM9HBlankInt(void) { diff --git a/desmume/src/OGLRender.cpp b/desmume/src/OGLRender.cpp index e6adfec2e..b8c83a831 100644 --- a/desmume/src/OGLRender.cpp +++ b/desmume/src/OGLRender.cpp @@ -677,6 +677,7 @@ static void setTexture(unsigned int format, unsigned int texpal) glLoadIdentity (); glScaled (texcache[i].invSizeX, texcache[i].invSizeY, 1.0f); + //INFO("Texture %03i - format=%08X; pal=%04X (mode %X, width %04i, height %04i)\n",i, texcache[i].frm, texcache[i].pal, texcache[i].mode, sizeX, sizeY); //============================================================================ Texture render diff --git a/desmume/src/arm_instructions.cpp b/desmume/src/arm_instructions.cpp index 53624787c..91e0bccbe 100644 --- a/desmume/src/arm_instructions.cpp +++ b/desmume/src/arm_instructions.cpp @@ -256,7 +256,7 @@ TEMPLATE static u32 FASTCALL OP_UND() #define TRAPUNDEF() \ LOG("Undefined instruction: %#08X PC = %#08X\n", cpu->instruction, cpu->instruct_adr); \ \ - if (((cpu->intVector != 0) ^ (cpu->proc_ID == ARMCPU_ARM9))){ \ + if (((cpu->intVector != 0) ^ (PROCNUM == ARMCPU_ARM9))){ \ Status_Reg tmp = cpu->CPSR; \ armcpu_switchMode(cpu, UND); /* enter und mode */ \ cpu->R[14] = cpu->R[15] - 4; /* jump to und Vector */ \ @@ -303,7 +303,7 @@ TEMPLATE static u32 FASTCALL OP_UND() TEMPLATE static u32 FASTCALL OP_AND_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSL_IMM; OP_AND(1, 3); @@ -311,14 +311,14 @@ TEMPLATE static u32 FASTCALL OP_AND_LSL_IMM() TEMPLATE static u32 FASTCALL OP_AND_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSL_REG; OP_AND(2, 4); } TEMPLATE static u32 FASTCALL OP_AND_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSR_IMM; OP_AND(1, 3); @@ -326,14 +326,14 @@ TEMPLATE static u32 FASTCALL OP_AND_LSR_IMM() TEMPLATE static u32 FASTCALL OP_AND_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSR_REG; OP_AND(2, 4); } TEMPLATE static u32 FASTCALL OP_AND_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ASR_IMM; OP_AND(1, 3); @@ -341,14 +341,14 @@ TEMPLATE static u32 FASTCALL OP_AND_ASR_IMM() TEMPLATE static u32 FASTCALL OP_AND_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ASR_REG; OP_AND(2, 4); } TEMPLATE static u32 FASTCALL OP_AND_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ROR_IMM; OP_AND(1, 3); @@ -356,77 +356,77 @@ TEMPLATE static u32 FASTCALL OP_AND_ROR_IMM() TEMPLATE static u32 FASTCALL OP_AND_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ROR_REG; OP_AND(2, 4); } TEMPLATE static u32 FASTCALL OP_AND_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; IMM_VALUE; OP_AND(1, 3); } TEMPLATE static u32 FASTCALL OP_AND_S_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSL_IMM; OP_ANDS(2, 4); } TEMPLATE static u32 FASTCALL OP_AND_S_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSL_REG; OP_ANDS(3, 5); } TEMPLATE static u32 FASTCALL OP_AND_S_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSR_IMM; OP_ANDS(2, 4); } TEMPLATE static u32 FASTCALL OP_AND_S_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSR_REG; OP_ANDS(3, 5); } TEMPLATE static u32 FASTCALL OP_AND_S_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ASR_IMM; OP_ANDS(2, 4); } TEMPLATE static u32 FASTCALL OP_AND_S_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ASR_REG; OP_ANDS(3, 5); } TEMPLATE static u32 FASTCALL OP_AND_S_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ROR_IMM; OP_ANDS(2, 4); } TEMPLATE static u32 FASTCALL OP_AND_S_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ROR_REG; OP_ANDS(3, 5); } TEMPLATE static u32 FASTCALL OP_AND_S_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_IMM_VALUE; OP_ANDS(2, 4); } @@ -458,7 +458,7 @@ TEMPLATE static u32 FASTCALL OP_AND_S_IMM_VAL() TEMPLATE static u32 FASTCALL OP_EOR_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSL_IMM; OP_EOR(1, 3); @@ -466,14 +466,14 @@ TEMPLATE static u32 FASTCALL OP_EOR_LSL_IMM() TEMPLATE static u32 FASTCALL OP_EOR_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSL_REG; OP_EOR(2, 4); } TEMPLATE static u32 FASTCALL OP_EOR_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSR_IMM; OP_EOR(1, 3); @@ -481,14 +481,14 @@ TEMPLATE static u32 FASTCALL OP_EOR_LSR_IMM() TEMPLATE static u32 FASTCALL OP_EOR_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSR_REG; OP_EOR(2, 4); } TEMPLATE static u32 FASTCALL OP_EOR_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ASR_IMM; OP_EOR(1, 3); @@ -496,14 +496,14 @@ TEMPLATE static u32 FASTCALL OP_EOR_ASR_IMM() TEMPLATE static u32 FASTCALL OP_EOR_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ASR_REG; OP_EOR(2, 4); } TEMPLATE static u32 FASTCALL OP_EOR_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ROR_IMM; OP_EOR(1, 3); @@ -511,77 +511,77 @@ TEMPLATE static u32 FASTCALL OP_EOR_ROR_IMM() TEMPLATE static u32 FASTCALL OP_EOR_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ROR_REG; OP_EOR(2, 4); } TEMPLATE static u32 FASTCALL OP_EOR_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; IMM_VALUE; OP_EOR(1, 3); } TEMPLATE static u32 FASTCALL OP_EOR_S_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSL_IMM; OP_EORS(2, 4); } TEMPLATE static u32 FASTCALL OP_EOR_S_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSL_REG; OP_EORS(3, 5); } TEMPLATE static u32 FASTCALL OP_EOR_S_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSR_IMM; OP_EORS(2, 4); } TEMPLATE static u32 FASTCALL OP_EOR_S_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSR_REG; OP_EORS(3, 5); } TEMPLATE static u32 FASTCALL OP_EOR_S_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ASR_IMM; OP_EORS(2, 4); } TEMPLATE static u32 FASTCALL OP_EOR_S_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ASR_REG; OP_EORS(3, 5); } TEMPLATE static u32 FASTCALL OP_EOR_S_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ROR_IMM; OP_EORS(2, 4); } TEMPLATE static u32 FASTCALL OP_EOR_S_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ROR_REG; OP_EORS(3, 5); } TEMPLATE static u32 FASTCALL OP_EOR_S_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_IMM_VALUE; OP_EORS(2, 4); } @@ -614,7 +614,7 @@ TEMPLATE static u32 FASTCALL OP_EOR_S_IMM_VAL() TEMPLATE static u32 FASTCALL OP_SUB_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSL_IMM; OP_SUB(1, 3); @@ -622,14 +622,14 @@ TEMPLATE static u32 FASTCALL OP_SUB_LSL_IMM() TEMPLATE static u32 FASTCALL OP_SUB_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSL_REG; OP_SUB(2, 4); } TEMPLATE static u32 FASTCALL OP_SUB_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSR_IMM; OP_SUB(1, 3); @@ -637,14 +637,14 @@ TEMPLATE static u32 FASTCALL OP_SUB_LSR_IMM() TEMPLATE static u32 FASTCALL OP_SUB_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSR_REG; OP_SUB(2, 4); } TEMPLATE static u32 FASTCALL OP_SUB_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ASR_IMM; OP_SUB(1, 3); @@ -652,14 +652,14 @@ TEMPLATE static u32 FASTCALL OP_SUB_ASR_IMM() TEMPLATE static u32 FASTCALL OP_SUB_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ASR_REG; OP_SUB(2, 4); } TEMPLATE static u32 FASTCALL OP_SUB_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ROR_IMM; OP_SUB(1, 3); @@ -667,21 +667,21 @@ TEMPLATE static u32 FASTCALL OP_SUB_ROR_IMM() TEMPLATE static u32 FASTCALL OP_SUB_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ROR_REG; OP_SUB(2, 4); } TEMPLATE static u32 FASTCALL OP_SUB_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; IMM_VALUE; OP_SUB(1, 3); } TEMPLATE static u32 FASTCALL OP_SUB_S_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; LSL_IMM; @@ -690,7 +690,7 @@ TEMPLATE static u32 FASTCALL OP_SUB_S_LSL_IMM() TEMPLATE static u32 FASTCALL OP_SUB_S_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; LSL_REG; OPSUBS(3, 5); @@ -698,7 +698,7 @@ TEMPLATE static u32 FASTCALL OP_SUB_S_LSL_REG() TEMPLATE static u32 FASTCALL OP_SUB_S_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; LSR_IMM; @@ -707,7 +707,7 @@ TEMPLATE static u32 FASTCALL OP_SUB_S_LSR_IMM() TEMPLATE static u32 FASTCALL OP_SUB_S_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; LSR_REG; OPSUBS(3, 5); @@ -715,7 +715,7 @@ TEMPLATE static u32 FASTCALL OP_SUB_S_LSR_REG() TEMPLATE static u32 FASTCALL OP_SUB_S_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; ASR_IMM; @@ -724,7 +724,7 @@ TEMPLATE static u32 FASTCALL OP_SUB_S_ASR_IMM() TEMPLATE static u32 FASTCALL OP_SUB_S_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; ASR_REG; OPSUBS(3, 5); @@ -732,7 +732,7 @@ TEMPLATE static u32 FASTCALL OP_SUB_S_ASR_REG() TEMPLATE static u32 FASTCALL OP_SUB_S_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; ROR_IMM; @@ -741,7 +741,7 @@ TEMPLATE static u32 FASTCALL OP_SUB_S_ROR_IMM() TEMPLATE static u32 FASTCALL OP_SUB_S_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; ROR_REG; OPSUBS(3, 5); @@ -749,7 +749,7 @@ TEMPLATE static u32 FASTCALL OP_SUB_S_ROR_REG() TEMPLATE static u32 FASTCALL OP_SUB_S_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; IMM_VALUE; OPSUBS(2, 4); @@ -783,7 +783,7 @@ TEMPLATE static u32 FASTCALL OP_SUB_S_IMM_VAL() TEMPLATE static u32 FASTCALL OP_RSB_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSL_IMM; OP_RSB(1, 3); @@ -791,14 +791,14 @@ TEMPLATE static u32 FASTCALL OP_RSB_LSL_IMM() TEMPLATE static u32 FASTCALL OP_RSB_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSL_REG; OP_RSB(2, 4); } TEMPLATE static u32 FASTCALL OP_RSB_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSR_IMM; OP_RSB(1, 3); @@ -806,14 +806,14 @@ TEMPLATE static u32 FASTCALL OP_RSB_LSR_IMM() TEMPLATE static u32 FASTCALL OP_RSB_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSR_REG; OP_RSB(2, 4); } TEMPLATE static u32 FASTCALL OP_RSB_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ASR_IMM; OP_RSB(1, 3); @@ -821,14 +821,14 @@ TEMPLATE static u32 FASTCALL OP_RSB_ASR_IMM() TEMPLATE static u32 FASTCALL OP_RSB_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ASR_REG; OP_RSB(2, 4); } TEMPLATE static u32 FASTCALL OP_RSB_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ROR_IMM; OP_RSB(1, 3); @@ -836,21 +836,21 @@ TEMPLATE static u32 FASTCALL OP_RSB_ROR_IMM() TEMPLATE static u32 FASTCALL OP_RSB_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ROR_REG; OP_RSB(2, 4); } TEMPLATE static u32 FASTCALL OP_RSB_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; IMM_VALUE; OP_RSB(1, 3); } TEMPLATE static u32 FASTCALL OP_RSB_S_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; LSL_IMM; @@ -859,7 +859,7 @@ TEMPLATE static u32 FASTCALL OP_RSB_S_LSL_IMM() TEMPLATE static u32 FASTCALL OP_RSB_S_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; LSL_REG; OP_RSBS(3, 5); @@ -867,7 +867,7 @@ TEMPLATE static u32 FASTCALL OP_RSB_S_LSL_REG() TEMPLATE static u32 FASTCALL OP_RSB_S_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; LSR_IMM; @@ -876,7 +876,7 @@ TEMPLATE static u32 FASTCALL OP_RSB_S_LSR_IMM() TEMPLATE static u32 FASTCALL OP_RSB_S_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; LSR_REG; OP_RSBS(3, 5); @@ -884,7 +884,7 @@ TEMPLATE static u32 FASTCALL OP_RSB_S_LSR_REG() TEMPLATE static u32 FASTCALL OP_RSB_S_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; ASR_IMM; @@ -893,7 +893,7 @@ TEMPLATE static u32 FASTCALL OP_RSB_S_ASR_IMM() TEMPLATE static u32 FASTCALL OP_RSB_S_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; ASR_REG; OP_RSBS(3, 5); @@ -901,7 +901,7 @@ TEMPLATE static u32 FASTCALL OP_RSB_S_ASR_REG() TEMPLATE static u32 FASTCALL OP_RSB_S_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; ROR_IMM; @@ -910,7 +910,7 @@ TEMPLATE static u32 FASTCALL OP_RSB_S_ROR_IMM() TEMPLATE static u32 FASTCALL OP_RSB_S_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; ROR_REG; OP_RSBS(3, 5); @@ -918,7 +918,7 @@ TEMPLATE static u32 FASTCALL OP_RSB_S_ROR_REG() TEMPLATE static u32 FASTCALL OP_RSB_S_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; IMM_VALUE; OP_RSBS(2, 4); @@ -936,7 +936,7 @@ TEMPLATE static u32 FASTCALL OP_RSB_S_IMM_VAL() TEMPLATE static u32 FASTCALL OP_ADD_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSL_IMM; OP_ADD(1, 3); @@ -944,14 +944,14 @@ TEMPLATE static u32 FASTCALL OP_ADD_LSL_IMM() TEMPLATE static u32 FASTCALL OP_ADD_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSL_REG; OP_ADD(2, 4); } TEMPLATE static u32 FASTCALL OP_ADD_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSR_IMM; OP_ADD(1, 3); @@ -959,14 +959,14 @@ TEMPLATE static u32 FASTCALL OP_ADD_LSR_IMM() TEMPLATE static u32 FASTCALL OP_ADD_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSR_REG; OP_ADD(2, 4); } TEMPLATE static u32 FASTCALL OP_ADD_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ASR_IMM; OP_ADD(1, 3); @@ -974,14 +974,14 @@ TEMPLATE static u32 FASTCALL OP_ADD_ASR_IMM() TEMPLATE static u32 FASTCALL OP_ADD_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ASR_REG; OP_ADD(2, 4); } TEMPLATE static u32 FASTCALL OP_ADD_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ROR_IMM; OP_ADD(1, 3); @@ -989,14 +989,14 @@ TEMPLATE static u32 FASTCALL OP_ADD_ROR_IMM() TEMPLATE static u32 FASTCALL OP_ADD_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ROR_REG; OP_ADD(2, 4); } TEMPLATE static u32 FASTCALL OP_ADD_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; IMM_VALUE; OP_ADD(1, 3); } @@ -1019,7 +1019,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_IMM_VAL() TEMPLATE static u32 FASTCALL OP_ADD_S_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; LSL_IMM; @@ -1028,7 +1028,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_S_LSL_IMM() TEMPLATE static u32 FASTCALL OP_ADD_S_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; LSL_REG; OP_ADDS(3, 5); @@ -1036,7 +1036,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_S_LSL_REG() TEMPLATE static u32 FASTCALL OP_ADD_S_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; LSR_IMM; @@ -1045,7 +1045,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_S_LSR_IMM() TEMPLATE static u32 FASTCALL OP_ADD_S_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; LSR_REG; OP_ADDS(3, 5); @@ -1053,7 +1053,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_S_LSR_REG() TEMPLATE static u32 FASTCALL OP_ADD_S_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; ASR_IMM; @@ -1062,7 +1062,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_S_ASR_IMM() TEMPLATE static u32 FASTCALL OP_ADD_S_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; ASR_REG; OP_ADDS(3, 5); @@ -1070,7 +1070,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_S_ASR_REG() TEMPLATE static u32 FASTCALL OP_ADD_S_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; ROR_IMM; @@ -1079,7 +1079,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_S_ROR_IMM() TEMPLATE static u32 FASTCALL OP_ADD_S_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; ROR_REG; OP_ADDS(3, 5); @@ -1087,7 +1087,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_S_ROR_REG() TEMPLATE static u32 FASTCALL OP_ADD_S_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; IMM_VALUE; OP_ADDS(2, 4); @@ -1105,7 +1105,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_S_IMM_VAL() TEMPLATE static u32 FASTCALL OP_ADC_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSL_IMM; OP_ADC(1, 3); @@ -1113,14 +1113,14 @@ TEMPLATE static u32 FASTCALL OP_ADC_LSL_IMM() TEMPLATE static u32 FASTCALL OP_ADC_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSL_REG; OP_ADC(2, 4); } TEMPLATE static u32 FASTCALL OP_ADC_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSR_IMM; OP_ADC(1, 3); @@ -1128,14 +1128,14 @@ TEMPLATE static u32 FASTCALL OP_ADC_LSR_IMM() TEMPLATE static u32 FASTCALL OP_ADC_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSR_REG; OP_ADC(2, 4); } TEMPLATE static u32 FASTCALL OP_ADC_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ASR_IMM; OP_ADC(1, 3); @@ -1143,14 +1143,14 @@ TEMPLATE static u32 FASTCALL OP_ADC_ASR_IMM() TEMPLATE static u32 FASTCALL OP_ADC_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ASR_REG; OP_ADC(2, 4); } TEMPLATE static u32 FASTCALL OP_ADC_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ROR_IMM; OP_ADC(1, 3); @@ -1158,14 +1158,14 @@ TEMPLATE static u32 FASTCALL OP_ADC_ROR_IMM() TEMPLATE static u32 FASTCALL OP_ADC_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ROR_REG; OP_ADC(2, 4); } TEMPLATE static u32 FASTCALL OP_ADC_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; IMM_VALUE; OP_ADC(1, 3); } @@ -1192,7 +1192,7 @@ TEMPLATE static u32 FASTCALL OP_ADC_IMM_VAL() TEMPLATE static u32 FASTCALL OP_ADC_S_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; LSL_IMM; @@ -1201,7 +1201,7 @@ TEMPLATE static u32 FASTCALL OP_ADC_S_LSL_IMM() TEMPLATE static u32 FASTCALL OP_ADC_S_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; LSL_REG; OP_ADCS(3, 5); @@ -1209,7 +1209,7 @@ TEMPLATE static u32 FASTCALL OP_ADC_S_LSL_REG() TEMPLATE static u32 FASTCALL OP_ADC_S_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; LSR_IMM; @@ -1218,7 +1218,7 @@ TEMPLATE static u32 FASTCALL OP_ADC_S_LSR_IMM() TEMPLATE static u32 FASTCALL OP_ADC_S_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; LSR_REG; OP_ADCS(3, 5); @@ -1226,7 +1226,7 @@ TEMPLATE static u32 FASTCALL OP_ADC_S_LSR_REG() TEMPLATE static u32 FASTCALL OP_ADC_S_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; ASR_IMM; @@ -1235,7 +1235,7 @@ TEMPLATE static u32 FASTCALL OP_ADC_S_ASR_IMM() TEMPLATE static u32 FASTCALL OP_ADC_S_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; ASR_REG; OP_ADCS(3, 5); @@ -1243,7 +1243,7 @@ TEMPLATE static u32 FASTCALL OP_ADC_S_ASR_REG() TEMPLATE static u32 FASTCALL OP_ADC_S_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; ROR_IMM; @@ -1252,7 +1252,7 @@ TEMPLATE static u32 FASTCALL OP_ADC_S_ROR_IMM() TEMPLATE static u32 FASTCALL OP_ADC_S_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; ROR_REG; OP_ADCS(3, 5); @@ -1260,7 +1260,7 @@ TEMPLATE static u32 FASTCALL OP_ADC_S_ROR_REG() TEMPLATE static u32 FASTCALL OP_ADC_S_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; IMM_VALUE; OP_ADCS(2, 4); @@ -1278,7 +1278,7 @@ TEMPLATE static u32 FASTCALL OP_ADC_S_IMM_VAL() TEMPLATE static u32 FASTCALL OP_SBC_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSL_IMM; OP_SBC(1, 3); @@ -1286,14 +1286,14 @@ TEMPLATE static u32 FASTCALL OP_SBC_LSL_IMM() TEMPLATE static u32 FASTCALL OP_SBC_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSL_REG; OP_SBC(2, 4); } TEMPLATE static u32 FASTCALL OP_SBC_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSR_IMM; OP_SBC(1, 3); @@ -1301,14 +1301,14 @@ TEMPLATE static u32 FASTCALL OP_SBC_LSR_IMM() TEMPLATE static u32 FASTCALL OP_SBC_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSR_REG; OP_SBC(2, 4); } TEMPLATE static u32 FASTCALL OP_SBC_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ASR_IMM; OP_SBC(1, 3); @@ -1316,14 +1316,14 @@ TEMPLATE static u32 FASTCALL OP_SBC_ASR_IMM() TEMPLATE static u32 FASTCALL OP_SBC_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ASR_REG; OP_SBC(2, 4); } TEMPLATE static u32 FASTCALL OP_SBC_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ROR_IMM; OP_SBC(1, 3); @@ -1331,14 +1331,14 @@ TEMPLATE static u32 FASTCALL OP_SBC_ROR_IMM() TEMPLATE static u32 FASTCALL OP_SBC_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ROR_REG; OP_SBC(2, 4); } TEMPLATE static u32 FASTCALL OP_SBC_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; IMM_VALUE; OP_SBC(1, 3); } @@ -1365,7 +1365,7 @@ TEMPLATE static u32 FASTCALL OP_SBC_IMM_VAL() TEMPLATE static u32 FASTCALL OP_SBC_S_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; LSL_IMM; @@ -1374,7 +1374,7 @@ TEMPLATE static u32 FASTCALL OP_SBC_S_LSL_IMM() TEMPLATE static u32 FASTCALL OP_SBC_S_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; LSL_REG; OP_SBCS(3, 5); @@ -1382,7 +1382,7 @@ TEMPLATE static u32 FASTCALL OP_SBC_S_LSL_REG() TEMPLATE static u32 FASTCALL OP_SBC_S_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; LSR_IMM; @@ -1391,7 +1391,7 @@ TEMPLATE static u32 FASTCALL OP_SBC_S_LSR_IMM() TEMPLATE static u32 FASTCALL OP_SBC_S_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; LSR_REG; OP_SBCS(3, 5); @@ -1399,7 +1399,7 @@ TEMPLATE static u32 FASTCALL OP_SBC_S_LSR_REG() TEMPLATE static u32 FASTCALL OP_SBC_S_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; ASR_IMM; @@ -1408,7 +1408,7 @@ TEMPLATE static u32 FASTCALL OP_SBC_S_ASR_IMM() TEMPLATE static u32 FASTCALL OP_SBC_S_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; ASR_REG; OP_SBCS(3, 5); @@ -1416,7 +1416,7 @@ TEMPLATE static u32 FASTCALL OP_SBC_S_ASR_REG() TEMPLATE static u32 FASTCALL OP_SBC_S_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; ROR_IMM; @@ -1425,7 +1425,7 @@ TEMPLATE static u32 FASTCALL OP_SBC_S_ROR_IMM() TEMPLATE static u32 FASTCALL OP_SBC_S_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; ROR_REG; OP_SBCS(3, 5); @@ -1433,7 +1433,7 @@ TEMPLATE static u32 FASTCALL OP_SBC_S_ROR_REG() TEMPLATE static u32 FASTCALL OP_SBC_S_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; IMM_VALUE; OP_SBCS(2, 4); @@ -1451,7 +1451,7 @@ TEMPLATE static u32 FASTCALL OP_SBC_S_IMM_VAL() TEMPLATE static u32 FASTCALL OP_RSC_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSL_IMM; OP_RSC(1, 3); @@ -1459,14 +1459,14 @@ TEMPLATE static u32 FASTCALL OP_RSC_LSL_IMM() TEMPLATE static u32 FASTCALL OP_RSC_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSL_REG; OP_RSC(2, 4); } TEMPLATE static u32 FASTCALL OP_RSC_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSR_IMM; OP_RSC(1, 3); @@ -1474,14 +1474,14 @@ TEMPLATE static u32 FASTCALL OP_RSC_LSR_IMM() TEMPLATE static u32 FASTCALL OP_RSC_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSR_REG; OP_RSC(2, 4); } TEMPLATE static u32 FASTCALL OP_RSC_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ASR_IMM; OP_RSC(1, 3); @@ -1489,14 +1489,14 @@ TEMPLATE static u32 FASTCALL OP_RSC_ASR_IMM() TEMPLATE static u32 FASTCALL OP_RSC_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ASR_REG; OP_RSC(2, 4); } TEMPLATE static u32 FASTCALL OP_RSC_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ROR_IMM; OP_RSC(1, 3); @@ -1504,14 +1504,14 @@ TEMPLATE static u32 FASTCALL OP_RSC_ROR_IMM() TEMPLATE static u32 FASTCALL OP_RSC_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ROR_REG; OP_RSC(2, 4); } TEMPLATE static u32 FASTCALL OP_RSC_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; IMM_VALUE; OP_RSC(1, 3); } @@ -1538,7 +1538,7 @@ TEMPLATE static u32 FASTCALL OP_RSC_IMM_VAL() TEMPLATE static u32 FASTCALL OP_RSC_S_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; LSL_IMM; @@ -1547,7 +1547,7 @@ TEMPLATE static u32 FASTCALL OP_RSC_S_LSL_IMM() TEMPLATE static u32 FASTCALL OP_RSC_S_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; LSL_REG; OP_RSCS(3,5); @@ -1555,7 +1555,7 @@ TEMPLATE static u32 FASTCALL OP_RSC_S_LSL_REG() TEMPLATE static u32 FASTCALL OP_RSC_S_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; LSR_IMM; @@ -1564,7 +1564,7 @@ TEMPLATE static u32 FASTCALL OP_RSC_S_LSR_IMM() TEMPLATE static u32 FASTCALL OP_RSC_S_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; LSR_REG; OP_RSCS(3,5); @@ -1572,7 +1572,7 @@ TEMPLATE static u32 FASTCALL OP_RSC_S_LSR_REG() TEMPLATE static u32 FASTCALL OP_RSC_S_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; ASR_IMM; @@ -1581,7 +1581,7 @@ TEMPLATE static u32 FASTCALL OP_RSC_S_ASR_IMM() TEMPLATE static u32 FASTCALL OP_RSC_S_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; ASR_REG; OP_RSCS(3,5); @@ -1589,7 +1589,7 @@ TEMPLATE static u32 FASTCALL OP_RSC_S_ASR_REG() TEMPLATE static u32 FASTCALL OP_RSC_S_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; u32 shift_op; ROR_IMM; @@ -1598,7 +1598,7 @@ TEMPLATE static u32 FASTCALL OP_RSC_S_ROR_IMM() TEMPLATE static u32 FASTCALL OP_RSC_S_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; ROR_REG; OP_RSCS(3,5); @@ -1606,7 +1606,7 @@ TEMPLATE static u32 FASTCALL OP_RSC_S_ROR_REG() TEMPLATE static u32 FASTCALL OP_RSC_S_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,16)]; IMM_VALUE; OP_RSCS(2,4); @@ -1625,63 +1625,63 @@ TEMPLATE static u32 FASTCALL OP_RSC_S_IMM_VAL() TEMPLATE static u32 FASTCALL OP_TST_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSL_IMM; OP_TST(1); } TEMPLATE static u32 FASTCALL OP_TST_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSL_REG; OP_TST(2); } TEMPLATE static u32 FASTCALL OP_TST_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSR_IMM; OP_TST(1); } TEMPLATE static u32 FASTCALL OP_TST_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSR_REG; OP_TST(2); } TEMPLATE static u32 FASTCALL OP_TST_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ASR_IMM; OP_TST(1); } TEMPLATE static u32 FASTCALL OP_TST_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ASR_REG; OP_TST(2); } TEMPLATE static u32 FASTCALL OP_TST_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ROR_IMM; OP_TST(1); } TEMPLATE static u32 FASTCALL OP_TST_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ROR_REG; OP_TST(2); } TEMPLATE static u32 FASTCALL OP_TST_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_IMM_VALUE; OP_TST(1); } @@ -1699,63 +1699,63 @@ TEMPLATE static u32 FASTCALL OP_TST_IMM_VAL() TEMPLATE static u32 FASTCALL OP_TEQ_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSL_IMM; OP_TEQ(1); } TEMPLATE static u32 FASTCALL OP_TEQ_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSL_REG; OP_TEQ(2); } TEMPLATE static u32 FASTCALL OP_TEQ_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSR_IMM; OP_TEQ(1); } TEMPLATE static u32 FASTCALL OP_TEQ_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSR_REG; OP_TEQ(2); } TEMPLATE static u32 FASTCALL OP_TEQ_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ASR_IMM; OP_TEQ(1); } TEMPLATE static u32 FASTCALL OP_TEQ_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ASR_REG; OP_TEQ(2); } TEMPLATE static u32 FASTCALL OP_TEQ_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ROR_IMM; OP_TEQ(1); } TEMPLATE static u32 FASTCALL OP_TEQ_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ROR_REG; OP_TEQ(2); } TEMPLATE static u32 FASTCALL OP_TEQ_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_IMM_VALUE; OP_TEQ(1); } @@ -1774,7 +1774,7 @@ TEMPLATE static u32 FASTCALL OP_TEQ_IMM_VAL() TEMPLATE static u32 FASTCALL OP_CMP_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSL_IMM; OP_CMP(1); @@ -1782,14 +1782,14 @@ TEMPLATE static u32 FASTCALL OP_CMP_LSL_IMM() TEMPLATE static u32 FASTCALL OP_CMP_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSL_REG; OP_CMP(2); } TEMPLATE static u32 FASTCALL OP_CMP_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSR_IMM; OP_CMP(1); @@ -1797,14 +1797,14 @@ TEMPLATE static u32 FASTCALL OP_CMP_LSR_IMM() TEMPLATE static u32 FASTCALL OP_CMP_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSR_REG; OP_CMP(2); } TEMPLATE static u32 FASTCALL OP_CMP_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ASR_IMM; OP_CMP(1); @@ -1812,14 +1812,14 @@ TEMPLATE static u32 FASTCALL OP_CMP_ASR_IMM() TEMPLATE static u32 FASTCALL OP_CMP_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ASR_REG; OP_CMP(2); } TEMPLATE static u32 FASTCALL OP_CMP_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ROR_IMM; OP_CMP(1); @@ -1827,14 +1827,14 @@ TEMPLATE static u32 FASTCALL OP_CMP_ROR_IMM() TEMPLATE static u32 FASTCALL OP_CMP_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ROR_REG; OP_CMP(2); } TEMPLATE static u32 FASTCALL OP_CMP_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; IMM_VALUE; OP_CMP(1); } @@ -1853,7 +1853,7 @@ TEMPLATE static u32 FASTCALL OP_CMP_IMM_VAL() TEMPLATE static u32 FASTCALL OP_CMN_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSL_IMM; OP_CMN(1); @@ -1861,14 +1861,14 @@ TEMPLATE static u32 FASTCALL OP_CMN_LSL_IMM() TEMPLATE static u32 FASTCALL OP_CMN_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSL_REG; OP_CMN(2); } TEMPLATE static u32 FASTCALL OP_CMN_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSR_IMM; OP_CMN(1); @@ -1876,14 +1876,14 @@ TEMPLATE static u32 FASTCALL OP_CMN_LSR_IMM() TEMPLATE static u32 FASTCALL OP_CMN_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSR_REG; OP_CMN(2); } TEMPLATE static u32 FASTCALL OP_CMN_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ASR_IMM; OP_CMN(1); @@ -1891,14 +1891,14 @@ TEMPLATE static u32 FASTCALL OP_CMN_ASR_IMM() TEMPLATE static u32 FASTCALL OP_CMN_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ASR_REG; OP_CMN(2); } TEMPLATE static u32 FASTCALL OP_CMN_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ROR_IMM; OP_CMN(1); @@ -1906,14 +1906,14 @@ TEMPLATE static u32 FASTCALL OP_CMN_ROR_IMM() TEMPLATE static u32 FASTCALL OP_CMN_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ROR_REG; OP_CMN(2); } TEMPLATE static u32 FASTCALL OP_CMN_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; IMM_VALUE; OP_CMN(1); } @@ -1930,7 +1930,7 @@ TEMPLATE static u32 FASTCALL OP_CMN_IMM_VAL() TEMPLATE static u32 FASTCALL OP_ORR_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSL_IMM; OP_ORR(1, 3); @@ -1938,14 +1938,14 @@ TEMPLATE static u32 FASTCALL OP_ORR_LSL_IMM() TEMPLATE static u32 FASTCALL OP_ORR_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSL_REG; OP_ORR(2, 4); } TEMPLATE static u32 FASTCALL OP_ORR_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSR_IMM; OP_ORR(1, 3); @@ -1953,14 +1953,14 @@ TEMPLATE static u32 FASTCALL OP_ORR_LSR_IMM() TEMPLATE static u32 FASTCALL OP_ORR_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSR_REG; OP_ORR(2, 4); } TEMPLATE static u32 FASTCALL OP_ORR_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ASR_IMM; OP_ORR(1, 3); @@ -1968,14 +1968,14 @@ TEMPLATE static u32 FASTCALL OP_ORR_ASR_IMM() TEMPLATE static u32 FASTCALL OP_ORR_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ASR_REG; OP_ORR(2, 4); } TEMPLATE static u32 FASTCALL OP_ORR_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ROR_IMM; OP_ORR(1, 3); @@ -1983,14 +1983,14 @@ TEMPLATE static u32 FASTCALL OP_ORR_ROR_IMM() TEMPLATE static u32 FASTCALL OP_ORR_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ROR_REG; OP_ORR(2, 4); } TEMPLATE static u32 FASTCALL OP_ORR_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; IMM_VALUE; OP_ORR(1, 3); } @@ -2015,63 +2015,63 @@ TEMPLATE static u32 FASTCALL OP_ORR_IMM_VAL() TEMPLATE static u32 FASTCALL OP_ORR_S_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSL_IMM; OP_ORRS(2,4); } TEMPLATE static u32 FASTCALL OP_ORR_S_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSL_REG; OP_ORRS(3,5); } TEMPLATE static u32 FASTCALL OP_ORR_S_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSR_IMM; OP_ORRS(2,4); } TEMPLATE static u32 FASTCALL OP_ORR_S_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSR_REG; OP_ORRS(3,5); } TEMPLATE static u32 FASTCALL OP_ORR_S_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ASR_IMM; OP_ORRS(2,4); } TEMPLATE static u32 FASTCALL OP_ORR_S_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ASR_REG; OP_ORRS(3,5); } TEMPLATE static u32 FASTCALL OP_ORR_S_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ROR_IMM; OP_ORRS(2,4); } TEMPLATE static u32 FASTCALL OP_ORR_S_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ROR_REG; OP_ORRS(3,5); } TEMPLATE static u32 FASTCALL OP_ORR_S_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_IMM_VALUE; OP_ORRS(2,4); } @@ -2103,7 +2103,7 @@ TEMPLATE static u32 FASTCALL OP_ORR_S_IMM_VAL() TEMPLATE static u32 FASTCALL OP_MOV_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSL_IMM; OP_MOV(1,3); @@ -2111,7 +2111,7 @@ TEMPLATE static u32 FASTCALL OP_MOV_LSL_IMM() TEMPLATE static u32 FASTCALL OP_MOV_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSL_REG; if (REG_POS(i,0) == 15) shift_op += 4; OP_MOV(2,4); @@ -2119,7 +2119,7 @@ TEMPLATE static u32 FASTCALL OP_MOV_LSL_REG() TEMPLATE static u32 FASTCALL OP_MOV_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSR_IMM; OP_MOV(1,3); @@ -2127,7 +2127,7 @@ TEMPLATE static u32 FASTCALL OP_MOV_LSR_IMM() TEMPLATE static u32 FASTCALL OP_MOV_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSR_REG; if (REG_POS(i,0) == 15) shift_op += 4; OP_MOV(2,4); @@ -2135,7 +2135,7 @@ TEMPLATE static u32 FASTCALL OP_MOV_LSR_REG() TEMPLATE static u32 FASTCALL OP_MOV_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ASR_IMM; OP_MOV(1,3); @@ -2143,14 +2143,14 @@ TEMPLATE static u32 FASTCALL OP_MOV_ASR_IMM() TEMPLATE static u32 FASTCALL OP_MOV_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ASR_REG; OP_MOV(2,4); } TEMPLATE static u32 FASTCALL OP_MOV_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ROR_IMM; OP_MOV(2,4); @@ -2158,28 +2158,28 @@ TEMPLATE static u32 FASTCALL OP_MOV_ROR_IMM() TEMPLATE static u32 FASTCALL OP_MOV_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ROR_REG; OP_MOV(2,4); } TEMPLATE static u32 FASTCALL OP_MOV_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; IMM_VALUE; OP_MOV(1,3); } TEMPLATE static u32 FASTCALL OP_MOV_S_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSL_IMM; OP_MOV_S(2,4); } TEMPLATE static u32 FASTCALL OP_MOV_S_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSL_REG; if (REG_POS(i,0) == 15) shift_op += 4; OP_MOV_S(3,5); @@ -2187,14 +2187,14 @@ TEMPLATE static u32 FASTCALL OP_MOV_S_LSL_REG() TEMPLATE static u32 FASTCALL OP_MOV_S_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSR_IMM; OP_MOV_S(2,4); } TEMPLATE static u32 FASTCALL OP_MOV_S_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSR_REG; if (REG_POS(i,0) == 15) shift_op += 4; OP_MOV_S(3,5); @@ -2202,35 +2202,35 @@ TEMPLATE static u32 FASTCALL OP_MOV_S_LSR_REG() TEMPLATE static u32 FASTCALL OP_MOV_S_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ASR_IMM; OP_MOV_S(2,4); } TEMPLATE static u32 FASTCALL OP_MOV_S_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ASR_REG; OP_MOV_S(3,5); } TEMPLATE static u32 FASTCALL OP_MOV_S_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ROR_IMM; OP_MOV_S(2,4); } TEMPLATE static u32 FASTCALL OP_MOV_S_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ROR_REG; OP_MOV_S(3,5); } TEMPLATE static u32 FASTCALL OP_MOV_S_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_IMM_VALUE; OP_MOV_S(2,4); } @@ -2261,7 +2261,7 @@ TEMPLATE static u32 FASTCALL OP_MOV_S_IMM_VAL() TEMPLATE static u32 FASTCALL OP_BIC_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSL_IMM; OPP_BIC(1,3); @@ -2269,14 +2269,14 @@ TEMPLATE static u32 FASTCALL OP_BIC_LSL_IMM() TEMPLATE static u32 FASTCALL OP_BIC_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSL_REG; OPP_BIC(2,4); } TEMPLATE static u32 FASTCALL OP_BIC_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSR_IMM; OPP_BIC(1,3); @@ -2284,14 +2284,14 @@ TEMPLATE static u32 FASTCALL OP_BIC_LSR_IMM() TEMPLATE static u32 FASTCALL OP_BIC_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSR_REG; OPP_BIC(2,4); } TEMPLATE static u32 FASTCALL OP_BIC_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ASR_IMM; OPP_BIC(1,3); @@ -2299,14 +2299,14 @@ TEMPLATE static u32 FASTCALL OP_BIC_ASR_IMM() TEMPLATE static u32 FASTCALL OP_BIC_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ASR_REG; OPP_BIC(2,4); } TEMPLATE static u32 FASTCALL OP_BIC_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ROR_IMM; OPP_BIC(1,3); @@ -2314,77 +2314,77 @@ TEMPLATE static u32 FASTCALL OP_BIC_ROR_IMM() TEMPLATE static u32 FASTCALL OP_BIC_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ROR_REG; OPP_BIC(2,4); } TEMPLATE static u32 FASTCALL OP_BIC_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; IMM_VALUE; OPP_BIC(1,3); } TEMPLATE static u32 FASTCALL OP_BIC_S_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSL_IMM; OPP_BIC_S(2,4); } TEMPLATE static u32 FASTCALL OP_BIC_S_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSL_REG; OPP_BIC_S(3,5); } TEMPLATE static u32 FASTCALL OP_BIC_S_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSR_IMM; OPP_BIC_S(2,4); } TEMPLATE static u32 FASTCALL OP_BIC_S_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSR_REG; OPP_BIC_S(3,5); } TEMPLATE static u32 FASTCALL OP_BIC_S_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ASR_IMM; OPP_BIC_S(2,4); } TEMPLATE static u32 FASTCALL OP_BIC_S_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ASR_REG; OPP_BIC_S(3,5); } TEMPLATE static u32 FASTCALL OP_BIC_S_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ROR_IMM; OPP_BIC_S(2,4); } TEMPLATE static u32 FASTCALL OP_BIC_S_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ROR_REG; OPP_BIC_S(3,5); } TEMPLATE static u32 FASTCALL OP_BIC_S_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_IMM_VALUE; OPP_BIC_S(2,4); } @@ -2415,7 +2415,7 @@ TEMPLATE static u32 FASTCALL OP_BIC_S_IMM_VAL() TEMPLATE static u32 FASTCALL OP_MVN_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSL_IMM; OPP_MVN(1,3); @@ -2423,14 +2423,14 @@ TEMPLATE static u32 FASTCALL OP_MVN_LSL_IMM() TEMPLATE static u32 FASTCALL OP_MVN_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSL_REG; OPP_MVN(2,4); } TEMPLATE static u32 FASTCALL OP_MVN_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; LSR_IMM; OPP_MVN(1,3); @@ -2438,14 +2438,14 @@ TEMPLATE static u32 FASTCALL OP_MVN_LSR_IMM() TEMPLATE static u32 FASTCALL OP_MVN_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; LSR_REG; OPP_MVN(2,4); } TEMPLATE static u32 FASTCALL OP_MVN_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ASR_IMM; OPP_MVN(1,3); @@ -2453,14 +2453,14 @@ TEMPLATE static u32 FASTCALL OP_MVN_ASR_IMM() TEMPLATE static u32 FASTCALL OP_MVN_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ASR_REG; OPP_MVN(2,4); } TEMPLATE static u32 FASTCALL OP_MVN_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 shift_op; ROR_IMM; OPP_MVN(1,3); @@ -2468,77 +2468,77 @@ TEMPLATE static u32 FASTCALL OP_MVN_ROR_IMM() TEMPLATE static u32 FASTCALL OP_MVN_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; ROR_REG; OPP_MVN(2,4); } TEMPLATE static u32 FASTCALL OP_MVN_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; IMM_VALUE; OPP_MVN(1,3); } TEMPLATE static u32 FASTCALL OP_MVN_S_LSL_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSL_IMM; OPP_MVN_S(2,4); } TEMPLATE static u32 FASTCALL OP_MVN_S_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSL_REG; OPP_MVN_S(3,5); } TEMPLATE static u32 FASTCALL OP_MVN_S_LSR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSR_IMM; OPP_MVN_S(2,4); } TEMPLATE static u32 FASTCALL OP_MVN_S_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_LSR_REG; OPP_MVN_S(3,5); } TEMPLATE static u32 FASTCALL OP_MVN_S_ASR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ASR_IMM; OPP_MVN_S(2,4); } TEMPLATE static u32 FASTCALL OP_MVN_S_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ASR_REG; OPP_MVN_S(3,5); } TEMPLATE static u32 FASTCALL OP_MVN_S_ROR_IMM() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ROR_IMM; OPP_MVN_S(2,4); } TEMPLATE static u32 FASTCALL OP_MVN_S_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_ROR_REG; OPP_MVN_S(3,5); } TEMPLATE static u32 FASTCALL OP_MVN_S_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; S_IMM_VALUE; OPP_MVN_S(2,4); } @@ -2557,7 +2557,7 @@ TEMPLATE static u32 FASTCALL OP_MVN_S_IMM_VAL() TEMPLATE static u32 FASTCALL OP_MUL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,16)] = cpu->R[REG_POS(i,8)] * v; OPP_M(5,2); @@ -2565,7 +2565,7 @@ TEMPLATE static u32 FASTCALL OP_MUL() TEMPLATE static u32 FASTCALL OP_MLA() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,0)]; u32 a = cpu->R[REG_POS(i,8)]; u32 b = cpu->R[REG_POS(i,12)]; @@ -2576,7 +2576,7 @@ TEMPLATE static u32 FASTCALL OP_MLA() TEMPLATE static u32 FASTCALL OP_MUL_S() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,16)] = cpu->R[REG_POS(i,8)] * v; @@ -2588,7 +2588,7 @@ TEMPLATE static u32 FASTCALL OP_MUL_S() TEMPLATE static u32 FASTCALL OP_MLA_S() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,16)] = cpu->R[REG_POS(i,8)] * v + cpu->R[REG_POS(i,12)]; cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]); @@ -2600,7 +2600,7 @@ TEMPLATE static u32 FASTCALL OP_MLA_S() TEMPLATE static u32 FASTCALL OP_UMULL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,0)]; u64 res = (u64)v * (u64)cpu->R[REG_POS(i,8)]; @@ -2612,7 +2612,7 @@ TEMPLATE static u32 FASTCALL OP_UMULL() TEMPLATE static u32 FASTCALL OP_UMLAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,0)]; u64 res = (u64)v * (u64)cpu->R[REG_POS(i,8)] + (u64)cpu->R[REG_POS(i,12)]; @@ -2624,7 +2624,7 @@ TEMPLATE static u32 FASTCALL OP_UMLAL() TEMPLATE static u32 FASTCALL OP_UMULL_S() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,0)]; u64 res = (u64)v * (u64)cpu->R[REG_POS(i,8)]; @@ -2639,7 +2639,7 @@ TEMPLATE static u32 FASTCALL OP_UMULL_S() TEMPLATE static u32 FASTCALL OP_UMLAL_S() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_POS(i,0)]; u64 res = (u64)v * (u64)cpu->R[REG_POS(i,8)] + (u64)cpu->R[REG_POS(i,12)]; @@ -2656,7 +2656,7 @@ TEMPLATE static u32 FASTCALL OP_UMLAL_S() TEMPLATE static u32 FASTCALL OP_SMULL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; s64 v = (s32)cpu->R[REG_POS(i,0)]; s64 b = (s32)cpu->R[REG_POS(i,8)]; s64 res = v * b; @@ -2671,7 +2671,7 @@ TEMPLATE static u32 FASTCALL OP_SMULL() TEMPLATE static u32 FASTCALL OP_SMLAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; s64 v = (s32)cpu->R[REG_POS(i,0)]; s64 b = (s32)cpu->R[REG_POS(i,8)]; @@ -2691,7 +2691,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAL() TEMPLATE static u32 FASTCALL OP_SMULL_S() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; s64 v = (s32)cpu->R[REG_POS(i,0)]; s64 b = (s32)cpu->R[REG_POS(i,8)]; s64 res = v * b; @@ -2709,7 +2709,7 @@ TEMPLATE static u32 FASTCALL OP_SMULL_S() TEMPLATE static u32 FASTCALL OP_SMLAL_S() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; s64 v = (s32)cpu->R[REG_POS(i,0)]; s64 b = (s32)cpu->R[REG_POS(i,8)]; s64 res = v * b + (u64)cpu->R[REG_POS(i,12)]; @@ -2729,498 +2729,498 @@ TEMPLATE static u32 FASTCALL OP_SMLAL_S() TEMPLATE static u32 FASTCALL OP_SWP() { - u32 i = cpu->instruction; + u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; u32 tmp = ROR(READ32(cpu->mem_if->data, adr), ((cpu->R[REG_POS(i,16)]&3)<<3)); WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,0)]); cpu->R[REG_POS(i,12)] = tmp; - return 4 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]*2; + return 4 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]*2; } TEMPLATE static u32 FASTCALL OP_SWPB() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; u8 tmp = READ8(cpu->mem_if->data, adr); WRITE8(cpu->mem_if->data, adr, (u8)(cpu->R[REG_POS(i,0)]&0xFF)); cpu->R[REG_POS(i,12)] = tmp; - return 4 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]*2; + return 4 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]*2; } //------------LDRH----------------------------- TEMPLATE static u32 FASTCALL OP_LDRH_P_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRH_M_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRH_P_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRH_M_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_P_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_M_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_P_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] =(u32)READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_M_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_P_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] += IMM_OFF; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_M_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] -= IMM_OFF; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_P_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_M_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } //------------STRH----------------------------- TEMPLATE static u32 FASTCALL OP_STRH_P_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRH_M_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRH_P_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRH_M_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_P_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; cpu->R[REG_POS(i,16)] = adr; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_M_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_P_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_M_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_P_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] += IMM_OFF; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_M_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] -= IMM_OFF; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_P_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_M_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } //----------------LDRSH-------------------------- TEMPLATE static u32 FASTCALL OP_LDRSH_P_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSH_M_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSH_P_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSH_M_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_P_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_M_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_P_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_M_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_P_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] += IMM_OFF; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_M_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] -= IMM_OFF; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_P_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_M_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } //----------------------LDRSB---------------------- TEMPLATE static u32 FASTCALL OP_LDRSB_P_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSB_M_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSB_P_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSB_M_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_P_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_M_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_P_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_M_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_P_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] += IMM_OFF; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_M_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] -= IMM_OFF; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_P_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_M_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } //--------------MRS-------------------------------- @@ -3243,7 +3243,7 @@ TEMPLATE static u32 FASTCALL OP_MRS_SPSR() TEMPLATE static u32 FASTCALL OP_MSR_CPSR() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 operand = cpu->R[REG_POS(i,0)]; if(cpu->CPSR.bits.mode!=USR) @@ -3266,7 +3266,7 @@ TEMPLATE static u32 FASTCALL OP_MSR_CPSR() TEMPLATE static u32 FASTCALL OP_MSR_SPSR() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 operand = cpu->R[REG_POS(i,0)]; if(cpu->CPSR.bits.mode!=USR) @@ -3288,7 +3288,7 @@ TEMPLATE static u32 FASTCALL OP_MSR_SPSR() TEMPLATE static u32 FASTCALL OP_MSR_CPSR_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; IMM_VALUE; if(cpu->CPSR.bits.mode!=USR) @@ -3314,7 +3314,7 @@ TEMPLATE static u32 FASTCALL OP_MSR_CPSR_IMM_VAL() TEMPLATE static u32 FASTCALL OP_MSR_SPSR_IMM_VAL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; IMM_VALUE; if(cpu->CPSR.bits.mode!=USR) @@ -3401,7 +3401,7 @@ u8 CLZ_TAB[16]= TEMPLATE static u32 FASTCALL OP_CLZ() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 Rm = cpu->R[REG_POS(i,0)]; u32 pos; @@ -3436,7 +3436,7 @@ TEMPLATE static u32 FASTCALL OP_CLZ() TEMPLATE static u32 FASTCALL OP_QADD() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 res = cpu->R[REG_POS(i,16)]+cpu->R[REG_POS(i,0)]; LOG("spe add\r\n"); @@ -3458,7 +3458,7 @@ TEMPLATE static u32 FASTCALL OP_QADD() TEMPLATE static u32 FASTCALL OP_QSUB() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 res = cpu->R[REG_POS(i,0)]-cpu->R[REG_POS(i,16)]; LOG("spe add\r\n"); @@ -3480,7 +3480,7 @@ TEMPLATE static u32 FASTCALL OP_QSUB() TEMPLATE static u32 FASTCALL OP_QDADD() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 mul = cpu->R[REG_POS(i,16)]<<1; u32 res; @@ -3511,7 +3511,7 @@ TEMPLATE static u32 FASTCALL OP_QDADD() TEMPLATE static u32 FASTCALL OP_QDSUB() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 mul = cpu->R[REG_POS(i,16)]<<1; u32 res; @@ -3547,7 +3547,7 @@ TEMPLATE static u32 FASTCALL OP_QDSUB() TEMPLATE static u32 FASTCALL OP_SMUL_B_B() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->R[REG_POS(i,16)] = (u32)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); @@ -3556,7 +3556,7 @@ TEMPLATE static u32 FASTCALL OP_SMUL_B_B() TEMPLATE static u32 FASTCALL OP_SMUL_B_T() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->R[REG_POS(i,16)] = (u32)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); @@ -3565,7 +3565,7 @@ TEMPLATE static u32 FASTCALL OP_SMUL_B_T() TEMPLATE static u32 FASTCALL OP_SMUL_T_B() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->R[REG_POS(i,16)] = (u32)(HWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); @@ -3574,7 +3574,7 @@ TEMPLATE static u32 FASTCALL OP_SMUL_T_B() TEMPLATE static u32 FASTCALL OP_SMUL_T_T() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->R[REG_POS(i,16)] = (u32)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); @@ -3585,7 +3585,7 @@ TEMPLATE static u32 FASTCALL OP_SMUL_T_T() TEMPLATE static u32 FASTCALL OP_SMLA_B_B() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 tmp = (u32)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); u32 a = cpu->R[REG_POS(i,12)]; @@ -3600,7 +3600,7 @@ TEMPLATE static u32 FASTCALL OP_SMLA_B_B() TEMPLATE static u32 FASTCALL OP_SMLA_B_T() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 tmp = (u32)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); u32 a = cpu->R[REG_POS(i,12)]; @@ -3615,7 +3615,7 @@ TEMPLATE static u32 FASTCALL OP_SMLA_B_T() TEMPLATE static u32 FASTCALL OP_SMLA_T_B() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 tmp = (u32)(HWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); u32 a = cpu->R[REG_POS(i,12)]; @@ -3630,7 +3630,7 @@ TEMPLATE static u32 FASTCALL OP_SMLA_T_B() TEMPLATE static u32 FASTCALL OP_SMLA_T_T() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 tmp = (u32)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); u32 a = cpu->R[REG_POS(i,12)]; @@ -3647,7 +3647,7 @@ TEMPLATE static u32 FASTCALL OP_SMLA_T_T() TEMPLATE static u32 FASTCALL OP_SMLAL_B_B() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; s64 tmp = (s64)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); u64 res = (u64)tmp + cpu->R[REG_POS(i,12)]; @@ -3661,7 +3661,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAL_B_B() TEMPLATE static u32 FASTCALL OP_SMLAL_B_T() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; s64 tmp = (s64)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); u64 res = (u64)tmp + cpu->R[REG_POS(i,12)]; @@ -3675,7 +3675,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAL_B_T() TEMPLATE static u32 FASTCALL OP_SMLAL_T_B() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; s64 tmp = (s64)(HWORD(cpu->R[REG_POS(i,0)])* (s64)LWORD(cpu->R[REG_POS(i,8)])); u64 res = (u64)tmp + cpu->R[REG_POS(i,12)]; @@ -3689,7 +3689,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAL_T_B() TEMPLATE static u32 FASTCALL OP_SMLAL_T_T() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; s64 tmp = (s64)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); u64 res = (u64)tmp + cpu->R[REG_POS(i,12)]; @@ -3705,7 +3705,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAL_T_T() TEMPLATE static u32 FASTCALL OP_SMULW_B() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; s64 tmp = (s64)LWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); //LOG("SMULWB %08X * %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], ((tmp>>16)&0xFFFFFFFF); @@ -3717,7 +3717,7 @@ TEMPLATE static u32 FASTCALL OP_SMULW_B() TEMPLATE static u32 FASTCALL OP_SMULW_T() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; s64 tmp = (s64)HWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); //LOG("SMULWT %08X * %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], ((tmp>>16)&0xFFFFFFFF)); @@ -3730,7 +3730,7 @@ TEMPLATE static u32 FASTCALL OP_SMULW_T() //--------------SMLAW------------------- TEMPLATE static u32 FASTCALL OP_SMLAW_B() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; s64 tmp = (s64)LWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); u32 a = cpu->R[REG_POS(i,12)]; @@ -3740,7 +3740,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAW_B() cpu->R[REG_POS(i,16)] = tmp + a; - if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)])) + if(SIGNED_OVERFLOW((u32)tmp, a, cpu->R[REG_POS(i,16)])) cpu->CPSR.bits.Q = 1; return 2; @@ -3748,7 +3748,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAW_B() TEMPLATE static u32 FASTCALL OP_SMLAW_T() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; s64 tmp = (s64)HWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); u32 a = cpu->R[REG_POS(i,12)]; @@ -3757,7 +3757,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAW_T() tmp = ((tmp>>16)&0xFFFFFFFF); cpu->R[REG_POS(i,16)] = tmp + a; - if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)])) + if(SIGNED_OVERFLOW((u32)tmp, a, cpu->R[REG_POS(i,16)])) cpu->CPSR.bits.Q = 1; return 2; @@ -3767,7 +3767,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAW_T() TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; u32 val = READ32(cpu->mem_if->data, adr); @@ -3779,16 +3779,16 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF() cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; u32 val = READ32(cpu->mem_if->data, adr); @@ -3800,17 +3800,17 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF() cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -3826,17 +3826,17 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF() cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -3852,17 +3852,17 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF() cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -3878,17 +3878,17 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF() cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -3904,17 +3904,17 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF() cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -3930,17 +3930,17 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF() cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -3956,17 +3956,17 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF() cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -3982,17 +3982,17 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF() cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4008,18 +4008,18 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF() cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; u32 val = READ32(cpu->mem_if->data, adr); @@ -4032,18 +4032,18 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_PREIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; u32 val = READ32(cpu->mem_if->data, adr); @@ -4056,19 +4056,19 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF_PREIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4085,19 +4085,19 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_PREIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4114,19 +4114,19 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_PREIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4143,19 +4143,19 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_PREIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4172,19 +4172,19 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_PREIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4201,19 +4201,19 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_PREIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4230,19 +4230,19 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_PREIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4259,19 +4259,19 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_PREIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4288,18 +4288,18 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_PREIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; u32 val = READ32(cpu->mem_if->data, adr); @@ -4312,19 +4312,19 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } //------------------------------------------------------------ TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND2() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; u32 val = READ32(cpu->mem_if->data, adr); @@ -4338,7 +4338,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND2() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } old = armcpu_switchMode(cpu, USR); @@ -4347,14 +4347,14 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND2() cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } //------------------------------------------------------------ TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; u32 val = READ32(cpu->mem_if->data, adr); @@ -4367,18 +4367,18 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF_POSTIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4395,18 +4395,18 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_POSTIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr + shift_op; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4423,18 +4423,18 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_POSTIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr - shift_op; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4451,18 +4451,18 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_POSTIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr + shift_op; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4479,18 +4479,18 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_POSTIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr - shift_op; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4507,18 +4507,18 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_POSTIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr + shift_op; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4535,18 +4535,18 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_POSTIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr - shift_op; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4563,18 +4563,18 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_POSTIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr + shift_op; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4591,40 +4591,40 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_POSTIND() cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; cpu->next_instruction = cpu->R[15]; cpu->R[REG_POS(i,16)] = adr - shift_op; - return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } //-----------------LDRB------------------------------------------- TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; u32 val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_M_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; u32 val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4633,12 +4633,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF() val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4647,12 +4647,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF() val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4661,12 +4661,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF() val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4675,12 +4675,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF() val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4689,12 +4689,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF() val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4703,12 +4703,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF() val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4717,12 +4717,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF() val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4732,12 +4732,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF() cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; u32 val = READ8(cpu->mem_if->data, adr); @@ -4745,24 +4745,24 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF_PREIND() cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_M_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; u32 val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4774,12 +4774,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_PREIND() cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4790,12 +4790,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_PREIND() cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4805,12 +4805,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_PREIND() cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4820,12 +4820,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_PREIND() cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4835,12 +4835,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_PREIND() cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4850,12 +4850,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_PREIND() cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4865,12 +4865,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_PREIND() cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4880,34 +4880,34 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_PREIND() cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; u32 val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_M_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; u32 val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4917,12 +4917,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_POSTIND() cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4932,12 +4932,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_POSTIND() cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4947,12 +4947,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_POSTIND() cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4962,12 +4962,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_POSTIND() cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4977,12 +4977,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_POSTIND() cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -4992,12 +4992,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_POSTIND() cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -5007,12 +5007,12 @@ TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_POSTIND() cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 val; u32 shift_op; @@ -5022,118 +5022,118 @@ TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_POSTIND() cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } //----------------------STR-------------------------------- TEMPLATE static u32 FASTCALL OP_STR_P_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); // execute = false; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ROR_IMM; @@ -5141,32 +5141,32 @@ TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF() WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_P_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSL_IMM; @@ -5174,12 +5174,12 @@ TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_PREIND() WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSL_IMM; @@ -5187,12 +5187,12 @@ TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_PREIND() WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSR_IMM; @@ -5200,12 +5200,12 @@ TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_PREIND() WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSR_IMM; @@ -5213,12 +5213,12 @@ TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_PREIND() WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ASR_IMM; @@ -5226,12 +5226,12 @@ TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_PREIND() WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ASR_IMM; @@ -5239,12 +5239,12 @@ TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_PREIND() WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ROR_IMM; @@ -5252,12 +5252,12 @@ TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_PREIND() WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ROR_IMM; @@ -5265,32 +5265,32 @@ TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_PREIND() WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_P_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSL_IMM; @@ -5298,12 +5298,12 @@ TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_POSTIND() WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSL_IMM; @@ -5311,12 +5311,12 @@ TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_POSTIND() WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSR_IMM; @@ -5324,12 +5324,12 @@ TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_POSTIND() WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSR_IMM; @@ -5337,12 +5337,12 @@ TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_POSTIND() WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ASR_IMM; @@ -5350,12 +5350,12 @@ TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_POSTIND() WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ASR_IMM; @@ -5363,12 +5363,12 @@ TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_POSTIND() WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ROR_IMM; @@ -5376,12 +5376,12 @@ TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_POSTIND() WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ROR_IMM; @@ -5389,148 +5389,148 @@ TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_POSTIND() WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } //-----------------------STRB------------------------------------- TEMPLATE static u32 FASTCALL OP_STRB_P_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_M_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_P_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; WRITE8(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_M_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSL_IMM; @@ -5538,12 +5538,12 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_PREIND() WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSL_IMM; @@ -5551,12 +5551,12 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_PREIND() WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSR_IMM; @@ -5564,12 +5564,12 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_PREIND() WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSR_IMM; @@ -5577,12 +5577,12 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_PREIND() WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ASR_IMM; @@ -5590,12 +5590,12 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_PREIND() WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ASR_IMM; @@ -5603,12 +5603,12 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_PREIND() WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ROR_IMM; @@ -5616,12 +5616,12 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_PREIND() WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_PREIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ROR_IMM; @@ -5629,32 +5629,32 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_PREIND() WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_P_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_M_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSL_IMM; @@ -5662,12 +5662,12 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_POSTIND() WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSL_IMM; @@ -5675,12 +5675,12 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_POSTIND() WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSR_IMM; @@ -5688,12 +5688,12 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_POSTIND() WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; LSR_IMM; @@ -5701,12 +5701,12 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_POSTIND() WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ASR_IMM; @@ -5714,12 +5714,12 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_POSTIND() WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ASR_IMM; @@ -5727,12 +5727,12 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_POSTIND() WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ROR_IMM; @@ -5740,12 +5740,12 @@ TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_POSTIND() WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr; u32 shift_op; ROR_IMM; @@ -5753,7 +5753,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND() WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } //-----------------------LDRBT------------------------------------- @@ -5777,7 +5777,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_P_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRBT_M_IMM_OFF_POSTIND() @@ -5803,7 +5803,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_M_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRBT_P_REG_OFF_POSTIND() @@ -5829,7 +5829,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_P_REG_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRBT_P_LSL_IMM_OFF_POSTIND() @@ -5856,7 +5856,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_P_LSL_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRBT_M_LSL_IMM_OFF_POSTIND() @@ -5884,7 +5884,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_M_LSL_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRBT_P_LSR_IMM_OFF_POSTIND() @@ -5912,7 +5912,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_P_LSR_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRBT_M_LSR_IMM_OFF_POSTIND() @@ -5940,7 +5940,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_M_LSR_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRBT_P_ASR_IMM_OFF_POSTIND() @@ -5968,7 +5968,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_P_ASR_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRBT_M_ASR_IMM_OFF_POSTIND() @@ -5996,7 +5996,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_M_ASR_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRBT_P_ROR_IMM_OFF_POSTIND() @@ -6024,7 +6024,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_P_ROR_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRBT_M_ROR_IMM_OFF_POSTIND() @@ -6052,7 +6052,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_M_ROR_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } //----------------------STRBT---------------------------- @@ -6076,7 +6076,7 @@ TEMPLATE static u32 FASTCALL OP_STRBT_P_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRBT_M_IMM_OFF_POSTIND() @@ -6098,7 +6098,7 @@ TEMPLATE static u32 FASTCALL OP_STRBT_M_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRBT_P_REG_OFF_POSTIND() @@ -6120,7 +6120,7 @@ TEMPLATE static u32 FASTCALL OP_STRBT_P_REG_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRBT_M_REG_OFF_POSTIND() @@ -6142,7 +6142,7 @@ TEMPLATE static u32 FASTCALL OP_STRBT_M_REG_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRBT_P_LSL_IMM_OFF_POSTIND() @@ -6166,7 +6166,7 @@ TEMPLATE static u32 FASTCALL OP_STRBT_P_LSL_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRBT_M_LSL_IMM_OFF_POSTIND() @@ -6190,7 +6190,7 @@ TEMPLATE static u32 FASTCALL OP_STRBT_M_LSL_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRBT_P_LSR_IMM_OFF_POSTIND() @@ -6214,7 +6214,7 @@ TEMPLATE static u32 FASTCALL OP_STRBT_P_LSR_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRBT_M_LSR_IMM_OFF_POSTIND() @@ -6238,7 +6238,7 @@ TEMPLATE static u32 FASTCALL OP_STRBT_M_LSR_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRBT_P_ASR_IMM_OFF_POSTIND() @@ -6262,7 +6262,7 @@ TEMPLATE static u32 FASTCALL OP_STRBT_P_ASR_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRBT_M_ASR_IMM_OFF_POSTIND() @@ -6286,7 +6286,7 @@ TEMPLATE static u32 FASTCALL OP_STRBT_M_ASR_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRBT_P_ROR_IMM_OFF_POSTIND() @@ -6310,7 +6310,7 @@ TEMPLATE static u32 FASTCALL OP_STRBT_P_ROR_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRBT_M_ROR_IMM_OFF_POSTIND() @@ -6334,7 +6334,7 @@ TEMPLATE static u32 FASTCALL OP_STRBT_M_ROR_IMM_OFF_POSTIND() armcpu_switchMode(cpu, oldmode); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } //---------------------LDM----------------------------- @@ -6369,12 +6369,12 @@ TEMPLATE static u32 FASTCALL OP_STRBT_M_ROR_IMM_OFF_POSTIND() TEMPLATE static u32 FASTCALL OP_LDMIA() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 c = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 * registres = cpu->R; - u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID]; + TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; OP_L_IA(0, start); OP_L_IA(1, start); @@ -6407,12 +6407,12 @@ TEMPLATE static u32 FASTCALL OP_LDMIA() TEMPLATE static u32 FASTCALL OP_LDMIB() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 c = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 * registres = cpu->R; - u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID]; + TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; OP_L_IB(0, start); OP_L_IB(1, start); @@ -6447,12 +6447,12 @@ TEMPLATE static u32 FASTCALL OP_LDMIB() TEMPLATE static u32 FASTCALL OP_LDMDA() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 c = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 * registres = cpu->R; - u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID]; + TWaitState * waitState = MMU.MMU_WAIT32[PROCNUM]; if(BIT15(i)) { @@ -6485,12 +6485,12 @@ TEMPLATE static u32 FASTCALL OP_LDMDA() TEMPLATE static u32 FASTCALL OP_LDMDB() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 c = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 * registres = cpu->R; - u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID]; + TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; if(BIT15(i)) { @@ -6524,12 +6524,13 @@ TEMPLATE static u32 FASTCALL OP_LDMDB() TEMPLATE static u32 FASTCALL OP_LDMIA_W() { - u32 i = cpu->instruction, c = 0; + const u32 &i = cpu->instruction; + u32 c = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF; u32 * registres = cpu->R; - u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID]; + TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; OP_L_IA(0, start); OP_L_IA(1, start); @@ -6569,12 +6570,13 @@ TEMPLATE static u32 FASTCALL OP_LDMIA_W() TEMPLATE static u32 FASTCALL OP_LDMIB_W() { - u32 i = cpu->instruction, c = 0; + const u32 &i = cpu->instruction; + u32 c = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF; u32 * registres = cpu->R; - u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID]; + TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; OP_L_IB(0, start); OP_L_IB(1, start); @@ -6616,12 +6618,13 @@ TEMPLATE static u32 FASTCALL OP_LDMIB_W() TEMPLATE static u32 FASTCALL OP_LDMDA_W() { - u32 i = cpu->instruction, c = 0; + const u32 &i = cpu->instruction; + u32 c = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF; u32 * registres = cpu->R; - u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID]; + TWaitState * waitState = MMU.MMU_WAIT32[PROCNUM]; if(BIT15(i)) { @@ -6661,11 +6664,12 @@ TEMPLATE static u32 FASTCALL OP_LDMDA_W() TEMPLATE static u32 FASTCALL OP_LDMDB_W() { - u32 i = cpu->instruction, c = 0; + const u32 &i = cpu->instruction; + u32 c = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF; u32 * registres = cpu->R; - u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID]; + TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; if(BIT15(i)) { @@ -6706,14 +6710,14 @@ TEMPLATE static u32 FASTCALL OP_LDMDB_W() TEMPLATE static u32 FASTCALL OP_LDMIA2() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 oldmode = 0; u32 c = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 * registres; - u32 * waitState; + TWaitState* waitState; if(BIT15(i)==0) { @@ -6723,7 +6727,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2() } registres = cpu->R; - waitState = MMU.MMU_WAIT32[cpu->proc_ID]; + waitState = MMU.MMU_WAIT32[PROCNUM]; OP_L_IA(0, start); OP_L_IA(1, start); @@ -6756,20 +6760,20 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2() cpu->CPSR=SPSR; //start += 4; cpu->next_instruction = cpu->R[15]; - c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; } return c + 2; } TEMPLATE static u32 FASTCALL OP_LDMIB2() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 oldmode = 0; u32 c = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 * registres; - u32 * waitState; + TWaitState* waitState; //execute = FALSE; LOG("Untested opcode: OP_LDMIB2\n"); @@ -6781,7 +6785,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2() } registres = cpu->R; - waitState = MMU.MMU_WAIT32[cpu->proc_ID]; + waitState = MMU.MMU_WAIT32[PROCNUM]; OP_L_IB(0, start); OP_L_IB(1, start); @@ -6821,12 +6825,12 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2() TEMPLATE static u32 FASTCALL OP_LDMDA2() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 oldmode = 0; u32 c = 0; u32 * registres; - u32 * waitState; + TWaitState* waitState; u32 start = cpu->R[REG_POS(i,16)]; //execute = FALSE; @@ -6840,7 +6844,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDA2() } registres = cpu->R; - waitState = MMU.MMU_WAIT32[cpu->proc_ID]; + waitState = MMU.MMU_WAIT32[PROCNUM]; if(BIT15(i)) { @@ -6884,12 +6888,12 @@ TEMPLATE static u32 FASTCALL OP_LDMDA2() TEMPLATE static u32 FASTCALL OP_LDMDB2() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 oldmode = 0; u32 c = 0; u32 * registres; - u32 * waitState; + TWaitState* waitState; u32 start = cpu->R[REG_POS(i,16)]; if(BIT15(i)==0) @@ -6900,7 +6904,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDB2() } registres = cpu->R; - waitState = MMU.MMU_WAIT32[cpu->proc_ID]; + waitState = MMU.MMU_WAIT32[PROCNUM]; if(BIT15(i)) { @@ -6945,13 +6949,13 @@ TEMPLATE static u32 FASTCALL OP_LDMDB2() TEMPLATE static u32 FASTCALL OP_LDMIA2_W() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 c = 0; u32 oldmode = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 * registres; - u32 * waitState; + TWaitState* waitState; u32 tmp; Status_Reg SPSR; // execute = FALSE; @@ -6963,7 +6967,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2_W() } registres = cpu->R; - waitState = MMU.MMU_WAIT32[cpu->proc_ID]; + waitState = MMU.MMU_WAIT32[PROCNUM]; OP_L_IA(0, start); OP_L_IA(1, start); @@ -7002,13 +7006,13 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2_W() TEMPLATE static u32 FASTCALL OP_LDMIB2_W() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 c = 0; u32 oldmode = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 * registres; - u32 * waitState; + TWaitState* waitState; u32 tmp; Status_Reg SPSR; @@ -7020,7 +7024,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2_W() } registres = cpu->R; - waitState = MMU.MMU_WAIT32[cpu->proc_ID]; + waitState = MMU.MMU_WAIT32[PROCNUM]; OP_L_IB(0, start); OP_L_IB(1, start); @@ -7061,13 +7065,13 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2_W() TEMPLATE static u32 FASTCALL OP_LDMDA2_W() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 c = 0; u32 oldmode = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 * registres; - u32 * waitState; + TWaitState * waitState; Status_Reg SPSR; // execute = FALSE; if(BIT15(i)==0) @@ -7078,7 +7082,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDA2_W() } registres = cpu->R; - waitState = MMU.MMU_WAIT32[cpu->proc_ID]; + waitState = MMU.MMU_WAIT32[PROCNUM]; if(BIT15(i)) { @@ -7121,13 +7125,13 @@ TEMPLATE static u32 FASTCALL OP_LDMDA2_W() TEMPLATE static u32 FASTCALL OP_LDMDB2_W() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 c = 0; u32 oldmode = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 * registres; - u32 * waitState; + TWaitState* waitState; Status_Reg SPSR; // execute = FALSE; if(BIT15(i)==0) @@ -7138,7 +7142,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDB2_W() } registres = cpu->R; - waitState = MMU.MMU_WAIT32[cpu->proc_ID]; + waitState = MMU.MMU_WAIT32[PROCNUM]; if(BIT15(i)) { @@ -7185,7 +7189,8 @@ TEMPLATE static u32 FASTCALL OP_LDMDB2_W() TEMPLATE static u32 FASTCALL OP_STMIA() { - u32 i = cpu->instruction, c = 0, b; + const u32 &i = cpu->instruction; + u32 c = 0, b; u32 start = cpu->R[REG_POS(i,16)]; for(b=0; b<16; ++b) @@ -7193,7 +7198,7 @@ TEMPLATE static u32 FASTCALL OP_STMIA() if(BIT_N(i, b)) { WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; start += 4; } } @@ -7202,7 +7207,8 @@ TEMPLATE static u32 FASTCALL OP_STMIA() TEMPLATE static u32 FASTCALL OP_STMIB() { - u32 i = cpu->instruction, c = 0, b; + const u32 &i = cpu->instruction; + u32 c = 0, b; u32 start = cpu->R[REG_POS(i,16)]; for(b=0; b<16; ++b) @@ -7211,7 +7217,7 @@ TEMPLATE static u32 FASTCALL OP_STMIB() { start += 4; WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; } } return c + 1; @@ -7219,7 +7225,8 @@ TEMPLATE static u32 FASTCALL OP_STMIB() TEMPLATE static u32 FASTCALL OP_STMDA() { - u32 i = cpu->instruction, c = 0, b; + const u32 &i = cpu->instruction; + u32 c = 0, b; u32 start = cpu->R[REG_POS(i,16)]; for(b=0; b<16; ++b) @@ -7227,7 +7234,7 @@ TEMPLATE static u32 FASTCALL OP_STMDA() if(BIT_N(i, 15-b)) { WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; start -= 4; } } @@ -7236,7 +7243,8 @@ TEMPLATE static u32 FASTCALL OP_STMDA() TEMPLATE static u32 FASTCALL OP_STMDB() { - u32 i = cpu->instruction, c = 0, b; + const u32 &i = cpu->instruction; + u32 c = 0, b; u32 start = cpu->R[REG_POS(i,16)]; for(b=0; b<16; ++b) @@ -7245,7 +7253,7 @@ TEMPLATE static u32 FASTCALL OP_STMDB() { start -= 4; WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; } } return c + 1; @@ -7253,7 +7261,8 @@ TEMPLATE static u32 FASTCALL OP_STMDB() TEMPLATE static u32 FASTCALL OP_STMIA_W() { - u32 i = cpu->instruction, c = 0, b; + const u32 &i = cpu->instruction; + u32 c = 0, b; u32 start = cpu->R[REG_POS(i,16)]; for(b=0; b<16; ++b) @@ -7261,7 +7270,7 @@ TEMPLATE static u32 FASTCALL OP_STMIA_W() if(BIT_N(i, b)) { WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; start += 4; } } @@ -7272,7 +7281,8 @@ TEMPLATE static u32 FASTCALL OP_STMIA_W() TEMPLATE static u32 FASTCALL OP_STMIB_W() { - u32 i = cpu->instruction, c = 0, b; + const u32 &i = cpu->instruction; + u32 c = 0, b; u32 start = cpu->R[REG_POS(i,16)]; for(b=0; b<16; ++b) @@ -7281,7 +7291,7 @@ TEMPLATE static u32 FASTCALL OP_STMIB_W() { start += 4; WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; } } cpu->R[REG_POS(i,16)] = start; @@ -7290,7 +7300,8 @@ TEMPLATE static u32 FASTCALL OP_STMIB_W() TEMPLATE static u32 FASTCALL OP_STMDA_W() { - u32 i = cpu->instruction, c = 0, b; + const u32 &i = cpu->instruction; + u32 c = 0, b; u32 start = cpu->R[REG_POS(i,16)]; for(b=0; b<16; ++b) @@ -7298,7 +7309,7 @@ TEMPLATE static u32 FASTCALL OP_STMDA_W() if(BIT_N(i, 15-b)) { WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; start -= 4; } } @@ -7309,7 +7320,8 @@ TEMPLATE static u32 FASTCALL OP_STMDA_W() TEMPLATE static u32 FASTCALL OP_STMDB_W() { - u32 i = cpu->instruction, c = 0, b; + const u32 &i = cpu->instruction; + u32 c = 0, b; u32 start = cpu->R[REG_POS(i,16)]; for(b=0; b<16; ++b) @@ -7318,7 +7330,7 @@ TEMPLATE static u32 FASTCALL OP_STMDB_W() { start -= 4; WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; } } @@ -7328,14 +7340,14 @@ TEMPLATE static u32 FASTCALL OP_STMDB_W() TEMPLATE static u32 FASTCALL OP_STMIA2() { - u32 i, c, b; + const u32 &i = cpu->instruction; + u32 c, b; u32 start; u32 oldmode; if(cpu->CPSR.bits.mode==USR) return 2; - i = cpu->instruction; c = 0; start = cpu->R[REG_POS(i,16)]; oldmode = armcpu_switchMode(cpu, SYS); @@ -7348,7 +7360,7 @@ TEMPLATE static u32 FASTCALL OP_STMIA2() if(BIT_N(i, b)) { WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; start += 4; } } @@ -7359,14 +7371,14 @@ TEMPLATE static u32 FASTCALL OP_STMIA2() TEMPLATE static u32 FASTCALL OP_STMIB2() { - u32 i, c, b; + const u32 &i = cpu->instruction; + u32 c, b; u32 start; u32 oldmode; if(cpu->CPSR.bits.mode==USR) return 2; - i = cpu->instruction; c = 0; start = cpu->R[REG_POS(i,16)]; oldmode = armcpu_switchMode(cpu, SYS); @@ -7380,7 +7392,7 @@ TEMPLATE static u32 FASTCALL OP_STMIB2() { start += 4; WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; } } @@ -7390,14 +7402,14 @@ TEMPLATE static u32 FASTCALL OP_STMIB2() TEMPLATE static u32 FASTCALL OP_STMDA2() { - u32 i, c, b; + const u32 &i=cpu->instruction; + u32 c, b; u32 start; u32 oldmode; if(cpu->CPSR.bits.mode==USR) return 2; - i = cpu->instruction; c = 0; start = cpu->R[REG_POS(i,16)]; oldmode = armcpu_switchMode(cpu, SYS); @@ -7410,7 +7422,7 @@ TEMPLATE static u32 FASTCALL OP_STMDA2() if(BIT_N(i, 15-b)) { WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; start -= 4; } } @@ -7421,13 +7433,14 @@ TEMPLATE static u32 FASTCALL OP_STMDA2() TEMPLATE static u32 FASTCALL OP_STMDB2() { - u32 i, c, b; + const u32 &i = cpu->instruction; + u32 c, b; u32 start; u32 oldmode; if(cpu->CPSR.bits.mode==USR) return 2; - i = cpu->instruction; + c=0; start = cpu->R[REG_POS(i,16)]; oldmode = armcpu_switchMode(cpu, SYS); @@ -7438,7 +7451,7 @@ TEMPLATE static u32 FASTCALL OP_STMDB2() { start -= 4; WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; } } @@ -7468,7 +7481,7 @@ TEMPLATE static u32 FASTCALL OP_STMIA2_W() if(BIT_N(i, b)) { WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; start += 4; } } @@ -7498,7 +7511,7 @@ TEMPLATE static u32 FASTCALL OP_STMIB2_W() { start += 4; WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; } } armcpu_switchMode(cpu, oldmode); @@ -7528,7 +7541,7 @@ TEMPLATE static u32 FASTCALL OP_STMDA2_W() if(BIT_N(i, 15-b)) { WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; start -= 4; } } @@ -7563,7 +7576,7 @@ TEMPLATE static u32 FASTCALL OP_STMDB2_W() { start -= 4; WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; } } @@ -7580,7 +7593,7 @@ TEMPLATE static u32 FASTCALL OP_STMDB2_W() */ TEMPLATE static u32 FASTCALL OP_LDRD_STRD_POST_INDEX( ) { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 Rd_num = REG_POS( i, 12); u32 addr = cpu->R[REG_POS(i,16)]; u32 index; @@ -7609,12 +7622,12 @@ OP_LDRD_STRD_POST_INDEX( ) { } } - return 3 + (MMU.MMU_WAIT32[cpu->proc_ID][(addr>>24)&0xF] * 2); + return 3 + (MMU.MMU_WAIT32[PROCNUM][(addr>>24)&0xF] * 2); } TEMPLATE static u32 FASTCALL OP_LDRD_STRD_OFFSET_PRE_INDEX( ) { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 Rd_num = REG_POS( i, 12); u32 addr = cpu->R[REG_POS(i,16)]; u32 index; @@ -7653,7 +7666,7 @@ OP_LDRD_STRD_OFFSET_PRE_INDEX( ) { } } - return 3 + (MMU.MMU_WAIT32[cpu->proc_ID][(addr>>24)&0xF] * 2); + return 3 + (MMU.MMU_WAIT32[PROCNUM][(addr>>24)&0xF] * 2); } @@ -7739,7 +7752,7 @@ TEMPLATE static u32 FASTCALL OP_LDC_OPTION() TEMPLATE static u32 FASTCALL OP_MCR() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 cpnum = REG_POS(i, 8); if(!cpu->coproc[cpnum]) @@ -7758,7 +7771,7 @@ TEMPLATE static u32 FASTCALL OP_MCR() TEMPLATE static u32 FASTCALL OP_MRC() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 cpnum = REG_POS(i, 8); if(!cpu->coproc[cpnum]) @@ -7776,7 +7789,7 @@ TEMPLATE static u32 FASTCALL OP_MRC() //--------------SWI------------------------------- TEMPLATE static u32 FASTCALL OP_SWI() { - if (((cpu->intVector != 0) ^ (cpu->proc_ID == ARMCPU_ARM9))) + if (((cpu->intVector != 0) ^ (PROCNUM == ARMCPU_ARM9))) { /* TODO (#1#): translocated SWI vectors */ /* we use an irq thats not in the irq tab, as diff --git a/desmume/src/armcpu.h b/desmume/src/armcpu.h index 89bec1505..7311cc224 100644 --- a/desmume/src/armcpu.h +++ b/desmume/src/armcpu.h @@ -30,25 +30,29 @@ #define ARMCPU_ARM9 0 #define ARMPROC (PROCNUM?NDS_ARM7:NDS_ARM9) -#define CODE(i) (((i)>>25)&0X7) +#define CODE(i) (((i)>>25)&0x7) #define OPCODE(i) (((i)>>21)&0xF) #define SIGNEBIT(i) BIT_N(i,20) #define INSTRUCTION_INDEX(i) ((((i)>>16)&0xFF0)|(((i)>>4)&0xF)) -#define ROR(i, j) ((((u32)(i))>>(j)) | (((u32)(i))<<(32-(j)))) +inline u32 ROR(u32 i, u32 j) { return ((((u32)(i))>>(j)) | (((u32)(i))<<(32-(j)))); } -#define UNSIGNED_OVERFLOW(a,b,c) ((BIT31(a)&BIT31(b)) | \ - ((BIT31(a)|BIT31(b))&BIT31(~c))) +template +inline T UNSIGNED_OVERFLOW(T a,T b,T c) { return ((BIT31(a)&BIT31(b)) | + ((BIT31(a)|BIT31(b))&BIT31(~c))); } -#define UNSIGNED_UNDERFLOW(a,b,c) ((BIT31(~a)&BIT31(b)) | \ - ((BIT31(~a)|BIT31(b))&BIT31(c))) +template +inline T UNSIGNED_UNDERFLOW(T a,T b,T c) { return ((BIT31(~a)&BIT31(b)) | + ((BIT31(~a)|BIT31(b))&BIT31(c))); } -#define SIGNED_OVERFLOW(a,b,c) ((BIT31(a)&BIT31(b)&BIT31(~c))|\ - (BIT31(~a)&BIT31(~(b))&BIT31(c))) +template +inline T SIGNED_OVERFLOW(T a,T b,T c) { return ((BIT31(a)&BIT31(b)&BIT31(~c))| + (BIT31(~a)&BIT31(~(b))&BIT31(c))); } -#define SIGNED_UNDERFLOW(a,b,c) ((BIT31(a)&BIT31(~(b))&BIT31(~c))|\ - (BIT31(~a)&BIT31(b)&BIT31(c))) +template +inline T SIGNED_UNDERFLOW(T a,T b,T c) { return ((BIT31(a)&BIT31(~(b))&BIT31(~c))| + (BIT31(~a)&BIT31(b)&BIT31(c))); } #define EQ 0x0 #define NE 0x1 @@ -259,8 +263,4 @@ static INLINE void NDS_makeInt(u8 proc_ID,u32 num) } } -//stores the currently executing arm cpu. -//we poke values in here instead of passing them around constantly. -extern armcpu_t *armcpu_curr; - #endif diff --git a/desmume/src/common.cpp b/desmume/src/common.cpp index b21a6b11e..b1c24c23f 100644 --- a/desmume/src/common.cpp +++ b/desmume/src/common.cpp @@ -46,7 +46,7 @@ void GetINIPath() { sprintf(IniName, "%s\\desmume.ini",szPath); } else if (MAX_PATH> strlen(".\\desmume.ini")) { - sprintf(IniName, ".\\desmume.ini",szPath); + sprintf(IniName, ".\\desmume.ini"); } else { memset(IniName,0,MAX_PATH) ; diff --git a/desmume/src/gfx3d.cpp b/desmume/src/gfx3d.cpp index 3f7f97063..969064ab0 100644 --- a/desmume/src/gfx3d.cpp +++ b/desmume/src/gfx3d.cpp @@ -37,10 +37,10 @@ GFX3D gfx3d; //tables that are provided to anyone -u32 color_15bit_to_24bit[32768]; +CACHE_ALIGN u32 color_15bit_to_24bit[32768]; //is this a crazy idea? this table spreads 5 bits evenly over 31 from exactly 0 to INT_MAX -const int material_5bit_to_31bit[] = { +CACHE_ALIGN const int material_5bit_to_31bit[] = { 0x00000000, 0x04210842, 0x08421084, 0x0C6318C6, 0x10842108, 0x14A5294A, 0x18C6318C, 0x1CE739CE, 0x21084210, 0x25294A52, 0x294A5294, 0x2D6B5AD6, @@ -51,15 +51,14 @@ const int material_5bit_to_31bit[] = { 0x739CE739, 0x77BDEF7B, 0x7BDEF7BD, 0x7FFFFFFF }; -const u8 material_5bit_to_8bit[] = { +CACHE_ALIGN const u8 material_5bit_to_8bit[] = { 0x00, 0x08, 0x10, 0x18, 0x21, 0x29, 0x31, 0x39, 0x42, 0x4A, 0x52, 0x5A, 0x63, 0x6B, 0x73, 0x7B, 0x84, 0x8C, 0x94, 0x9C, 0xA5, 0xAD, 0xB5, 0xBD, 0xC6, 0xCE, 0xD6, 0xDE, 0xE7, 0xEF, 0xF7, 0xFF }; - -const u8 material_3bit_to_8bit[] = { +CACHE_ALIGN const u8 material_3bit_to_8bit[] = { 0x00, 0x24, 0x49, 0x6D, 0x92, 0xB6, 0xDB, 0xFF }; @@ -73,28 +72,28 @@ static float normalTable[1024]; #define fix10_2float(v) (((float)((s32)(v))) / (float)(1<<9)) // Matrix stack handling -static ALIGN(16) MatrixStack mtxStack[4]; -static ALIGN(16) float mtxCurrent [4][16]; -static ALIGN(16) float mtxTemporal[16]; +static CACHE_ALIGN MatrixStack mtxStack[4]; +static CACHE_ALIGN float mtxCurrent [4][16]; +static CACHE_ALIGN float mtxTemporal[16]; static u32 mode = 0; // Indexes for matrix loading/multiplication -static u8 ML4x4ind = 0; -static u8 ML4x3_c = 0, ML4x3_l = 0; -static u8 MM4x4ind = 0; -static u8 MM4x3_c = 0, MM4x3_l = 0; -static u8 MM3x3_c = 0, MM3x3_l = 0; +static int ML4x4ind = 0; +static int ML4x3_c = 0, ML4x3_l = 0; +static int MM4x4ind = 0; +static int MM4x3_c = 0, MM4x3_l = 0; +static int MM3x3_c = 0, MM3x3_l = 0; // Data for vertex submission -static ALIGN(16) float coord[4] = {0.0, 0.0, 0.0, 0.0}; +static CACHE_ALIGN float coord[4] = {0.0, 0.0, 0.0, 0.0}; static char coordind = 0; static u32 vtxFormat; // Data for basic transforms -static ALIGN(16) float trans[4] = {0.0, 0.0, 0.0, 0.0}; -static u8 transind = 0; -static ALIGN(16) float scale[4] = {0.0, 0.0, 0.0, 0.0}; -static u8 scaleind = 0; +static CACHE_ALIGN float trans[4] = {0.0, 0.0, 0.0, 0.0}; +static int transind = 0; +static CACHE_ALIGN float scale[4] = {0.0, 0.0, 0.0, 0.0}; +static int scaleind = 0; //various other registers static int _t=0, _s=0; @@ -107,7 +106,7 @@ static u32 clInd2 = 0; static u32 polyAttr=0,textureFormat=0, texturePalette=0; //the current vertex color, 5bit values -static u8 colorRGB[4] = { 31,31,31,31 }; +static int colorRGB[4] = { 31,31,31,31 }; u32 control = 0; @@ -130,8 +129,8 @@ static u32 envMode=0; static u32 lightMask=0; //other things: static int texCoordinateTransform = 0; -static ALIGN(16) float cacheLightDirection[4][4]; -static ALIGN(16) float cacheHalfVector[4][4]; +static CACHE_ALIGN float cacheLightDirection[4][4]; +static CACHE_ALIGN float cacheHalfVector[4][4]; //------------------ #define RENDER_FRONT_SURFACE 0x80 @@ -160,6 +159,7 @@ static void twiddleLists() { } static BOOL flushPending = FALSE; +static BOOL drawPending = FALSE; //------------------------------------------------------------ static void makeTables() { @@ -1389,7 +1389,13 @@ void gfx3d_VBlankSignal() //so, if we have a redraw pending, now is a safe time to do it if(!flushPending) return; flushPending = FALSE; + drawPending = TRUE; +} +void gfx3d_VBlankEndSignal() +{ + if(!drawPending) return; + drawPending = FALSE; gpu3D->NDS_3D_Render(); } @@ -1507,6 +1513,7 @@ SFORMAT SF_GFX3D[]={ { "GTST", 4, 1, &triStripToggle}, { "GLTW", 4, 1, &listTwiddle}, { "GFLP", 4, 1, &flushPending}, + { "GDRP", 4, 1, &drawPending}, { "GSET", 4, 1, &gfx3d.enableTexturing}, { "GSEA", 4, 1, &gfx3d.enableAlphaTest}, { "GSEB", 4, 1, &gfx3d.enableAlphaBlending}, diff --git a/desmume/src/gfx3d.h b/desmume/src/gfx3d.h index 85f1f1278..7316311c1 100644 --- a/desmume/src/gfx3d.h +++ b/desmume/src/gfx3d.h @@ -130,10 +130,10 @@ extern GFX3D gfx3d; //produce a 32bpp color from a ds RGB15 plus an 8bit alpha, not using a table (but using other tables) #define RGB15TO32_DIRECT(col,alpha8) ( ((alpha8)<<24) | (material_5bit_to_8bit[((col)>>10)&0x1F]<<16) | (material_5bit_to_8bit[((col)>>5)&0x1F]<<8) | material_5bit_to_8bit[(col)&0x1F] ) -extern u32 color_15bit_to_24bit[32768]; -extern const int material_5bit_to_31bit[32]; -extern const u8 material_5bit_to_8bit[32]; -extern const u8 material_3bit_to_8bit[8]; +extern CACHE_ALIGN u32 color_15bit_to_24bit[32768]; +extern CACHE_ALIGN const int material_5bit_to_31bit[32]; +extern CACHE_ALIGN const u8 material_5bit_to_8bit[32]; +extern CACHE_ALIGN const u8 material_3bit_to_8bit[8]; //GE commands: void gfx3d_glViewPort(unsigned long v); @@ -186,6 +186,7 @@ void gfx3d_glGetVecRes(unsigned int index); void gfx3d_glCallList(unsigned long v); void gfx3d_glFlush(unsigned long v); void gfx3d_VBlankSignal(); +void gfx3d_VBlankEndSignal(); void gfx3d_Control(unsigned long v); //other misc stuff diff --git a/desmume/src/thumb_instructions.cpp b/desmume/src/thumb_instructions.cpp index 6ac5a4ddb..be50b9eb1 100644 --- a/desmume/src/thumb_instructions.cpp +++ b/desmume/src/thumb_instructions.cpp @@ -65,7 +65,7 @@ TEMPLATE static u32 FASTCALL OP_UND_THUMB() TEMPLATE static u32 FASTCALL OP_LSL_0() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->R[REG_NUM(i, 0)] = cpu->R[REG_NUM(i, 3)]; cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0; @@ -75,7 +75,7 @@ TEMPLATE static u32 FASTCALL OP_LSL_0() TEMPLATE static u32 FASTCALL OP_LSL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = (i>>6) & 0x1F; cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 3)], 32-v); cpu->R[REG_NUM(i, 0)] = (cpu->R[REG_NUM(i, 3)] << v); @@ -87,7 +87,7 @@ TEMPLATE static u32 FASTCALL OP_LSL() TEMPLATE static u32 FASTCALL OP_LSR_0() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; // cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 0)]); cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 3)]); cpu->R[REG_NUM(i, 0)] = 0; @@ -99,7 +99,7 @@ TEMPLATE static u32 FASTCALL OP_LSR_0() TEMPLATE static u32 FASTCALL OP_LSR() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = (i>>6) & 0x1F; cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 0)], v-1); cpu->R[REG_NUM(i, 0)] = (cpu->R[REG_NUM(i, 3)] >> v); @@ -111,7 +111,7 @@ TEMPLATE static u32 FASTCALL OP_LSR() TEMPLATE static u32 FASTCALL OP_ASR_0() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 3)]); cpu->R[REG_NUM(i, 0)] = BIT31(cpu->R[REG_NUM(i, 3)])*0xFFFFFFFF; cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); @@ -122,7 +122,7 @@ TEMPLATE static u32 FASTCALL OP_ASR_0() TEMPLATE static u32 FASTCALL OP_ASR() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = (i>>6) & 0x1F; cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 3)], v-1); cpu->R[REG_NUM(i, 0)] = (((s32)cpu->R[REG_NUM(i, 3)]) >> v); @@ -134,7 +134,7 @@ TEMPLATE static u32 FASTCALL OP_ASR() TEMPLATE static u32 FASTCALL OP_ADD_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 a = cpu->R[REG_NUM(i, 3)]; u32 b = cpu->R[REG_NUM(i, 6)]; cpu->R[REG_NUM(i, 0)] = a + b; @@ -148,7 +148,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_REG() TEMPLATE static u32 FASTCALL OP_SUB_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 a = cpu->R[REG_NUM(i, 3)]; u32 b = cpu->R[REG_NUM(i, 6)]; cpu->R[REG_NUM(i, 0)] = a - b; @@ -162,7 +162,7 @@ TEMPLATE static u32 FASTCALL OP_SUB_REG() TEMPLATE static u32 FASTCALL OP_ADD_IMM3() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 a = cpu->R[REG_NUM(i, 3)]; cpu->R[REG_NUM(i, 0)] = a + REG_NUM(i, 6); cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); @@ -175,7 +175,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_IMM3() TEMPLATE static u32 FASTCALL OP_SUB_IMM3() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 a = cpu->R[REG_NUM(i, 3)]; cpu->R[REG_NUM(i, 0)] = a - REG_NUM(i, 6); cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); @@ -188,7 +188,7 @@ TEMPLATE static u32 FASTCALL OP_SUB_IMM3() TEMPLATE static u32 FASTCALL OP_MOV_IMM8() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->R[REG_NUM(i, 8)] = i & 0xFF; cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 8)]); cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 8)] == 0; @@ -198,7 +198,7 @@ TEMPLATE static u32 FASTCALL OP_MOV_IMM8() TEMPLATE static u32 FASTCALL OP_CMP_IMM8() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 tmp = cpu->R[REG_NUM(i, 8)] - (i & 0xFF); cpu->CPSR.bits.N = BIT31(tmp); cpu->CPSR.bits.Z = tmp == 0; @@ -210,7 +210,7 @@ TEMPLATE static u32 FASTCALL OP_CMP_IMM8() TEMPLATE static u32 FASTCALL OP_ADD_IMM8() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 tmp = cpu->R[REG_NUM(i, 8)] + (i & 0xFF); cpu->CPSR.bits.N = BIT31(tmp); cpu->CPSR.bits.Z = tmp == 0; @@ -223,7 +223,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_IMM8() TEMPLATE static u32 FASTCALL OP_SUB_IMM8() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 tmp = cpu->R[REG_NUM(i, 8)] - (i & 0xFF); cpu->CPSR.bits.N = BIT31(tmp); cpu->CPSR.bits.Z = tmp == 0; @@ -236,7 +236,7 @@ TEMPLATE static u32 FASTCALL OP_SUB_IMM8() TEMPLATE static u32 FASTCALL OP_AND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->R[REG_NUM(i, 0)] &= cpu->R[REG_NUM(i, 3)]; cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0; @@ -246,7 +246,7 @@ TEMPLATE static u32 FASTCALL OP_AND() TEMPLATE static u32 FASTCALL OP_EOR() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->R[REG_NUM(i, 0)] ^= cpu->R[REG_NUM(i, 3)]; cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0; @@ -256,7 +256,7 @@ TEMPLATE static u32 FASTCALL OP_EOR() TEMPLATE static u32 FASTCALL OP_LSL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_NUM(i, 3)]&0xFF; if(!v) @@ -286,7 +286,7 @@ TEMPLATE static u32 FASTCALL OP_LSL_REG() TEMPLATE static u32 FASTCALL OP_LSR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_NUM(i, 3)]&0xFF; if(!v) @@ -316,7 +316,7 @@ TEMPLATE static u32 FASTCALL OP_LSR_REG() TEMPLATE static u32 FASTCALL OP_ASR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_NUM(i, 3)]&0xFF; if(!v) @@ -344,7 +344,7 @@ TEMPLATE static u32 FASTCALL OP_ASR_REG() TEMPLATE static u32 FASTCALL OP_ADC_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 a = cpu->R[REG_NUM(i, 0)]; u32 b = cpu->R[REG_NUM(i, 3)]; u32 tmp = b + cpu->CPSR.bits.C; @@ -363,7 +363,7 @@ TEMPLATE static u32 FASTCALL OP_ADC_REG() TEMPLATE static u32 FASTCALL OP_SBC_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 a = cpu->R[REG_NUM(i, 0)]; u32 b = cpu->R[REG_NUM(i, 3)]; u32 tmp = a - (!cpu->CPSR.bits.C); @@ -373,15 +373,15 @@ TEMPLATE static u32 FASTCALL OP_SBC_REG() cpu->CPSR.bits.N = BIT31(res); cpu->CPSR.bits.Z = res == 0; - cpu->CPSR.bits.C = (!UNSIGNED_UNDERFLOW(a, (cpu->CPSR.bits.C?0:0x80000000), tmp)) & (!UNSIGNED_OVERFLOW(tmp, b, res)); - cpu->CPSR.bits.V = SIGNED_UNDERFLOW(a, (cpu->CPSR.bits.C?0:0x80000000), tmp) | SIGNED_OVERFLOW(tmp, b, res); + cpu->CPSR.bits.C = (!UNSIGNED_UNDERFLOW(a, (u32)(cpu->CPSR.bits.C?0:0x80000000), tmp)) & (!UNSIGNED_OVERFLOW(tmp, b, res)); + cpu->CPSR.bits.V = SIGNED_UNDERFLOW(a, (u32)(cpu->CPSR.bits.C?0:0x80000000), tmp) | SIGNED_OVERFLOW(tmp, b, res); return 3; } TEMPLATE static u32 FASTCALL OP_ROR_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 v = cpu->R[REG_NUM(i, 3)]&0xFF; if(v == 0) @@ -408,7 +408,7 @@ TEMPLATE static u32 FASTCALL OP_ROR_REG() TEMPLATE static u32 FASTCALL OP_TST() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 tmp = cpu->R[REG_NUM(i, 0)] & cpu->R[REG_NUM(i, 3)]; cpu->CPSR.bits.N = BIT31(tmp); cpu->CPSR.bits.Z = tmp == 0; @@ -418,21 +418,21 @@ TEMPLATE static u32 FASTCALL OP_TST() TEMPLATE static u32 FASTCALL OP_NEG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 a = cpu->R[REG_NUM(i, 3)]; cpu->R[REG_NUM(i, 0)] = -((signed int)a); cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0; - cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(0, a, cpu->R[REG_NUM(i, 0)]); - cpu->CPSR.bits.V = SIGNED_UNDERFLOW(0, a, cpu->R[REG_NUM(i, 0)]); + cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW((u32)0, a, cpu->R[REG_NUM(i, 0)]); + cpu->CPSR.bits.V = SIGNED_UNDERFLOW((u32)0, a, cpu->R[REG_NUM(i, 0)]); return 3; } TEMPLATE static u32 FASTCALL OP_CMP() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 tmp = cpu->R[REG_NUM(i, 0)] -cpu->R[REG_NUM(i, 3)]; cpu->CPSR.bits.N = BIT31(tmp); @@ -445,7 +445,7 @@ TEMPLATE static u32 FASTCALL OP_CMP() TEMPLATE static u32 FASTCALL OP_CMN() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 tmp = cpu->R[REG_NUM(i, 0)] + cpu->R[REG_NUM(i, 3)]; //execute = FALSE; @@ -460,7 +460,7 @@ TEMPLATE static u32 FASTCALL OP_CMN() TEMPLATE static u32 FASTCALL OP_ORR() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->R[REG_NUM(i, 0)] |= cpu->R[REG_NUM(i, 3)]; cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0; @@ -470,7 +470,7 @@ TEMPLATE static u32 FASTCALL OP_ORR() TEMPLATE static u32 FASTCALL OP_MUL_REG() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->R[REG_NUM(i, 0)] *= cpu->R[REG_NUM(i, 3)]; cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0; @@ -480,7 +480,7 @@ TEMPLATE static u32 FASTCALL OP_MUL_REG() TEMPLATE static u32 FASTCALL OP_BIC() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->R[REG_NUM(i, 0)] &= (~cpu->R[REG_NUM(i, 3)]); cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0; @@ -490,7 +490,7 @@ TEMPLATE static u32 FASTCALL OP_BIC() TEMPLATE static u32 FASTCALL OP_MVN() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->R[REG_NUM(i, 0)] = (~cpu->R[REG_NUM(i, 3)]); cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0; @@ -500,7 +500,7 @@ TEMPLATE static u32 FASTCALL OP_MVN() TEMPLATE static u32 FASTCALL OP_ADD_SPE() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 Rd = (i&7) | ((i>>4)&8); cpu->R[Rd] += cpu->R[REG_POS(i, 3)]; @@ -512,7 +512,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_SPE() TEMPLATE static u32 FASTCALL OP_CMP_SPE() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 Rn = (i&7) | ((i>>4)&8); u32 tmp = cpu->R[Rn] -cpu->R[REG_POS(i, 3)]; @@ -526,7 +526,7 @@ TEMPLATE static u32 FASTCALL OP_CMP_SPE() TEMPLATE static u32 FASTCALL OP_MOV_SPE() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 Rd = (i&7) | ((i>>4)&8); cpu->R[Rd] = cpu->R[REG_POS(i, 3)]; @@ -565,48 +565,48 @@ TEMPLATE static u32 FASTCALL OP_LDR_PCREL() cpu->R[REG_NUM(cpu->instruction, 8)] = READ32(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 6)] + cpu->R[REG_NUM(i, 3)]; WRITE32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 0)]); - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRH_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; WRITE16(cpu->mem_if->data, adr, ((u16)cpu->R[REG_NUM(i, 0)])); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; WRITE8(cpu->mem_if->data, adr, ((u8)cpu->R[REG_NUM(i, 0)])); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSB_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; cpu->R[REG_NUM(i, 0)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = (cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]); u32 tempValue = READ32(cpu->mem_if->data, adr&0xFFFFFFFC); @@ -614,114 +614,114 @@ TEMPLATE static u32 FASTCALL OP_LDR_REG_OFF() tempValue = (tempValue>>adr) | (tempValue<<(32-adr)); cpu->R[REG_NUM(i, 0)] = tempValue; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRH_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; cpu->R[REG_NUM(i, 0)] = (u32)READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; cpu->R[REG_NUM(i, 0)] = (u32)READ8(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRSH_REG_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; cpu->R[REG_NUM(i, 0)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C); WRITE32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 0)]); - return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C); u32 tempValue = READ32(cpu->mem_if->data, adr&0xFFFFFFFC); adr = (adr&3)*8; tempValue = (tempValue>>adr) | (tempValue<<(32-adr)); cpu->R[REG_NUM(i, 0)] = tempValue; - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRB_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F); WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_NUM(i, 0)]); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRB_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F); cpu->R[REG_NUM(i, 0)] = READ8(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STRH_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E); WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_NUM(i, 0)]); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDRH_IMM_OFF() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E); cpu->R[REG_NUM(i, 0)] = READ16(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_STR_SPREL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[13] + ((i&0xFF)<<2); WRITE32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 8)]); - return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_LDR_SPREL() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[13] + ((i&0xFF)<<2); cpu->R[REG_NUM(i, 8)] = READ32(cpu->mem_if->data, adr); - return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; } TEMPLATE static u32 FASTCALL OP_ADD_2PC() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->R[REG_NUM(i, 8)] = (cpu->R[15]&0xFFFFFFFC) + ((i&0xFF)<<2); return 5; @@ -729,7 +729,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_2PC() TEMPLATE static u32 FASTCALL OP_ADD_2SP() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->R[REG_NUM(i, 8)] = cpu->R[13] + ((i&0xFF)<<2); return 2; @@ -751,7 +751,7 @@ TEMPLATE static u32 FASTCALL OP_ADJUST_M_SP() TEMPLATE static u32 FASTCALL OP_PUSH() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[13] - 4; u32 c = 0, j; @@ -759,7 +759,7 @@ TEMPLATE static u32 FASTCALL OP_PUSH() if(BIT_N(i, 7-j)) { WRITE32(cpu->mem_if->data, adr, cpu->R[7-j]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; adr -= 4; } cpu->R[13] = adr + 4; @@ -769,19 +769,19 @@ TEMPLATE static u32 FASTCALL OP_PUSH() TEMPLATE static u32 FASTCALL OP_PUSH_LR() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[13] - 4; u32 c = 0, j; WRITE32(cpu->mem_if->data, adr, cpu->R[14]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; adr -= 4; for(j = 0; j<8; ++j) if(BIT_N(i, 7-j)) { WRITE32(cpu->mem_if->data, adr, cpu->R[7-j]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; adr -= 4; } cpu->R[13] = adr + 4; @@ -791,7 +791,7 @@ TEMPLATE static u32 FASTCALL OP_PUSH_LR() TEMPLATE static u32 FASTCALL OP_POP() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[13]; u32 c = 0, j; @@ -799,7 +799,7 @@ TEMPLATE static u32 FASTCALL OP_POP() if(BIT_N(i, j)) { cpu->R[j] = READ32(cpu->mem_if->data, adr); - c += MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; adr += 4; } cpu->R[13] = adr; @@ -809,7 +809,7 @@ TEMPLATE static u32 FASTCALL OP_POP() TEMPLATE static u32 FASTCALL OP_POP_PC() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[13]; u32 c = 0, j; u32 v; @@ -818,15 +818,15 @@ TEMPLATE static u32 FASTCALL OP_POP_PC() if(BIT_N(i, j)) { cpu->R[j] = READ32(cpu->mem_if->data, adr); - c += MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; adr += 4; } v = READ32(cpu->mem_if->data, adr); - c += MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; cpu->R[15] = v & 0xFFFFFFFE; cpu->next_instruction = v & 0xFFFFFFFE; - if(cpu->proc_ID==0) + if(PROCNUM==0) cpu->CPSR.bits.T = BIT0(v); adr += 4; @@ -841,7 +841,7 @@ TEMPLATE static u32 FASTCALL OP_BKPT_THUMB() TEMPLATE static u32 FASTCALL OP_STMIA_THUMB() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 8)]; u32 c = 0, j; @@ -849,7 +849,7 @@ TEMPLATE static u32 FASTCALL OP_STMIA_THUMB() if(BIT_N(i, j)) { WRITE32(cpu->mem_if->data, adr, cpu->R[j]); - c += MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; adr += 4; } cpu->R[REG_NUM(i, 8)] = adr; @@ -858,7 +858,7 @@ TEMPLATE static u32 FASTCALL OP_STMIA_THUMB() TEMPLATE static u32 FASTCALL OP_LDMIA_THUMB() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 8)]; u32 c = 0, j; @@ -866,7 +866,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIA_THUMB() if(BIT_N(i, j)) { cpu->R[j] = READ32(cpu->mem_if->data, adr); - c += MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; + c += MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; adr += 4; } cpu->R[REG_NUM(i, 8)] = adr; @@ -875,7 +875,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIA_THUMB() TEMPLATE static u32 FASTCALL OP_B_COND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; if(!TEST_COND((i>>8)&0xF, 0, cpu->CPSR)) return 1; @@ -886,7 +886,7 @@ TEMPLATE static u32 FASTCALL OP_B_COND() TEMPLATE static u32 FASTCALL OP_SWI_THUMB() { - if (((cpu->intVector != 0) ^ (cpu->proc_ID == ARMCPU_ARM9))) + if (((cpu->intVector != 0) ^ (PROCNUM == ARMCPU_ARM9))) { /* we use an irq thats not in the irq tab, as it was replaced duie to a changed intVector */ @@ -912,7 +912,7 @@ TEMPLATE static u32 FASTCALL OP_SWI_THUMB() TEMPLATE static u32 FASTCALL OP_B_UNCOND() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->R[15] += (SIGNEEXT_IMM11(i)<<1); cpu->next_instruction = cpu->R[15]; return 3; @@ -920,7 +920,7 @@ TEMPLATE static u32 FASTCALL OP_B_UNCOND() TEMPLATE static u32 FASTCALL OP_BLX() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->R[15] = (cpu->R[14] + ((i&0x7FF)<<1))&0xFFFFFFFC; cpu->R[14] = cpu->next_instruction | 1; cpu->next_instruction = cpu->R[15]; @@ -930,14 +930,14 @@ TEMPLATE static u32 FASTCALL OP_BLX() TEMPLATE static u32 FASTCALL OP_BL_10() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->R[14] = cpu->R[15] + (SIGNEEXT_IMM11(i)<<12); return 1; } TEMPLATE static u32 FASTCALL OP_BL_THUMB() { - u32 i = cpu->instruction; + const u32 &i = cpu->instruction; cpu->R[15] = (cpu->R[14] + ((i&0x7FF)<<1)); cpu->R[14] = cpu->next_instruction | 1; cpu->next_instruction = cpu->R[15]; diff --git a/desmume/src/types.h b/desmume/src/types.h index 99ab243b5..a2b0af033 100644 --- a/desmume/src/types.h +++ b/desmume/src/types.h @@ -21,8 +21,8 @@ #define TYPES_HPP #define DESMUME_NAME "DeSmuME" -#define DESMUME_VERSION_STRING "0.8.0b2-interim" -#define DESMUME_VERSION_NUMERIC 80002 +#define DESMUME_VERSION_STRING "0.9-interim" +#define DESMUME_VERSION_NUMERIC 90000 #define DESMUME_NAME_AND_VERSION DESMUME_NAME " " DESMUME_VERSION_STRING " " VERSION #ifdef _WIN32 @@ -39,6 +39,8 @@ #define ALIGN(X) #endif +#define CACHE_ALIGN ALIGN(32) + #ifndef FASTCALL #ifdef __MINGW32__ #define FASTCALL __attribute__((fastcall)) @@ -59,6 +61,14 @@ #endif #endif +#ifndef FORCEINLINE +#if defined(_MSC_VER) +#define FORCEINLINE __forceinline +#else +#define FORCEINLINE INLINE +#endif +#endif + #if defined(__LP64__) typedef unsigned char u8; typedef unsigned short u16; diff --git a/desmume/src/windows/DeSmuME_2005.vcproj b/desmume/src/windows/DeSmuME_2005.vcproj index d0ace97cb..9020d918e 100644 --- a/desmume/src/windows/DeSmuME_2005.vcproj +++ b/desmume/src/windows/DeSmuME_2005.vcproj @@ -107,6 +107,189 @@ Name="VCPostBuildEventTool" /> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + diff --git a/desmume/src/windows/IORegView.cpp b/desmume/src/windows/IORegView.cpp index df2b49e9d..e54a9e4eb 100644 --- a/desmume/src/windows/IORegView.cpp +++ b/desmume/src/windows/IORegView.cpp @@ -72,7 +72,7 @@ BOOL CALLBACK IoregView_Proc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lPa switch (message) { case WM_INITDIALOG : - IORegView = new ioregview_struct[1]; + IORegView = new ioregview_struct; memset(IORegView, 0, sizeof(ioregview_struct)); IORegView->autoup_secs = 5; SendMessage(GetDlgItem(hwnd, IDC_AUTO_UPDATE_SPIN), @@ -138,5 +138,5 @@ BOOL CALLBACK IoregView_Proc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lPa } return 0; } - return DefWindowProc(hwnd, message, wParam, lParam); + return FALSE; } diff --git a/desmume/src/windows/disView.cpp b/desmume/src/windows/disView.cpp index 5d7509987..2454081d0 100644 --- a/desmume/src/windows/disView.cpp +++ b/desmume/src/windows/disView.cpp @@ -280,11 +280,15 @@ LRESULT CALLBACK ViewDisasm_ARM7BoxProc(HWND hwnd, UINT msg, WPARAM wParam, LPAR case WM_ERASEBKGND: return 1; } - return DefWindowProc(hwnd, msg, wParam, lParam); + return FALSE; } BOOL CALLBACK ViewDisasm_ARM7Proc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam) { + //bail out early if the dialog isnt initialized + if(!DisView7 && message != WM_INITDIALOG) + return false; + switch (message) { case WM_INITDIALOG : @@ -292,7 +296,7 @@ BOOL CALLBACK ViewDisasm_ARM7Proc (HWND hwnd, UINT message, WPARAM wParam, LPARA SetWindowText(hwnd, "ARM7 Disassembler"); SetDlgItemInt(hwnd, IDC_SETPNUM, 1, FALSE); SendMessage(GetDlgItem(hwnd, IDC_AUTO_DES), BM_SETCHECK, TRUE, 0); - DisView7 = new disview_struct[1]; + DisView7 = new disview_struct; memset(DisView7, 0, sizeof(disview_struct)); DisView7->cpu = &NDS_ARM7; DisView7->autoup_secs = 5; @@ -380,7 +384,7 @@ BOOL CALLBACK ViewDisasm_ARM7Proc (HWND hwnd, UINT message, WPARAM wParam, LPARA { int ndstep; ndstep = GetDlgItemInt(hwnd, IDC_SETPNUM, NULL, FALSE); - NDS_exec(ndstep, TRUE); + NDS_exec(ndstep); } return 1; case IDC_GO : @@ -459,7 +463,7 @@ BOOL CALLBACK ViewDisasm_ARM7Proc (HWND hwnd, UINT message, WPARAM wParam, LPARA return 0; } - return DefWindowProc(hwnd, message, wParam, lParam); + return FALSE; } // =================================================== ARM9 @@ -520,11 +524,15 @@ LRESULT CALLBACK ViewDisasm_ARM9BoxProc(HWND hwnd, UINT msg, WPARAM wParam, LPAR case WM_ERASEBKGND: return 1; } - return DefWindowProc(hwnd, msg, wParam, lParam); + return FALSE; } BOOL CALLBACK ViewDisasm_ARM9Proc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam) { + //bail out early if the dialog isnt initialized + if(!DisView9 && message != WM_INITDIALOG) + return false; + switch (message) { case WM_INITDIALOG : @@ -532,7 +540,7 @@ BOOL CALLBACK ViewDisasm_ARM9Proc (HWND hwnd, UINT message, WPARAM wParam, LPARA SetWindowText(hwnd, "ARM9 Disassembler"); SetDlgItemInt(hwnd, IDC_SETPNUM, 1, FALSE); SendMessage(GetDlgItem(hwnd, IDC_AUTO_DES), BM_SETCHECK, TRUE, 0); - DisView9 = new disview_struct[1]; + DisView9 = new disview_struct; memset(DisView9, 0, sizeof(disview_struct)); DisView9->cpu = &NDS_ARM9; DisView9->autoup_secs = 5; @@ -620,7 +628,7 @@ BOOL CALLBACK ViewDisasm_ARM9Proc (HWND hwnd, UINT message, WPARAM wParam, LPARA { int ndstep; ndstep = GetDlgItemInt(hwnd, IDC_SETPNUM, NULL, FALSE); - NDS_exec(ndstep, TRUE); + NDS_exec(ndstep); } return 1; case IDC_GO : @@ -699,7 +707,7 @@ BOOL CALLBACK ViewDisasm_ARM9Proc (HWND hwnd, UINT message, WPARAM wParam, LPARA return 0; } - return DefWindowProc(hwnd, message, wParam, lParam); + return FALSE; } void DisassemblerTools_Refresh(u8 proc) diff --git a/desmume/src/windows/fs-windows.cpp b/desmume/src/windows/fs-windows.cpp index e56e74b72..5f02031db 100644 --- a/desmume/src/windows/fs-windows.cpp +++ b/desmume/src/windows/fs-windows.cpp @@ -42,7 +42,7 @@ void * FsReadFirst(const char * p, FsEntry * entry) { strncpy(entry->cFileName, FindFileData.cFileName,256); entry->cFileName[255] = 0 ; strncpy(entry->cAlternateFileName, FindFileData.cAlternateFileName,14); - entry->cAlternateFileName[14] = 0 ; + entry->cAlternateFileName[13] = 0 ; entry->flags = 0; if (FindFileData.dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) { entry->flags = FS_IS_DIR; @@ -66,7 +66,7 @@ int FsReadNext(void * search, FsEntry * entry) { strncpy(entry->cFileName, FindFileData.cFileName,256); entry->cFileName[255] = 0 ; strncpy(entry->cAlternateFileName, FindFileData.cAlternateFileName,14); - entry->cAlternateFileName[14] = 0 ; + entry->cAlternateFileName[13] = 0 ; entry->flags = 0; if (FindFileData.dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) { entry->flags = FS_IS_DIR; diff --git a/desmume/src/windows/lightView.cpp b/desmume/src/windows/lightView.cpp index 9d92bdf45..011bdcb14 100644 --- a/desmume/src/windows/lightView.cpp +++ b/desmume/src/windows/lightView.cpp @@ -105,7 +105,7 @@ BOOL CALLBACK ViewLightsProc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lPa switch (message) { case WM_INITDIALOG: - LightsView = new lightsview_struct[1]; + LightsView = new lightsview_struct; memset(LightsView, 0, sizeof(lightsview_struct)); LightsView->autoup_secs = 5; SendMessage(GetDlgItem(hwnd, IDC_AUTO_UPDATE_SPIN), @@ -180,5 +180,5 @@ BOOL CALLBACK ViewLightsProc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lPa } return 0; } - return DefWindowProc(hwnd, message, wParam, lParam); + return FALSE; } diff --git a/desmume/src/windows/main.cpp b/desmume/src/windows/main.cpp index 6ce1a519b..b7f4009f2 100644 --- a/desmume/src/windows/main.cpp +++ b/desmume/src/windows/main.cpp @@ -876,7 +876,7 @@ DWORD WINAPI run() while(execute) { EnterCriticalSection(&win_sync); - cycles = NDS_exec((560190<<1)-cycles,FALSE); + cycles = NDS_exec((560190<<1)-cycles); win_sound_samplecounter = 735; LeaveCriticalSection(&win_sync); @@ -1150,7 +1150,6 @@ static void ExitRunLoop() execute = FALSE; } - int WINAPI WinMain (HINSTANCE hThisInstance, HINSTANCE hPrevInstance, LPSTR lpszArgument, @@ -1158,7 +1157,7 @@ int WINAPI WinMain (HINSTANCE hThisInstance, { InitializeCriticalSection(&win_sync); - + #ifdef GDB_STUB gdbstub_handle_t arm9_gdb_stub; gdbstub_handle_t arm7_gdb_stub; @@ -2032,14 +2031,14 @@ LRESULT CALLBACK WindowProcedure (HWND hwnd, UINT message, WPARAM wParam, LPARAM tpaused=true; NDS_Pause(); } - DialogBox(GetModuleHandle(NULL), MAKEINTRESOURCE(IDD_SOUNDSETTINGS), hwnd, (DLGPROC)SoundSettingsDlgProc); + DialogBox(hAppInst, MAKEINTRESOURCE(IDD_SOUNDSETTINGS), hwnd, (DLGPROC)SoundSettingsDlgProc); if (tpaused) NDS_UnPause(); } return 0; case IDM_GAME_INFO: { - CreateDialog(GetModuleHandle(NULL), MAKEINTRESOURCE(IDD_GAME_INFO), hwnd, GinfoView_Proc); + CreateDialog(hAppInst, MAKEINTRESOURCE(IDD_GAME_INFO), hwnd, GinfoView_Proc); } return 0; diff --git a/desmume/src/windows/mapView.cpp b/desmume/src/windows/mapView.cpp index 98576706f..ad756e7f4 100644 --- a/desmume/src/windows/mapView.cpp +++ b/desmume/src/windows/mapView.cpp @@ -79,11 +79,11 @@ LRESULT MapView_OnPaint(mapview_struct * win, HWND hwnd, WPARAM wParam, LPARAM l SetWindowText(GetDlgItem(hwnd, IDC_MODE), text); if(!(bgcnt&(1<<7))) - sprintf(text, "normale 16"); + sprintf(text, "normal 16"); else { if(!(dispcnt&(1<<30))) - sprintf(text, "normale 256"); + sprintf(text, "normal 256"); else { switch(win->map) @@ -104,6 +104,12 @@ LRESULT MapView_OnPaint(mapview_struct * win, HWND hwnd, WPARAM wParam, LPARAM l sprintf(text, "%d", (int)(bgcnt&3)); SetWindowText(GetDlgItem(hwnd, IDC_PRIO), text); + + + if((dispcnt>>8>>win->map)&1) + SetWindowText(GetDlgItem(hwnd, IDC_VISIBLE), "true"); + else + SetWindowText(GetDlgItem(hwnd, IDC_VISIBLE), "false"); sprintf(text, "0x%08X", (int)(0x6000000 + ((bgcnt>>2)&0xF)*0x4000 + win->lcd*0x200000 +((dispcnt>>24)&7)*0x10000)); SetWindowText(GetDlgItem(hwnd, IDC_CHAR), text); @@ -217,11 +223,15 @@ LRESULT MapView_OnPaint(mapview_struct * win, HWND hwnd, WPARAM wParam, LPARAM l BOOL CALLBACK ViewMapsProc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam) { + //bail out early if the dialog isnt initialized + if(!MapView && message != WM_INITDIALOG) + return false; + switch (message) { case WM_INITDIALOG : { - MapView = new mapview_struct[1]; + MapView = new mapview_struct; memset(MapView, 0, sizeof(MapView)); MapView->autoup_secs = 5; SendMessage(GetDlgItem(hwnd, IDC_AUTO_UPDATE_SPIN), @@ -332,5 +342,5 @@ BOOL CALLBACK ViewMapsProc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lPara }//switch return 1; } - return DefWindowProc(hwnd, message, wParam, lParam); + return false; } diff --git a/desmume/src/windows/matrixView.cpp b/desmume/src/windows/matrixView.cpp index 879f6e0e8..b68fc9100 100644 --- a/desmume/src/windows/matrixView.cpp +++ b/desmume/src/windows/matrixView.cpp @@ -149,7 +149,7 @@ BOOL CALLBACK ViewMatricesProc (HWND hwnd, UINT message, WPARAM wParam, LPARAM l { case WM_INITDIALOG: { - MatrixView = new matrixview_struct[1]; + MatrixView = new matrixview_struct; memset(MatrixView, 0, sizeof(matrixview_struct)); MatrixView->autoup_secs = 5; SendMessage(GetDlgItem(hwnd, IDC_AUTO_UPDATE_SPIN), @@ -252,5 +252,5 @@ BOOL CALLBACK ViewMatricesProc (HWND hwnd, UINT message, WPARAM wParam, LPARAM l return 0; } - return DefWindowProc(hwnd, message, wParam, lParam); + return false; } diff --git a/desmume/src/windows/memView.cpp b/desmume/src/windows/memView.cpp index 98255ecec..215c0b18a 100644 --- a/desmume/src/windows/memView.cpp +++ b/desmume/src/windows/memView.cpp @@ -200,19 +200,22 @@ LRESULT CALLBACK ViewMem_ARM7BoxProc(HWND hwnd, UINT msg, WPARAM wParam, LPARAM return 1; } - return DefWindowProc(hwnd, msg, wParam, lParam); + return FALSE; } -bool CALLBACK ViewMem_ARM7Proc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam) +BOOL CALLBACK ViewMem_ARM7Proc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam) { - + //bail out early if the dialog isnt initialized + if(!MemView7 && message != WM_INITDIALOG) + return false; + switch (message) { case WM_INITDIALOG : { SetWindowText(hwnd, "ARM7 memory viewer"); SendMessage(GetDlgItem(hwnd, IDC_8_BIT), BM_SETCHECK, TRUE, 0); - MemView7 = new memview_struct[1]; + MemView7 = new memview_struct; memset(MemView7, 0, sizeof(memview_struct)); MemView7->cpu = 1; MemView7->autoup_secs = 5; @@ -324,7 +327,7 @@ bool CALLBACK ViewMem_ARM7Proc (HWND hwnd, UINT message, WPARAM wParam, LPARAM l return 1; } } - return DefWindowProc(hwnd, message, wParam, lParam); + return FALSE; } //=================================================== ARM9 @@ -385,12 +388,15 @@ LRESULT CALLBACK ViewMem_ARM9BoxProc(HWND hwnd, UINT msg, WPARAM wParam, LPARAM return 1; } - return DefWindowProc(hwnd, msg, wParam, lParam); + return FALSE; } -bool CALLBACK ViewMem_ARM9Proc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam) +BOOL CALLBACK ViewMem_ARM9Proc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam) { - + //bail out early if the dialog isnt initialized + if(!MemView9 && message != WM_INITDIALOG) + return false; + switch (message) { case WM_INITDIALOG : @@ -405,7 +411,7 @@ bool CALLBACK ViewMem_ARM9Proc (HWND hwnd, UINT message, WPARAM wParam, LPARAM l UDM_SETRANGE, 0, MAKELONG(99, 1)); SendMessage(GetDlgItem(hwnd, IDC_AUTO_UPDATE_SPIN), UDM_SETPOS32, 0, MemView9->autoup_secs); - return 0; + return 1; } case WM_CLOSE: { @@ -509,5 +515,5 @@ bool CALLBACK ViewMem_ARM9Proc (HWND hwnd, UINT message, WPARAM wParam, LPARAM l return 1; } } - return DefWindowProc(hwnd, message, wParam, lParam); + return FALSE; } diff --git a/desmume/src/windows/memView.h b/desmume/src/windows/memView.h index 81c6c1e36..d9e13b2e2 100644 --- a/desmume/src/windows/memView.h +++ b/desmume/src/windows/memView.h @@ -24,10 +24,10 @@ #include -extern bool CALLBACK ViewMem_ARM7Proc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam); +extern BOOL CALLBACK ViewMem_ARM7Proc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam); extern LRESULT CALLBACK ViewMem_ARM7BoxProc(HWND hwnd, UINT msg, WPARAM wParam, LPARAM lParam); -extern bool CALLBACK ViewMem_ARM9Proc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam); +extern BOOL CALLBACK ViewMem_ARM9Proc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam); extern LRESULT CALLBACK ViewMem_ARM9BoxProc(HWND hwnd, UINT msg, WPARAM wParam, LPARAM lParam); #endif \ No newline at end of file diff --git a/desmume/src/windows/oamView.cpp b/desmume/src/windows/oamView.cpp index d7da44de8..3beb8ba42 100644 --- a/desmume/src/windows/oamView.cpp +++ b/desmume/src/windows/oamView.cpp @@ -206,11 +206,15 @@ LRESULT CALLBACK ViewOAMBoxProc(HWND hwnd, UINT msg, WPARAM wParam, LPARAM lPara BOOL CALLBACK ViewOAMProc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam) { + //bail out early if the dialog isnt initialized + if(!OAMView && message != WM_INITDIALOG) + return false; + switch (message) { case WM_INITDIALOG : { - OAMView = new oamview_struct[1]; + OAMView = new oamview_struct; memset(OAMView, 0, sizeof(oamview_struct)); OAMView->oam = (OAM *)(ARM9Mem.ARM9_OAM); OAMView->gpu = MainScreen.gpu; @@ -332,5 +336,5 @@ BOOL CALLBACK ViewOAMProc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam } return 0; } - return DefWindowProc(hwnd, message, wParam, lParam); + return FALSE; } diff --git a/desmume/src/windows/palView.cpp b/desmume/src/windows/palView.cpp index 5ef6f8b28..12d91d9ae 100644 --- a/desmume/src/windows/palView.cpp +++ b/desmume/src/windows/palView.cpp @@ -85,11 +85,15 @@ LRESULT PalView_OnPaint(const u16 * adr, u16 num, HWND hwnd, WPARAM wParam, LPAR BOOL CALLBACK ViewPalProc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam) { + //bail out early if the dialog isnt initialized + if(!PalView && message != WM_INITDIALOG) + return false; + switch (message) { case WM_INITDIALOG : { - PalView = new palview_struct[1]; + PalView = new palview_struct; memset(PalView, 0, sizeof(palview_struct)); PalView->adr = (u16 *)ARM9Mem.ARM9_VMEM; PalView->autoup_secs = 5; @@ -287,5 +291,5 @@ BOOL CALLBACK ViewPalProc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam } return 0; } - return DefWindowProc(hwnd, message, wParam, lParam); + return false; } diff --git a/desmume/src/windows/resource.h b/desmume/src/windows/resource.h index 1995f56b5..289220cb9 100644 --- a/desmume/src/windows/resource.h +++ b/desmume/src/windows/resource.h @@ -166,6 +166,7 @@ #define IDC_SCR 806 #define IDC_MSIZE 807 #define IDC_SCROLL 808 +#define IDC_PRIO2 809 #define IDD_OAM 900 #define IDC_SCR_SELECT 901 #define IDC_TILE 902 @@ -208,6 +209,7 @@ #define ID_CANCEL 1016 #define IDSAVE 1017 #define IDC_AUTOUPDATE_ASM 1018 +#define IDC_VISIBLE 1019 #define IDM_FIRMSETTINGS 1100 #define IDD_FIRMSETTINGS 1101 #define IDC_EDIT1 1102 @@ -357,7 +359,7 @@ #ifndef APSTUDIO_READONLY_SYMBOLS #define _APS_NEXT_RESOURCE_VALUE 107 #define _APS_NEXT_COMMAND_VALUE 40038 -#define _APS_NEXT_CONTROL_VALUE 1019 +#define _APS_NEXT_CONTROL_VALUE 1020 #define _APS_NEXT_SYMED_VALUE 112 #endif #endif diff --git a/desmume/src/windows/resources.rc b/desmume/src/windows/resources.rc index fd1ebe93f..818fa4fab 100644 --- a/desmume/src/windows/resources.rc +++ b/desmume/src/windows/resources.rc @@ -1039,7 +1039,7 @@ END IDD_TILE DIALOGEX 0, 0, 446, 180 STYLE DS_SETFONT | DS_CENTER | WS_VISIBLE | WS_CAPTION -CAPTION "TILE Fremvisning" +CAPTION "TILE VIEW" FONT 8, "MS Sans Serif", 0, 0, 0x0 BEGIN COMBOBOX IDC_PAL_SELECT,4,13,90,14,CBS_DROPDOWN | WS_TABSTOP @@ -1068,22 +1068,23 @@ BEGIN LTEXT "Mode :",IDC_STATIC,4,20,45,8 LTEXT "Palette :",IDC_STATIC,4,30,45,8 LTEXT "Prio :",IDC_STATIC,4,40,45,8 - LTEXT "Char base :",IDC_STATIC,4,50,45,8 - LTEXT "Screen base :",IDC_STATIC,4,60,45,8 - LTEXT "Size :",IDC_STATIC,4,70,45,8 - LTEXT "Scroll :",IDC_STATIC,4,80,45,8 + LTEXT "Char base :",IDC_STATIC,3,61,45,8 + LTEXT "Screen base :",IDC_STATIC,3,71,45,8 + LTEXT "Size :",IDC_STATIC,3,81,45,8 + LTEXT "Scroll :",IDC_STATIC,3,91,45,8 LTEXT "",IDC_MODE,48,20,85,8 LTEXT "",IDC_PAL,48,30,85,8 LTEXT "",IDC_PRIO,48,40,85,8 - LTEXT "",IDC_CHAR,48,50,85,8 + LTEXT "",IDC_VISIBLE,48,50,62,8 LTEXT "",IDC_SCR,48,60,85,8 LTEXT "",IDC_MSIZE,48,70,85,8 LTEXT "",IDC_SCROLL,48,80,85,8 PUSHBUTTON "&Close",IDC_FERMER,4,300,50,14 - CONTROL "&Auto-update",IDC_AUTO_UPDATE,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,4,92,54,14 - EDITTEXT IDC_AUTO_UPDATE_SECS,59,93,12,14,ES_AUTOHSCROLL | ES_READONLY | WS_DISABLED - CONTROL "",IDC_AUTO_UPDATE_SPIN,"msctls_updown32",UDS_SETBUDDYINT | UDS_AUTOBUDDY | UDS_ARROWKEYS | WS_DISABLED,71,93,11,14 - LTEXT "secs",IDC_STATIC,83,96,16,8 + CONTROL "&Auto-update",IDC_AUTO_UPDATE,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,4,102,54,14 + EDITTEXT IDC_AUTO_UPDATE_SECS,59,103,12,14,ES_AUTOHSCROLL | ES_READONLY | WS_DISABLED + CONTROL "",IDC_AUTO_UPDATE_SPIN,"msctls_updown32",UDS_SETBUDDYINT | UDS_AUTOBUDDY | UDS_ARROWKEYS | WS_DISABLED,71,103,11,14 + LTEXT "secs",IDC_STATIC,83,106,16,8 + LTEXT "Visible :",IDC_STATIC,4,50,38,8 END IDD_OAM DIALOGEX 0, 0, 300, 200 diff --git a/desmume/src/windows/tileView.cpp b/desmume/src/windows/tileView.cpp index ba338b9f2..5ac79289f 100644 --- a/desmume/src/windows/tileView.cpp +++ b/desmume/src/windows/tileView.cpp @@ -314,6 +314,10 @@ LRESULT CALLBACK MiniTileViewBoxProc(HWND hwnd, UINT msg, WPARAM wParam, LPARAM BOOL CALLBACK ViewTilesProc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam) { + //bail out early if the dialog isnt initialized + if(!TileView && message != WM_INITDIALOG) + return false; + switch (message) { case WM_INITDIALOG : @@ -628,5 +632,5 @@ BOOL CALLBACK ViewTilesProc (HWND hwnd, UINT message, WPARAM wParam, LPARAM lPar } return 0; } - return DefWindowProc(hwnd, message, wParam, lParam); + return FALSE; }