diff --git a/desmume/src/MMU.c b/desmume/src/MMU.c index 2e58dd93b..ba7b0fa05 100644 --- a/desmume/src/MMU.c +++ b/desmume/src/MMU.c @@ -2918,14 +2918,14 @@ void FASTCALL MMU_doDMA(u32 proc, u32 num) if ((MMU.DMACrt[proc][num]>>26)&1) for(; i < taille; ++i) { - MMU_writeWord(proc, dst, MMU_readWord(proc, src)); + MMU_write32(proc, dst, MMU_read32(proc, src)); dst += dstinc; src += srcinc; } else for(; i < taille; ++i) { - MMU_write16(proc, dst, MMU_readHWord(proc, src)); + MMU_write16(proc, dst, MMU_read16(proc, src)); dst += dstinc; src += srcinc; } diff --git a/desmume/src/MMU.h b/desmume/src/MMU.h index 9a76ea793..e609b4165 100644 --- a/desmume/src/MMU.h +++ b/desmume/src/MMU.h @@ -145,13 +145,10 @@ void MMU_clearMem( void); void MMU_setRom(u8 * rom, u32 mask); void MMU_unsetRom( void); -#define MMU_readByte MMU_read8 -#define MMU_readHWord MMU_read16 -#define MMU_readWord MMU_read32 -#define MMU_readByteACL MMU_read8_acl -#define MMU_readHWordACL MMU_read16_acl -#define MMU_readWordACL MMU_read32_acl +/** + * Memory reading + */ u8 FASTCALL MMU_read8(u32 proc, u32 adr); u16 FASTCALL MMU_read16(u32 proc, u32 adr); u32 FASTCALL MMU_read32(u32 proc, u32 adr); @@ -166,17 +163,12 @@ u32 FASTCALL MMU_read32(u32 proc, u32 adr); #define MMU_read32_acl(proc,adr,access) MMU_read32(proc,adr) #endif -#define MMU_writeByte MMU_write8 -#define MMU_writeHWord MMU_write16 -#define MMU_writeWord MMU_write32 -#define MMU_writeByteACL MMU_write8_acl -#define MMU_writeHWordACL MMU_write16_acl -#define MMU_writeWordACL MMU_write32_acl - +/** + * Memory writing + */ void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val); void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val); void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val); -void FASTCALL MMU_writeXX(u32 proc, u32 adr, u32 val, u8 nbbytes); #ifdef MMU_ENABLE_ACL void FASTCALL MMU_write8_acl(u32 proc, u32 adr, u8 val); diff --git a/desmume/src/NDSSystem.c b/desmume/src/NDSSystem.c index 6f753dba8..9c66d0425 100644 --- a/desmume/src/NDSSystem.c +++ b/desmume/src/NDSSystem.c @@ -136,10 +136,14 @@ copy_firmware_user_data( u8 *dest_buffer, const u8 *fw_data) { } +#ifdef GDB_STUB int NDS_Init( struct armcpu_memory_iface *arm9_mem_if, struct armcpu_ctrl_iface **arm9_ctrl_iface, struct armcpu_memory_iface *arm7_mem_if, struct armcpu_ctrl_iface **arm7_ctrl_iface) { +#else +int NDS_Init( void) { +#endif nds.ARM9Cycle = 0; nds.ARM7Cycle = 0; nds.cycles = 0; @@ -151,8 +155,13 @@ int NDS_Init( struct armcpu_memory_iface *arm9_mem_if, if (Screen_Init(GFXCORE_DUMMY) != 0) return -1; + #ifdef GDB_STUB armcpu_new(&NDS_ARM7,1, arm7_mem_if, arm7_ctrl_iface); armcpu_new(&NDS_ARM9,0, arm9_mem_if, arm9_ctrl_iface); +#else + armcpu_new(&NDS_ARM7,1); + armcpu_new(&NDS_ARM9,0); +#endif if (SPU_Init(SNDCORE_DUMMY, 735) != 0) return -1; @@ -429,7 +438,7 @@ void NDS_Reset( void) for(i = 0; i < (header->ARM9binSize>>2); ++i) { - MMU_writeWord(0, dst, T1ReadLong(MMU.CART_ROM, src)); + MMU_write32(0, dst, T1ReadLong(MMU.CART_ROM, src)); dst += 4; src += 4; } @@ -439,7 +448,7 @@ void NDS_Reset( void) for(i = 0; i < (header->ARM7binSize>>2); ++i) { - MMU_writeWord(1, dst, T1ReadLong(MMU.CART_ROM, src)); + MMU_write32(1, dst, T1ReadLong(MMU.CART_ROM, src)); dst += 4; src += 4; } @@ -459,9 +468,9 @@ void NDS_Reset( void) nds.lignerendu = FALSE; nds.touchX = nds.touchY = 0; - MMU_writeHWord(0, 0x04000130, 0x3FF); - MMU_writeHWord(1, 0x04000130, 0x3FF); - MMU_writeByte(1, 0x04000136, 0x43); + MMU_write16(0, 0x04000130, 0x3FF); + MMU_write16(1, 0x04000130, 0x3FF); + MMU_write8(1, 0x04000136, 0x43); /* * Setup a copy of the firmware user settings in memory. @@ -473,63 +482,63 @@ void NDS_Reset( void) if ( copy_firmware_user_data( temp_buffer, MMU.fw.data)) { for ( fw_index = 0; fw_index < NDS_FW_USER_SETTINGS_MEM_BYTE_COUNT; fw_index++) { - MMU_writeByte( 0, 0x027FFC80 + fw_index, temp_buffer[fw_index]); + MMU_write8( 0, 0x027FFC80 + fw_index, temp_buffer[fw_index]); } } } - MMU_writeWord(0, 0x027FFE40, header->FNameTblOff); - MMU_writeWord(0, 0x027FFE44, header->FNameTblSize); - MMU_writeWord(0, 0x027FFE48, header->FATOff); - MMU_writeWord(0, 0x027FFE4C, header->FATSize); + MMU_write32(0, 0x027FFE40, header->FNameTblOff); + MMU_write32(0, 0x027FFE44, header->FNameTblSize); + MMU_write32(0, 0x027FFE48, header->FATOff); + MMU_write32(0, 0x027FFE4C, header->FATSize); - MMU_writeWord(0, 0x027FFE50, header->ARM9OverlayOff); - MMU_writeWord(0, 0x027FFE54, header->ARM9OverlaySize); - MMU_writeWord(0, 0x027FFE58, header->ARM7OverlayOff); - MMU_writeWord(0, 0x027FFE5C, header->ARM7OverlaySize); + MMU_write32(0, 0x027FFE50, header->ARM9OverlayOff); + MMU_write32(0, 0x027FFE54, header->ARM9OverlaySize); + MMU_write32(0, 0x027FFE58, header->ARM7OverlayOff); + MMU_write32(0, 0x027FFE5C, header->ARM7OverlaySize); - MMU_writeWord(0, 0x027FFE60, header->unknown2a); - MMU_writeWord(0, 0x027FFE64, header->unknown2b); //merci EACKiX + MMU_write32(0, 0x027FFE60, header->unknown2a); + MMU_write32(0, 0x027FFE64, header->unknown2b); //merci EACKiX - MMU_writeWord(0, 0x027FFE70, header->ARM9unk); - MMU_writeWord(0, 0x027FFE74, header->ARM7unk); + MMU_write32(0, 0x027FFE70, header->ARM9unk); + MMU_write32(0, 0x027FFE74, header->ARM7unk); - MMU_writeWord(0, 0x027FFF9C, 0x027FFF90); // ?????? besoin d'avoir la vrai valeur sur ds + MMU_write32(0, 0x027FFF9C, 0x027FFF90); // ?????? besoin d'avoir la vrai valeur sur ds MainScreen.offset = 192; SubScreen.offset = 0; - //MMU_writeWord(0, 0x02007FFC, 0xE92D4030); + //MMU_write32(0, 0x02007FFC, 0xE92D4030); //ARM7 BIOS IRQ HANDLER - MMU_writeWord(1, 0x00, 0xE25EF002); - MMU_writeWord(1, 0x04, 0xEAFFFFFE); - MMU_writeWord(1, 0x18, 0xEA000000); - MMU_writeWord(1, 0x20, 0xE92D500F); - MMU_writeWord(1, 0x24, 0xE3A00301); - MMU_writeWord(1, 0x28, 0xE28FE000); - MMU_writeWord(1, 0x2C, 0xE510F004); - MMU_writeWord(1, 0x30, 0xE8BD500F); - MMU_writeWord(1, 0x34, 0xE25EF004); + MMU_write32(1, 0x00, 0xE25EF002); + MMU_write32(1, 0x04, 0xEAFFFFFE); + MMU_write32(1, 0x18, 0xEA000000); + MMU_write32(1, 0x20, 0xE92D500F); + MMU_write32(1, 0x24, 0xE3A00301); + MMU_write32(1, 0x28, 0xE28FE000); + MMU_write32(1, 0x2C, 0xE510F004); + MMU_write32(1, 0x30, 0xE8BD500F); + MMU_write32(1, 0x34, 0xE25EF004); //ARM9 BIOS IRQ HANDLER - MMU_writeWord(0, 0xFFFF0018, 0xEA000000); - MMU_writeWord(0, 0xFFFF0020, 0xE92D500F); - MMU_writeWord(0, 0xFFFF0024, 0xEE190F11); - MMU_writeWord(0, 0xFFFF0028, 0xE1A00620); - MMU_writeWord(0, 0xFFFF002C, 0xE1A00600); - MMU_writeWord(0, 0xFFFF0030, 0xE2800C40); - MMU_writeWord(0, 0xFFFF0034, 0xE28FE000); - MMU_writeWord(0, 0xFFFF0038, 0xE510F004); - MMU_writeWord(0, 0xFFFF003C, 0xE8BD500F); - MMU_writeWord(0, 0xFFFF0040, 0xE25EF004); + MMU_write32(0, 0xFFFF0018, 0xEA000000); + MMU_write32(0, 0xFFFF0020, 0xE92D500F); + MMU_write32(0, 0xFFFF0024, 0xEE190F11); + MMU_write32(0, 0xFFFF0028, 0xE1A00620); + MMU_write32(0, 0xFFFF002C, 0xE1A00600); + MMU_write32(0, 0xFFFF0030, 0xE2800C40); + MMU_write32(0, 0xFFFF0034, 0xE28FE000); + MMU_write32(0, 0xFFFF0038, 0xE510F004); + MMU_write32(0, 0xFFFF003C, 0xE8BD500F); + MMU_write32(0, 0xFFFF0040, 0xE25EF004); - MMU_writeWord(0, 0x0000004, 0xE3A0010E); - MMU_writeWord(0, 0x0000008, 0xE3A01020); -// MMU_writeWord(0, 0x000000C, 0xE1B02110); - MMU_writeWord(0, 0x000000C, 0xE1B02040); - MMU_writeWord(0, 0x0000010, 0xE3B02020); -// MMU_writeWord(0, 0x0000010, 0xE2100202); + MMU_write32(0, 0x0000004, 0xE3A0010E); + MMU_write32(0, 0x0000008, 0xE3A01020); +// MMU_write32(0, 0x000000C, 0xE1B02110); + MMU_write32(0, 0x000000C, 0xE1B02040); + MMU_write32(0, 0x0000010, 0xE3B02020); +// MMU_write32(0, 0x0000010, 0xE2100202); free(header); @@ -1448,28 +1457,32 @@ NDS_exec(s32 nb, BOOL force) if((MMU.DMACrt[1][3])&(1<<30)) NDS_makeARM7Int(11); MMU.DMAing[1][3] = FALSE; } - - if((MMU.reg_IF[0]&MMU.reg_IE[0]) && (MMU.reg_IME[0])) - //if(NDS_ARM9.irqExeption()) - if ( armcpu_flagIrq( &NDS_ARM9)) { - nds.ARM9Cycle = nds.cycles; - } - /* - if(armcpu_irqExeption(&NDS_ARM9)) - { - nds.ARM9Cycle = nds.cycles; - } - */ - - if((MMU.reg_IF[1]&MMU.reg_IE[1]) && (MMU.reg_IME[1])) - if ( armcpu_flagIrq( &NDS_ARM7)) { - nds.ARM7Cycle = nds.cycles; - } - /* - if (armcpu_irqExeption(&NDS_ARM7)) - nds.ARM7Cycle = nds.cycles; - */ + + if((MMU.reg_IF[0]&MMU.reg_IE[0]) && (MMU.reg_IME[0])) + { +#ifdef GDB_STUB + if ( armcpu_flagIrq( &NDS_ARM9)) +#else + if ( armcpu_irqExeption(&NDS_ARM9)) +#endif + { + nds.ARM9Cycle = nds.cycles; + } + } + + if((MMU.reg_IF[1]&MMU.reg_IE[1]) && (MMU.reg_IME[1])) + { +#ifdef GDB_STUB + if ( armcpu_flagIrq( &NDS_ARM7)) +#else + if ( armcpu_irqExeption(&NDS_ARM7)) +#endif + { + nds.ARM7Cycle = nds.cycles; + } + } } - return nds.cycles; + + return nds.cycles; } diff --git a/desmume/src/NDSSystem.h b/desmume/src/NDSSystem.h index c6ed5f188..9206d865e 100644 --- a/desmume/src/NDSSystem.h +++ b/desmume/src/NDSSystem.h @@ -166,10 +166,15 @@ struct NDS_fw_config_data { extern NDSSystem nds; +#ifdef GDB_STUB int NDS_Init( struct armcpu_memory_iface *arm9_mem_if, struct armcpu_ctrl_iface **arm9_ctrl_iface, struct armcpu_memory_iface *arm7_mem_if, struct armcpu_ctrl_iface **arm7_ctrl_iface); +#else +int NDS_Init ( void); +#endif + void NDS_DeInit(void); void NDS_FillDefaultFirmwareConfigData( struct NDS_fw_config_data *fw_config); diff --git a/desmume/src/arm_instructions.c b/desmume/src/arm_instructions.c index bfe41f7cd..3b0df3a86 100644 --- a/desmume/src/arm_instructions.c +++ b/desmume/src/arm_instructions.c @@ -26,13 +26,25 @@ #include "debug.h" #include "MMU.h" -//#define ASM_CORE -//#define C_CORE -//s8 CFlag; -//s8 ZFlag; -//s8 NFlag; -//s8 OFlag; +// Use this macros for reading/writing, so the GDB stub isn't broken +#ifdef GDB_STUB + #define READ32(a,b) cpu->mem_if->read32(a,b) + #define WRITE32(a,b,c) cpu->mem_if->write32(a,b,c) + #define READ16(a,b) cpu->mem_if->read16(a,b) + #define WRITE16(a,b,c) cpu->mem_if->write16(a,b,c) + #define READ8(a,b) cpu->mem_if->read8(a,b) + #define WRITE8(a,b,c) cpu->mem_if->write8(a,b,c) +#else + #define READ32(a,b) MMU_read32(cpu->proc_ID, b) + #define WRITE32(a,b,c) MMU_write32(cpu->proc_ID,b,c) + #define READ16(a,b) MMU_read16(cpu->proc_ID, b) + #define WRITE16(a,b,c) MMU_write16(cpu->proc_ID,b,c) + #define READ8(a,b) MMU_read8(cpu->proc_ID, b) + #define WRITE8(a,b,c) MMU_write8(cpu->proc_ID,b,c) +#endif + + #define LSL_IMM shift_op = cpu->R[REG_POS(i,0)]<<((i>>7)&0x1F); @@ -2790,9 +2802,9 @@ static u32 FASTCALL OP_SWP(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - u32 tmp = ROR(cpu->mem_if->read32(cpu->mem_if->data, adr), ((cpu->R[REG_POS(i,16)]&3)<<3)); + u32 tmp = ROR(READ32(cpu->mem_if->data, adr), ((cpu->R[REG_POS(i,16)]&3)<<3)); - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,0)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,0)]); cpu->R[REG_POS(i,12)] = tmp; return 4 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]*2; @@ -2802,8 +2814,8 @@ static u32 FASTCALL OP_SWPB(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - u8 tmp = cpu->mem_if->read8(cpu->mem_if->data, adr); - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)(cpu->R[REG_POS(i,0)]&0xFF)); + u8 tmp = READ8(cpu->mem_if->data, adr); + WRITE8(cpu->mem_if->data, adr, (u8)(cpu->R[REG_POS(i,0)]&0xFF)); cpu->R[REG_POS(i,12)] = tmp; return 4 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]*2; @@ -2815,7 +2827,7 @@ static u32 FASTCALL OP_LDRH_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; - cpu->R[REG_POS(i,12)] = (u32)cpu->mem_if->read16(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -2824,7 +2836,7 @@ static u32 FASTCALL OP_LDRH_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; - cpu->R[REG_POS(i,12)] = (u32)cpu->mem_if->read16(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -2833,7 +2845,7 @@ static u32 FASTCALL OP_LDRH_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (u32)cpu->mem_if->read16(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -2842,7 +2854,7 @@ static u32 FASTCALL OP_LDRH_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (u32)cpu->mem_if->read16(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -2852,7 +2864,7 @@ static u32 FASTCALL OP_LDRH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu) u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = (u32)cpu->mem_if->read16(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -2862,7 +2874,7 @@ static u32 FASTCALL OP_LDRH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu) u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = (u32)cpu->mem_if->read16(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -2873,7 +2885,7 @@ static u32 FASTCALL OP_LDRH_PRE_INDE_P_REG_OFF(armcpu_t *cpu) u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] =(u32)cpu->mem_if->read16(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] =(u32)READ16(cpu->mem_if->data, adr); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -2883,7 +2895,7 @@ static u32 FASTCALL OP_LDRH_PRE_INDE_M_REG_OFF(armcpu_t *cpu) u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = (u32)cpu->mem_if->read16(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -2892,7 +2904,7 @@ static u32 FASTCALL OP_LDRH_POS_INDE_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (u32)cpu->mem_if->read16(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] += IMM_OFF; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -2902,7 +2914,7 @@ static u32 FASTCALL OP_LDRH_POS_INDE_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (u32)cpu->mem_if->read16(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] -= IMM_OFF; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -2912,7 +2924,7 @@ static u32 FASTCALL OP_LDRH_POS_INDE_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (u32)cpu->mem_if->read16(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -2922,7 +2934,7 @@ static u32 FASTCALL OP_LDRH_POS_INDE_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (u32)cpu->mem_if->read16(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -2934,7 +2946,7 @@ static u32 FASTCALL OP_STRH_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; - cpu->mem_if->write16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -2943,7 +2955,7 @@ static u32 FASTCALL OP_STRH_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; - cpu->mem_if->write16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -2952,7 +2964,7 @@ static u32 FASTCALL OP_STRH_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; - cpu->mem_if->write16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -2961,7 +2973,7 @@ static u32 FASTCALL OP_STRH_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; - cpu->mem_if->write16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -2971,7 +2983,7 @@ static u32 FASTCALL OP_STRH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu) u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; cpu->R[REG_POS(i,16)] = adr; - cpu->mem_if->write16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -2980,7 +2992,7 @@ static u32 FASTCALL OP_STRH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; - cpu->mem_if->write16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -2990,7 +3002,7 @@ static u32 FASTCALL OP_STRH_PRE_INDE_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; - cpu->mem_if->write16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3000,7 +3012,7 @@ static u32 FASTCALL OP_STRH_PRE_INDE_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; - cpu->mem_if->write16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3010,7 +3022,7 @@ static u32 FASTCALL OP_STRH_POS_INDE_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] += IMM_OFF; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3020,7 +3032,7 @@ static u32 FASTCALL OP_STRH_POS_INDE_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] -= IMM_OFF; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3030,7 +3042,7 @@ static u32 FASTCALL OP_STRH_POS_INDE_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3040,7 +3052,7 @@ static u32 FASTCALL OP_STRH_POS_INDE_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3052,7 +3064,7 @@ static u32 FASTCALL OP_LDRSH_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; - cpu->R[REG_POS(i,12)] = (s32)((s16)cpu->mem_if->read16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -3061,7 +3073,7 @@ static u32 FASTCALL OP_LDRSH_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; - cpu->R[REG_POS(i,12)] = (s32)((s16)cpu->mem_if->read16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -3070,7 +3082,7 @@ static u32 FASTCALL OP_LDRSH_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (s32)((s16)cpu->mem_if->read16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -3079,7 +3091,7 @@ static u32 FASTCALL OP_LDRSH_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (s32)((s16)cpu->mem_if->read16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -3088,7 +3100,7 @@ static u32 FASTCALL OP_LDRSH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; - cpu->R[REG_POS(i,12)] = (s32)((s16)cpu->mem_if->read16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3098,7 +3110,7 @@ static u32 FASTCALL OP_LDRSH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; - cpu->R[REG_POS(i,12)] = (s32)((s16)cpu->mem_if->read16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3108,7 +3120,7 @@ static u32 FASTCALL OP_LDRSH_PRE_INDE_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (s32)((s16)cpu->mem_if->read16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3118,7 +3130,7 @@ static u32 FASTCALL OP_LDRSH_PRE_INDE_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (s32)((s16)cpu->mem_if->read16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3128,7 +3140,7 @@ static u32 FASTCALL OP_LDRSH_POS_INDE_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (s32)((s16)cpu->mem_if->read16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] += IMM_OFF; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3138,7 +3150,7 @@ static u32 FASTCALL OP_LDRSH_POS_INDE_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (s32)((s16)cpu->mem_if->read16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] -= IMM_OFF; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3148,7 +3160,7 @@ static u32 FASTCALL OP_LDRSH_POS_INDE_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (s32)((s16)cpu->mem_if->read16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3158,7 +3170,7 @@ static u32 FASTCALL OP_LDRSH_POS_INDE_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (s32)((s16)cpu->mem_if->read16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3170,7 +3182,7 @@ static u32 FASTCALL OP_LDRSB_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; - cpu->R[REG_POS(i,12)] = (s32)((s8)cpu->mem_if->read8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -3179,7 +3191,7 @@ static u32 FASTCALL OP_LDRSB_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; - cpu->R[REG_POS(i,12)] = (s32)((s8)cpu->mem_if->read8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -3188,7 +3200,7 @@ static u32 FASTCALL OP_LDRSB_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (s32)((s8)cpu->mem_if->read8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -3197,7 +3209,7 @@ static u32 FASTCALL OP_LDRSB_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (s32)((s8)cpu->mem_if->read8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -3206,7 +3218,7 @@ static u32 FASTCALL OP_LDRSB_PRE_INDE_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; - cpu->R[REG_POS(i,12)] = (s32)((s8)cpu->mem_if->read8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3216,7 +3228,7 @@ static u32 FASTCALL OP_LDRSB_PRE_INDE_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; - cpu->R[REG_POS(i,12)] = (s32)((s8)cpu->mem_if->read8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3226,7 +3238,7 @@ static u32 FASTCALL OP_LDRSB_PRE_INDE_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (s32)((s8)cpu->mem_if->read8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3236,7 +3248,7 @@ static u32 FASTCALL OP_LDRSB_PRE_INDE_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (s32)((s8)cpu->mem_if->read8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3246,7 +3258,7 @@ static u32 FASTCALL OP_LDRSB_POS_INDE_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (s32)((s8)cpu->mem_if->read8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] += IMM_OFF; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3256,7 +3268,7 @@ static u32 FASTCALL OP_LDRSB_POS_INDE_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (s32)((s8)cpu->mem_if->read8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] -= IMM_OFF; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3266,7 +3278,7 @@ static u32 FASTCALL OP_LDRSB_POS_INDE_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (s32)((s8)cpu->mem_if->read8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3276,7 +3288,7 @@ static u32 FASTCALL OP_LDRSB_POS_INDE_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (s32)((s8)cpu->mem_if->read8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -3828,7 +3840,7 @@ static u32 FASTCALL OP_LDR_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - u32 val = cpu->mem_if->read32(cpu->mem_if->data, adr); + u32 val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -3849,7 +3861,7 @@ static u32 FASTCALL OP_LDR_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - u32 val = cpu->mem_if->read32(cpu->mem_if->data, adr); + u32 val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -3875,7 +3887,7 @@ static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -3901,7 +3913,7 @@ static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -3927,7 +3939,7 @@ static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -3953,7 +3965,7 @@ static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -3979,7 +3991,7 @@ static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4005,7 +4017,7 @@ static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4031,7 +4043,7 @@ static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4057,7 +4069,7 @@ static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4080,7 +4092,7 @@ static u32 FASTCALL OP_LDR_P_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - u32 val = cpu->mem_if->read32(cpu->mem_if->data, adr); + u32 val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4104,7 +4116,7 @@ static u32 FASTCALL OP_LDR_M_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - u32 val = cpu->mem_if->read32(cpu->mem_if->data, adr); + u32 val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4133,7 +4145,7 @@ static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4162,7 +4174,7 @@ static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4191,7 +4203,7 @@ static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4220,7 +4232,7 @@ static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4249,7 +4261,7 @@ static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4278,7 +4290,7 @@ static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4307,7 +4319,7 @@ static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4336,7 +4348,7 @@ static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4360,7 +4372,7 @@ static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - u32 val = cpu->mem_if->read32(cpu->mem_if->data, adr); + u32 val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4386,7 +4398,7 @@ static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND2(armcpu_t *cpu) u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - u32 val = cpu->mem_if->read32(cpu->mem_if->data, adr); + u32 val = READ32(cpu->mem_if->data, adr); u32 old; if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4415,7 +4427,7 @@ static u32 FASTCALL OP_LDR_M_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - u32 val = cpu->mem_if->read32(cpu->mem_if->data, adr); + u32 val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4443,7 +4455,7 @@ static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4471,7 +4483,7 @@ static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4499,7 +4511,7 @@ static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4527,7 +4539,7 @@ static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4555,7 +4567,7 @@ static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4583,7 +4595,7 @@ static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4611,7 +4623,7 @@ static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4639,7 +4651,7 @@ static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read32(cpu->mem_if->data, adr); + val = READ32(cpu->mem_if->data, adr); if(adr&3) val = ROR(val, 8*(adr&3)); @@ -4665,7 +4677,7 @@ static u32 FASTCALL OP_LDRB_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - u32 val = cpu->mem_if->read8(cpu->mem_if->data, adr); + u32 val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -4675,7 +4687,7 @@ static u32 FASTCALL OP_LDRB_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - u32 val = cpu->mem_if->read8(cpu->mem_if->data, adr); + u32 val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -4689,7 +4701,7 @@ static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -4703,7 +4715,7 @@ static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -4717,7 +4729,7 @@ static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -4731,7 +4743,7 @@ static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -4745,7 +4757,7 @@ static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -4759,7 +4771,7 @@ static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -4773,7 +4785,7 @@ static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -4787,7 +4799,7 @@ static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr; @@ -4798,7 +4810,7 @@ static u32 FASTCALL OP_LDRB_P_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - u32 val = cpu->mem_if->read8(cpu->mem_if->data, adr); + u32 val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; @@ -4811,7 +4823,7 @@ static u32 FASTCALL OP_LDRB_M_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - u32 val = cpu->mem_if->read8(cpu->mem_if->data, adr); + u32 val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; @@ -4827,7 +4839,7 @@ static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; @@ -4844,7 +4856,7 @@ static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; @@ -4860,7 +4872,7 @@ static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; @@ -4875,7 +4887,7 @@ static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; @@ -4890,7 +4902,7 @@ static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; @@ -4905,7 +4917,7 @@ static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; @@ -4920,7 +4932,7 @@ static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; @@ -4935,7 +4947,7 @@ static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; @@ -4946,7 +4958,7 @@ static u32 FASTCALL OP_LDRB_P_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - u32 val = cpu->mem_if->read8(cpu->mem_if->data, adr); + u32 val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; cpu->R[REG_POS(i,12)] = val; @@ -4957,7 +4969,7 @@ static u32 FASTCALL OP_LDRB_M_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - u32 val = cpu->mem_if->read8(cpu->mem_if->data, adr); + u32 val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; cpu->R[REG_POS(i,12)] = val; @@ -4972,7 +4984,7 @@ static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; @@ -4987,7 +4999,7 @@ static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; @@ -5002,7 +5014,7 @@ static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; @@ -5017,7 +5029,7 @@ static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; @@ -5032,7 +5044,7 @@ static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; @@ -5047,7 +5059,7 @@ static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; @@ -5062,7 +5074,7 @@ static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr + shift_op; cpu->R[REG_POS(i,12)] = val; @@ -5077,7 +5089,7 @@ static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,16)] = adr - shift_op; cpu->R[REG_POS(i,12)] = val; @@ -5090,7 +5102,7 @@ static u32 FASTCALL OP_STR_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); // execute = false; @@ -5101,7 +5113,7 @@ static u32 FASTCALL OP_STR_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5113,7 +5125,7 @@ static u32 FASTCALL OP_STR_P_LSL_IMM_OFF(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5125,7 +5137,7 @@ static u32 FASTCALL OP_STR_M_LSL_IMM_OFF(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5137,7 +5149,7 @@ static u32 FASTCALL OP_STR_P_LSR_IMM_OFF(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5149,7 +5161,7 @@ static u32 FASTCALL OP_STR_M_LSR_IMM_OFF(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5161,7 +5173,7 @@ static u32 FASTCALL OP_STR_P_ASR_IMM_OFF(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5173,7 +5185,7 @@ static u32 FASTCALL OP_STR_M_ASR_IMM_OFF(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5185,7 +5197,7 @@ static u32 FASTCALL OP_STR_P_ROR_IMM_OFF(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5197,7 +5209,7 @@ static u32 FASTCALL OP_STR_M_ROR_IMM_OFF(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5207,7 +5219,7 @@ static u32 FASTCALL OP_STR_P_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5217,7 +5229,7 @@ static u32 FASTCALL OP_STR_M_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5230,7 +5242,7 @@ static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5243,7 +5255,7 @@ static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5256,7 +5268,7 @@ static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5269,7 +5281,7 @@ static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5282,7 +5294,7 @@ static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5295,7 +5307,7 @@ static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5308,7 +5320,7 @@ static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5321,7 +5333,7 @@ static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5331,7 +5343,7 @@ static u32 FASTCALL OP_STR_P_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5341,7 +5353,7 @@ static u32 FASTCALL OP_STR_M_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5354,7 +5366,7 @@ static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5367,7 +5379,7 @@ static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5380,7 +5392,7 @@ static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5393,7 +5405,7 @@ static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5406,7 +5418,7 @@ static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5419,7 +5431,7 @@ static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5432,7 +5444,7 @@ static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5445,7 +5457,7 @@ static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; @@ -5457,7 +5469,7 @@ static u32 FASTCALL OP_STRB_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5466,7 +5478,7 @@ static u32 FASTCALL OP_STRB_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5478,7 +5490,7 @@ static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5490,7 +5502,7 @@ static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5502,7 +5514,7 @@ static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5514,7 +5526,7 @@ static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5526,7 +5538,7 @@ static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5538,7 +5550,7 @@ static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5550,7 +5562,7 @@ static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5562,7 +5574,7 @@ static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5571,7 +5583,7 @@ static u32 FASTCALL OP_STRB_P_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - cpu->mem_if->write8(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5581,7 +5593,7 @@ static u32 FASTCALL OP_STRB_M_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5594,7 +5606,7 @@ static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5607,7 +5619,7 @@ static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5620,7 +5632,7 @@ static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5633,7 +5645,7 @@ static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5646,7 +5658,7 @@ static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5659,7 +5671,7 @@ static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5672,7 +5684,7 @@ static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] + shift_op; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5685,7 +5697,7 @@ static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)] - shift_op; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5695,7 +5707,7 @@ static u32 FASTCALL OP_STRB_P_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5705,7 +5717,7 @@ static u32 FASTCALL OP_STRB_M_IMM_OFF_POSTIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5718,7 +5730,7 @@ static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5731,7 +5743,7 @@ static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; LSL_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5744,7 +5756,7 @@ static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5757,7 +5769,7 @@ static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; LSR_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5770,7 +5782,7 @@ static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5783,7 +5795,7 @@ static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; ASR_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5796,7 +5808,7 @@ static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5809,7 +5821,7 @@ static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) u32 shift_op; ROR_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5830,7 +5842,7 @@ static u32 FASTCALL OP_LDRBT_P_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; @@ -5854,7 +5866,7 @@ static u32 FASTCALL OP_LDRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; @@ -5879,7 +5891,7 @@ static u32 FASTCALL OP_LDRBT_P_REG_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr + cpu->R[REG_POS(i,0)]; @@ -5905,7 +5917,7 @@ static u32 FASTCALL OP_LDRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; LSL_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr + shift_op; @@ -5932,7 +5944,7 @@ static u32 FASTCALL OP_LDRBT_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; LSL_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr - shift_op; @@ -5959,7 +5971,7 @@ static u32 FASTCALL OP_LDRBT_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; LSR_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr + shift_op; @@ -5986,7 +5998,7 @@ static u32 FASTCALL OP_LDRBT_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; LSR_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr - shift_op; @@ -6013,7 +6025,7 @@ static u32 FASTCALL OP_LDRBT_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; ASR_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr + shift_op; @@ -6040,7 +6052,7 @@ static u32 FASTCALL OP_LDRBT_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; ASR_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr - shift_op; @@ -6067,7 +6079,7 @@ static u32 FASTCALL OP_LDRBT_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; ROR_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr + shift_op; @@ -6094,7 +6106,7 @@ static u32 FASTCALL OP_LDRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; ROR_IMM; adr = cpu->R[REG_POS(i,16)]; - val = cpu->mem_if->read8(cpu->mem_if->data, adr); + val = READ8(cpu->mem_if->data, adr); cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr - shift_op; @@ -6119,7 +6131,7 @@ static u32 FASTCALL OP_STRBT_P_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; armcpu_switchMode(cpu, oldmode); @@ -6141,7 +6153,7 @@ static u32 FASTCALL OP_STRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; armcpu_switchMode(cpu, oldmode); @@ -6163,7 +6175,7 @@ static u32 FASTCALL OP_STRBT_P_REG_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + cpu->R[REG_POS(i,0)]; armcpu_switchMode(cpu, oldmode); @@ -6185,7 +6197,7 @@ static u32 FASTCALL OP_STRBT_M_REG_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - cpu->R[REG_POS(i,0)]; armcpu_switchMode(cpu, oldmode); @@ -6209,7 +6221,7 @@ static u32 FASTCALL OP_STRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; LSL_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; armcpu_switchMode(cpu, oldmode); @@ -6233,7 +6245,7 @@ static u32 FASTCALL OP_STRBT_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; LSL_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; armcpu_switchMode(cpu, oldmode); @@ -6257,7 +6269,7 @@ static u32 FASTCALL OP_STRBT_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; LSR_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; armcpu_switchMode(cpu, oldmode); @@ -6281,7 +6293,7 @@ static u32 FASTCALL OP_STRBT_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; LSR_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; armcpu_switchMode(cpu, oldmode); @@ -6305,7 +6317,7 @@ static u32 FASTCALL OP_STRBT_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; ASR_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; armcpu_switchMode(cpu, oldmode); @@ -6329,7 +6341,7 @@ static u32 FASTCALL OP_STRBT_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; ASR_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; armcpu_switchMode(cpu, oldmode); @@ -6353,7 +6365,7 @@ static u32 FASTCALL OP_STRBT_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; ROR_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; armcpu_switchMode(cpu, oldmode); @@ -6377,7 +6389,7 @@ static u32 FASTCALL OP_STRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) i = cpu->instruction; ROR_IMM; adr = cpu->R[REG_POS(i,16)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; armcpu_switchMode(cpu, oldmode); @@ -6389,7 +6401,7 @@ static u32 FASTCALL OP_STRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) #define OP_L_IA(reg, adr) if(BIT##reg(i))\ {\ - registres[reg] = cpu->mem_if->read32(cpu->mem_if->data, start);\ + registres[reg] = READ32(cpu->mem_if->data, start);\ c += waitState[(start>>24)&0xF];\ adr += 4;\ } @@ -6397,13 +6409,13 @@ static u32 FASTCALL OP_STRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) #define OP_L_IB(reg, adr) if(BIT##reg(i))\ {\ adr += 4;\ - registres[reg] = cpu->mem_if->read32(cpu->mem_if->data, start);\ + registres[reg] = READ32(cpu->mem_if->data, start);\ c += waitState[(start>>24)&0xF];\ } #define OP_L_DA(reg, adr) if(BIT##reg(i))\ {\ - registres[reg] = cpu->mem_if->read32(cpu->mem_if->data, start);\ + registres[reg] = READ32(cpu->mem_if->data, start);\ c += waitState[(start>>24)&0xF];\ adr -= 4;\ } @@ -6411,7 +6423,7 @@ static u32 FASTCALL OP_STRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) #define OP_L_DB(reg, adr) if(BIT##reg(i))\ {\ adr -= 4;\ - registres[reg] = cpu->mem_if->read32(cpu->mem_if->data, start);\ + registres[reg] = READ32(cpu->mem_if->data, start);\ c += waitState[(start>>24)&0xF];\ } @@ -6442,7 +6454,7 @@ static u32 FASTCALL OP_LDMIA(armcpu_t *cpu) if(BIT15(i)) { - u32 tmp = cpu->mem_if->read32(cpu->mem_if->data, start); + u32 tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR.bits.T = BIT0(tmp); //start += 4; @@ -6483,7 +6495,7 @@ static u32 FASTCALL OP_LDMIB(armcpu_t *cpu) u32 tmp; start += 4; c += waitState[(start>>24)&0xF]; - tmp = cpu->mem_if->read32(cpu->mem_if->data, start); + tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR.bits.T = BIT0(tmp); cpu->next_instruction = registres[15]; @@ -6504,7 +6516,7 @@ static u32 FASTCALL OP_LDMDA(armcpu_t *cpu) if(BIT15(i)) { - u32 tmp = cpu->mem_if->read32(cpu->mem_if->data, start); + u32 tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR.bits.T = BIT0(tmp); c += waitState[(start>>24)&0xF]; @@ -6544,7 +6556,7 @@ static u32 FASTCALL OP_LDMDB(armcpu_t *cpu) { u32 tmp; start -= 4; - tmp = cpu->mem_if->read32(cpu->mem_if->data, start); + tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR.bits.T = BIT0(tmp); cpu->next_instruction = registres[15]; @@ -6603,7 +6615,7 @@ static u32 FASTCALL OP_LDMIA_W(armcpu_t *cpu) if(BIT15(i)) { - u32 tmp = cpu->mem_if->read32(cpu->mem_if->data, start); + u32 tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR.bits.T = BIT0(tmp); c += waitState[(start>>24)&0xF]; @@ -6657,7 +6669,7 @@ static u32 FASTCALL OP_LDMIB_W(armcpu_t *cpu) u32 tmp; start += 4; c += waitState[(start>>24)&0xF]; - tmp = cpu->mem_if->read32(cpu->mem_if->data, start); + tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR.bits.T = BIT0(tmp); cpu->next_instruction = registres[15]; @@ -6691,7 +6703,7 @@ static u32 FASTCALL OP_LDMDA_W(armcpu_t *cpu) if(BIT15(i)) { - u32 tmp = cpu->mem_if->read32(cpu->mem_if->data, start); + u32 tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR.bits.T = BIT0(tmp); c += waitState[(start>>24)&0xF]; @@ -6738,7 +6750,7 @@ static u32 FASTCALL OP_LDMDB_W(armcpu_t *cpu) { u32 tmp; start -= 4; - tmp = cpu->mem_if->read32(cpu->mem_if->data, start); + tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR.bits.T = BIT0(tmp); cpu->next_instruction = registres[15]; @@ -6804,7 +6816,7 @@ static u32 FASTCALL OP_LDMIA2(armcpu_t *cpu) if(BIT15(i)) { - u32 tmp = cpu->mem_if->read32(cpu->mem_if->data, start); + u32 tmp = READ32(cpu->mem_if->data, start); Status_Reg SPSR; cpu->R[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); SPSR = cpu->SPSR; @@ -6862,7 +6874,7 @@ static u32 FASTCALL OP_LDMIB2(armcpu_t *cpu) u32 tmp; Status_Reg SPSR; start += 4; - tmp = cpu->mem_if->read32(cpu->mem_if->data, start); + tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); SPSR = cpu->SPSR; armcpu_switchMode(cpu, SPSR.bits.mode); @@ -6900,7 +6912,7 @@ static u32 FASTCALL OP_LDMDA2(armcpu_t *cpu) if(BIT15(i)) { - u32 tmp = cpu->mem_if->read32(cpu->mem_if->data, start); + u32 tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR = cpu->SPSR; c += waitState[(start>>24)&0xF]; @@ -6962,7 +6974,7 @@ static u32 FASTCALL OP_LDMDB2(armcpu_t *cpu) { u32 tmp; start -= 4; - tmp = cpu->mem_if->read32(cpu->mem_if->data, start); + tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR = cpu->SPSR; cpu->next_instruction = registres[15]; @@ -7045,7 +7057,7 @@ static u32 FASTCALL OP_LDMIA2_W(armcpu_t *cpu) } registres[REG_POS(i,16)] = start + 4; - tmp = cpu->mem_if->read32(cpu->mem_if->data, start); + tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); SPSR = cpu->SPSR; armcpu_switchMode(cpu, SPSR.bits.mode); @@ -7103,7 +7115,7 @@ static u32 FASTCALL OP_LDMIB2_W(armcpu_t *cpu) } registres[REG_POS(i,16)] = start + 4; - tmp = cpu->mem_if->read32(cpu->mem_if->data, start + 4); + tmp = READ32(cpu->mem_if->data, start + 4); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR = cpu->SPSR; cpu->next_instruction = registres[15]; @@ -7138,7 +7150,7 @@ static u32 FASTCALL OP_LDMDA2_W(armcpu_t *cpu) if(BIT15(i)) { - u32 tmp = cpu->mem_if->read32(cpu->mem_if->data, start); + u32 tmp = READ32(cpu->mem_if->data, start); registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); c += waitState[(start>>24)&0xF]; start -= 4; @@ -7200,7 +7212,7 @@ static u32 FASTCALL OP_LDMDB2_W(armcpu_t *cpu) { u32 tmp; start -= 4; - tmp = cpu->mem_if->read32(cpu->mem_if->data, start); + tmp = READ32(cpu->mem_if->data, start); c += waitState[(start>>24)&0xF]; registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->CPSR = cpu->SPSR; @@ -7248,7 +7260,7 @@ static u32 FASTCALL OP_STMIA(armcpu_t *cpu) { if(BIT_N(i, b)) { - cpu->mem_if->write32(cpu->mem_if->data, start, cpu->R[b]); + WRITE32(cpu->mem_if->data, start, cpu->R[b]); c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; start += 4; } @@ -7266,7 +7278,7 @@ static u32 FASTCALL OP_STMIB(armcpu_t *cpu) if(BIT_N(i, b)) { start += 4; - cpu->mem_if->write32(cpu->mem_if->data, start, cpu->R[b]); + WRITE32(cpu->mem_if->data, start, cpu->R[b]); c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; } } @@ -7282,7 +7294,7 @@ static u32 FASTCALL OP_STMDA(armcpu_t *cpu) { if(BIT_N(i, 15-b)) { - cpu->mem_if->write32(cpu->mem_if->data, start, cpu->R[15-b]); + WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; start -= 4; } @@ -7300,7 +7312,7 @@ static u32 FASTCALL OP_STMDB(armcpu_t *cpu) if(BIT_N(i, 15-b)) { start -= 4; - cpu->mem_if->write32(cpu->mem_if->data, start, cpu->R[15-b]); + WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; } } @@ -7316,7 +7328,7 @@ static u32 FASTCALL OP_STMIA_W(armcpu_t *cpu) { if(BIT_N(i, b)) { - cpu->mem_if->write32(cpu->mem_if->data, start, cpu->R[b]); + WRITE32(cpu->mem_if->data, start, cpu->R[b]); c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; start += 4; } @@ -7336,7 +7348,7 @@ static u32 FASTCALL OP_STMIB_W(armcpu_t *cpu) if(BIT_N(i, b)) { start += 4; - cpu->mem_if->write32(cpu->mem_if->data, start, cpu->R[b]); + WRITE32(cpu->mem_if->data, start, cpu->R[b]); c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; } } @@ -7353,7 +7365,7 @@ static u32 FASTCALL OP_STMDA_W(armcpu_t *cpu) { if(BIT_N(i, 15-b)) { - cpu->mem_if->write32(cpu->mem_if->data, start, cpu->R[15-b]); + WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; start -= 4; } @@ -7373,7 +7385,7 @@ static u32 FASTCALL OP_STMDB_W(armcpu_t *cpu) if(BIT_N(i, 15-b)) { start -= 4; - cpu->mem_if->write32(cpu->mem_if->data, start, cpu->R[15-b]); + WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; } } @@ -7402,7 +7414,7 @@ static u32 FASTCALL OP_STMIA2(armcpu_t *cpu) { if(BIT_N(i, b)) { - cpu->mem_if->write32(cpu->mem_if->data, start, cpu->R[b]); + WRITE32(cpu->mem_if->data, start, cpu->R[b]); c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; start += 4; } @@ -7433,7 +7445,7 @@ static u32 FASTCALL OP_STMIB2(armcpu_t *cpu) if(BIT_N(i, b)) { start += 4; - cpu->mem_if->write32(cpu->mem_if->data, start, cpu->R[b]); + WRITE32(cpu->mem_if->data, start, cpu->R[b]); c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; } } @@ -7462,7 +7474,7 @@ static u32 FASTCALL OP_STMDA2(armcpu_t *cpu) { if(BIT_N(i, 15-b)) { - cpu->mem_if->write32(cpu->mem_if->data, start, cpu->R[15-b]); + WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; start -= 4; } @@ -7490,7 +7502,7 @@ static u32 FASTCALL OP_STMDB2(armcpu_t *cpu) if(BIT_N(i, 15-b)) { start -= 4; - cpu->mem_if->write32(cpu->mem_if->data, start, cpu->R[15-b]); + WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; } } @@ -7519,7 +7531,7 @@ static u32 FASTCALL OP_STMIA2_W(armcpu_t *cpu) { if(BIT_N(i, b)) { - cpu->mem_if->write32(cpu->mem_if->data, start, cpu->R[b]); + WRITE32(cpu->mem_if->data, start, cpu->R[b]); c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; start += 4; } @@ -7549,7 +7561,7 @@ static u32 FASTCALL OP_STMIB2_W(armcpu_t *cpu) if(BIT_N(i, b)) { start += 4; - cpu->mem_if->write32(cpu->mem_if->data, start, cpu->R[b]); + WRITE32(cpu->mem_if->data, start, cpu->R[b]); c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; } } @@ -7578,7 +7590,7 @@ static u32 FASTCALL OP_STMDA2_W(armcpu_t *cpu) { if(BIT_N(i, 15-b)) { - cpu->mem_if->write32(cpu->mem_if->data, start, cpu->R[15-b]); + WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; start -= 4; } @@ -7612,7 +7624,7 @@ static u32 FASTCALL OP_STMDB2_W(armcpu_t *cpu) if(BIT_N(i, 15-b)) { start -= 4; - cpu->mem_if->write32(cpu->mem_if->data, start, cpu->R[15-b]); + WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; } } @@ -7650,12 +7662,12 @@ OP_LDRD_STRD_POST_INDEX( armcpu_t *cpu) { if ( !(Rd_num & 0x1)) { /* Store/Load */ if ( BIT5(i)) { - cpu->mem_if->write32(cpu->mem_if->data, addr, cpu->R[Rd_num]); - cpu->mem_if->write32(cpu->mem_if->data, addr + 4, cpu->R[Rd_num + 1]); + WRITE32(cpu->mem_if->data, addr, cpu->R[Rd_num]); + WRITE32(cpu->mem_if->data, addr + 4, cpu->R[Rd_num + 1]); } else { - cpu->R[Rd_num] = cpu->mem_if->read32(cpu->mem_if->data, addr); - cpu->R[Rd_num + 1] = cpu->mem_if->read32(cpu->mem_if->data, addr + 4); + cpu->R[Rd_num] = READ32(cpu->mem_if->data, addr); + cpu->R[Rd_num + 1] = READ32(cpu->mem_if->data, addr + 4); } } @@ -7694,12 +7706,12 @@ OP_LDRD_STRD_OFFSET_PRE_INDEX( armcpu_t *cpu) { if ( !(Rd_num & 0x1)) { /* Store/Load */ if ( BIT5(i)) { - cpu->mem_if->write32(cpu->mem_if->data, addr, cpu->R[Rd_num]); - cpu->mem_if->write32(cpu->mem_if->data, addr + 4, cpu->R[Rd_num + 1]); + WRITE32(cpu->mem_if->data, addr, cpu->R[Rd_num]); + WRITE32(cpu->mem_if->data, addr + 4, cpu->R[Rd_num + 1]); } else { - cpu->R[Rd_num] = cpu->mem_if->read32(cpu->mem_if->data, addr); - cpu->R[Rd_num + 1] = cpu->mem_if->read32(cpu->mem_if->data, addr + 4); + cpu->R[Rd_num] = READ32(cpu->mem_if->data, addr); + cpu->R[Rd_num + 1] = READ32(cpu->mem_if->data, addr + 4); } } diff --git a/desmume/src/arm_instructions.h b/desmume/src/arm_instructions.h index cc56e40c6..350680aaf 100644 --- a/desmume/src/arm_instructions.h +++ b/desmume/src/arm_instructions.h @@ -25,7 +25,7 @@ #include "types.h" #include "armcpu.h" -extern u32 (*FASTCALL arm_instructions_set[4096])(armcpu_t * cpu); +extern u32 (FASTCALL* arm_instructions_set[4096])(armcpu_t * cpu); #endif diff --git a/desmume/src/armcpu.c b/desmume/src/armcpu.c index e27af88fb..179593d2d 100644 --- a/desmume/src/armcpu.c +++ b/desmume/src/armcpu.c @@ -29,8 +29,6 @@ armcpu_t NDS_ARM7; armcpu_t NDS_ARM9; -#define STALLED_CYCLE_COUNT 10 - #define SWAP(a, b, c) do \ { \ c=a; \ @@ -39,6 +37,10 @@ armcpu_t NDS_ARM9; } \ while(0) +#ifdef GDB_STUB + +#define STALLED_CYCLE_COUNT 10 + static void stall_cpu( void *instance) { armcpu_t *armcpu = (armcpu_t *)instance; @@ -46,7 +48,6 @@ stall_cpu( void *instance) { armcpu->stalled = 1; } - static void unstall_cpu( void *instance) { armcpu_t *armcpu = (armcpu_t *)instance; @@ -70,6 +71,7 @@ remove_post_exec_fn( void *instance) { armcpu->post_ex_fn = NULL; } +#endif static u32 read_cpu_reg( void *instance, u32 reg_num) { @@ -105,34 +107,41 @@ set_cpu_reg( void *instance, u32 reg_num, u32 value) { } } - +#ifdef GDB_STUB int armcpu_new( armcpu_t *armcpu, u32 id, struct armcpu_memory_iface *mem_if, struct armcpu_ctrl_iface **ctrl_iface_ret) +#else +int armcpu_new( armcpu_t *armcpu, u32 id) +#endif { - armcpu->proc_ID = id; - - if(id==0) armcpu->swi_tab = ARM9_swi_tab; - else armcpu->swi_tab = ARM7_swi_tab; - armcpu->mem_if = mem_if; - /* populate the control interface */ - armcpu->ctrl_iface.stall = stall_cpu; - armcpu->ctrl_iface.unstall = unstall_cpu; - armcpu->ctrl_iface.read_reg = read_cpu_reg; - armcpu->ctrl_iface.set_reg = set_cpu_reg; - armcpu->ctrl_iface.install_post_ex_fn = install_post_exec_fn; - armcpu->ctrl_iface.remove_post_ex_fn = remove_post_exec_fn; - armcpu->ctrl_iface.data = armcpu; + if(id==0) + armcpu->swi_tab = ARM9_swi_tab; + else + armcpu->swi_tab = ARM7_swi_tab; + +#ifdef GDB_STUB + armcpu->mem_if = mem_if; + + /* populate the control interface */ + armcpu->ctrl_iface.stall = stall_cpu; + armcpu->ctrl_iface.unstall = unstall_cpu; + armcpu->ctrl_iface.read_reg = read_cpu_reg; + armcpu->ctrl_iface.set_reg = set_cpu_reg; + armcpu->ctrl_iface.install_post_ex_fn = install_post_exec_fn; + armcpu->ctrl_iface.remove_post_ex_fn = remove_post_exec_fn; + armcpu->ctrl_iface.data = armcpu; + + *ctrl_iface_ret = &armcpu->ctrl_iface; + + armcpu->stalled = 0; + armcpu->post_ex_fn = NULL; +#endif - *ctrl_iface_ret = &armcpu->ctrl_iface; - - armcpu->stalled = 0; - armcpu->post_ex_fn = NULL; - armcpu_init(armcpu, 0); - + return 0; } @@ -144,7 +153,10 @@ void armcpu_init(armcpu_t *armcpu, u32 adr) armcpu->intVector = 0xFFFF0000 * (armcpu->proc_ID==0); armcpu->waitIRQ = FALSE; armcpu->wirq = FALSE; - armcpu->irq_flag = 0; + +#ifdef GDB_STUB + armcpu->irq_flag = 0; +#endif if(armcpu->coproc[15]) free(armcpu->coproc[15]); @@ -164,12 +176,21 @@ void armcpu_init(armcpu_t *armcpu, u32 adr) armcpu->R8_fiq = armcpu->R9_fiq = armcpu->R10_fiq = armcpu->R11_fiq = armcpu->R12_fiq = armcpu->R13_fiq = armcpu->R14_fiq = 0; armcpu->SPSR_svc.val = armcpu->SPSR_abt.val = armcpu->SPSR_und.val = armcpu->SPSR_irq.val = armcpu->SPSR_fiq.val = 0; - armcpu->instruct_adr = adr; - armcpu->next_instruction = adr; + +#ifdef GDB_STUB + armcpu->instruct_adr = adr; armcpu->R[15] = adr + 8; +#else + armcpu->R[15] = adr; +#endif + + armcpu->next_instruction = adr; + armcpu->coproc[15] = (armcp_t*)armcp15_new(armcpu); - //armcpu_prefetch(armcpu); +#ifndef GDB_STUB + armcpu_prefetch(armcpu); +#endif } u32 armcpu_switchMode(armcpu_t *armcpu, u8 mode) @@ -282,31 +303,51 @@ u32 armcpu_switchMode(armcpu_t *armcpu, u8 mode) static u32 armcpu_prefetch(armcpu_t *armcpu) { - u32 temp_instruction; + u32 temp_instruction; if(armcpu->CPSR.bits.T == 0) { - temp_instruction = - armcpu->mem_if->prefetch32( armcpu->mem_if->data, - armcpu->next_instruction); +#ifdef GDB_STUB + temp_instruction = + armcpu->mem_if->prefetch32( armcpu->mem_if->data, + armcpu->next_instruction); - if ( !armcpu->stalled) { - armcpu->instruction = temp_instruction; - armcpu->instruct_adr = armcpu->next_instruction; - armcpu->next_instruction += 4; - armcpu->R[15] = armcpu->next_instruction + 4; - } - return MMU.MMU_WAIT32[armcpu->proc_ID][(armcpu->instruct_adr>>24)&0xF]; + if ( !armcpu->stalled) { + armcpu->instruction = temp_instruction; + armcpu->instruct_adr = armcpu->next_instruction; + armcpu->next_instruction += 4; + armcpu->R[15] = armcpu->next_instruction + 4; + } +#else + armcpu->instruction = MMU_read32_acl(armcpu->proc_ID, armcpu->next_instruction,CP15_ACCESS_EXECUTE); + + armcpu->instruct_adr = armcpu->next_instruction; + armcpu->next_instruction += 4; + armcpu->R[15] = armcpu->next_instruction + 4; +#endif + + return MMU.MMU_WAIT32[armcpu->proc_ID][(armcpu->instruct_adr>>24)&0xF]; } + +#ifdef GDB_STUB temp_instruction = armcpu->mem_if->prefetch16( armcpu->mem_if->data, armcpu->next_instruction); - if ( !armcpu->stalled) { - armcpu->instruction = temp_instruction; - armcpu->instruct_adr = armcpu->next_instruction; - armcpu->next_instruction = armcpu->next_instruction + 2; - armcpu->R[15] = armcpu->next_instruction + 2; - } + + if ( !armcpu->stalled) { + armcpu->instruction = temp_instruction; + armcpu->instruct_adr = armcpu->next_instruction; + armcpu->next_instruction = armcpu->next_instruction + 2; + armcpu->R[15] = armcpu->next_instruction + 2; + } +#else + armcpu->instruction = MMU_read16_acl(armcpu->proc_ID, armcpu->next_instruction,CP15_ACCESS_EXECUTE); + + armcpu->instruct_adr = armcpu->next_instruction; + armcpu->next_instruction += 2; + armcpu->R[15] = armcpu->next_instruction + 2; +#endif + return MMU.MMU_WAIT16[armcpu->proc_ID][(armcpu->instruct_adr>>24)&0xF]; } @@ -327,7 +368,7 @@ static BOOL FASTCALL test_GT(Status_Reg CPSR) { return (!CPSR.bits.Z) && (CPSR.b static BOOL FASTCALL test_LE(Status_Reg CPSR) { return ( CPSR.bits.Z) || (CPSR.bits.N!=CPSR.bits.V); } static BOOL FASTCALL test_AL(Status_Reg CPSR) { return 1; } -static BOOL (*FASTCALL test_conditions[])(Status_Reg CPSR)= { +static BOOL (FASTCALL* test_conditions[])(Status_Reg CPSR)= { test_EQ , test_NE , test_CS , test_CC , test_MI , test_PL , @@ -341,23 +382,38 @@ static BOOL (*FASTCALL test_conditions[])(Status_Reg CPSR)= { (cond<15&&test_conditions[cond](CPSR)) -static BOOL armcpu_irqExeption(armcpu_t *armcpu) +BOOL armcpu_irqExeption(armcpu_t *armcpu) { - Status_Reg tmp; + Status_Reg tmp; + if(armcpu->CPSR.bits.I) return FALSE; + +#ifdef GDB_STUB armcpu->irq_flag = 0; - tmp = armcpu->CPSR; +#endif + + tmp = armcpu->CPSR; armcpu_switchMode(armcpu, IRQ); + +#ifdef GDB_STUB armcpu->R[14] = armcpu->next_instruction + 4; +#else + armcpu->R[14] = armcpu->instruct_adr + 4; +#endif armcpu->SPSR = tmp; armcpu->CPSR.bits.T = 0; armcpu->CPSR.bits.I = 1; armcpu->next_instruction = armcpu->intVector + 0x18; - //armcpu->R[15] = armcpu->next_instruction + 8; armcpu->waitIRQ = 0; + +#ifndef GDB_STUB + armcpu->R[15] = armcpu->next_instruction + 8; + armcpu_prefetch(armcpu); +#endif + return TRUE; } - +/* static BOOL armcpu_prefetchExeption(armcpu_t *armcpu) { Status_Reg tmp; @@ -373,20 +429,56 @@ static BOOL armcpu_prefetchExeption(armcpu_t *armcpu) armcpu->waitIRQ = 0; return TRUE; } +*/ + +static BOOL armcpu_prefetchExeption(armcpu_t *armcpu) +{ + Status_Reg tmp; + if(armcpu->CPSR.bits.I) return FALSE; + tmp = armcpu->CPSR; + armcpu_switchMode(armcpu, ABT); + +#ifdef GDB_STUB + armcpu->R[14] = armcpu->next_instruction + 4; +#else + armcpu->R[14] = armcpu->instruct_adr + 4; +#endif + + armcpu->SPSR = tmp; + armcpu->CPSR.bits.T = 0; + armcpu->CPSR.bits.I = 1; + armcpu->next_instruction = armcpu->intVector + 0xC; + armcpu->waitIRQ = 0; + +#ifdef GDB_STUB + armcpu->R[15] = armcpu->next_instruction + 8; +#else + armcpu->R[15] = armcpu->next_instruction; + armcpu_prefetch(armcpu); +#endif + + return TRUE; +} BOOL armcpu_flagIrq( armcpu_t *armcpu) { if(armcpu->CPSR.bits.I) return FALSE; armcpu->waitIRQ = 0; + +#ifdef GDB_STUB armcpu->irq_flag = 1; +#endif + return TRUE; } u32 armcpu_exec(armcpu_t *armcpu) { - u32 c; + u32 c = 1; + +#ifdef GDB_STUB if ( armcpu->stalled) return STALLED_CYCLE_COUNT; @@ -400,6 +492,7 @@ u32 armcpu_exec(armcpu_t *armcpu) if ( armcpu->stalled) { return c; } +#endif if(armcpu->CPSR.bits.T == 0) { @@ -407,22 +500,28 @@ u32 armcpu_exec(armcpu_t *armcpu) { c += arm_instructions_set[INSTRUCTION_INDEX(armcpu->instruction)](armcpu); } - - if ( armcpu->post_ex_fn != NULL) { - /* call the external post execute function */ - armcpu->post_ex_fn( armcpu->post_ex_fn_data, - armcpu->instruct_adr, 0); - } - +#ifdef GDB_STUB + if ( armcpu->post_ex_fn != NULL) { + /* call the external post execute function */ + armcpu->post_ex_fn( armcpu->post_ex_fn_data, + armcpu->instruct_adr, 0); + } +#else + c += armcpu_prefetch(armcpu); +#endif return c; } + c += thumb_instructions_set[armcpu->instruction>>6](armcpu); - if ( armcpu->post_ex_fn != NULL) { - /* call the external post execute function */ - armcpu->post_ex_fn( armcpu->post_ex_fn_data, armcpu->instruct_adr, 1); - } - +#ifdef GDB_STUB + if ( armcpu->post_ex_fn != NULL) { + /* call the external post execute function */ + armcpu->post_ex_fn( armcpu->post_ex_fn_data, armcpu->instruct_adr, 1); + } +#else + c += armcpu_prefetch(armcpu); +#endif return c; } diff --git a/desmume/src/armcpu.h b/desmume/src/armcpu.h index c8cd32fc1..d7c5ba392 100644 --- a/desmume/src/armcpu.h +++ b/desmume/src/armcpu.h @@ -195,6 +195,7 @@ typedef struct armcpu_t u32 (* *swi_tab)(struct armcpu_t * cpu); +#ifdef GDB_STUB /** there is a pending irq for the cpu */ int irq_flag; @@ -204,6 +205,7 @@ typedef struct armcpu_t /** data for the post executed function */ void *post_ex_fn_data; + /** flag indicating if the processor is stalled */ int stalled; @@ -212,14 +214,18 @@ typedef struct armcpu_t /** the ctrl interface */ struct armcpu_ctrl_iface ctrl_iface; +#endif } armcpu_t; - +#ifdef GDB_STUB int armcpu_new( armcpu_t *armcpu, u32 id, struct armcpu_memory_iface *mem_if, struct armcpu_ctrl_iface **ctrl_iface_ret); +#else +int armcpu_new( armcpu_t *armcpu, u32 id); +#endif void armcpu_init(armcpu_t *armcpu, u32 adr); u32 armcpu_switchMode(armcpu_t *armcpu, u8 mode); -//u32 armcpu_prefetch(armcpu_t *armcpu); +u32 armcpu_prefetch(armcpu_t *armcpu); u32 armcpu_exec(armcpu_t *armcpu); //BOOL armcpu_irqExeption(armcpu_t *armcpu); //BOOL armcpu_prefetchExeption(armcpu_t *armcpu); diff --git a/desmume/src/bios.c b/desmume/src/bios.c index 4a99e0ec6..871140438 100644 --- a/desmume/src/bios.c +++ b/desmume/src/bios.c @@ -219,7 +219,7 @@ u32 intrWaitARM(armcpu_t * cpu) } else { intrFlagAdr = (((armcp15_t *)(cpu->coproc[15]))->DTCMRegion&0xFFFFF000)+0x3FF8; } - intr = MMU_readWord(cpu->proc_ID, intrFlagAdr); + intr = MMU_read32(cpu->proc_ID, intrFlagAdr); intrFlag = cpu->R[1] & intr; if(intrFlag) @@ -227,7 +227,7 @@ u32 intrWaitARM(armcpu_t * cpu) // si une(ou plusieurs) des interruptions que l'on attend s'est(se sont) produite(s) // on efface son(les) occurence(s). intr ^= intrFlag; - MMU_writeWord(cpu->proc_ID, intrFlagAdr, intr); + MMU_write32(cpu->proc_ID, intrFlagAdr, intr); //cpu->switchMode(oldmode[cpu->proc_ID]); return 1; } @@ -253,7 +253,7 @@ u32 waitVBlankARM(armcpu_t * cpu) } else { intrFlagAdr = (((armcp15_t *)(cpu->coproc[15]))->DTCMRegion&0xFFFFF000)+0x3FF8; } - intr = MMU_readWord(cpu->proc_ID, intrFlagAdr); + intr = MMU_read32(cpu->proc_ID, intrFlagAdr); intrFlag = 1 & intr; if(intrFlag) @@ -261,7 +261,7 @@ u32 waitVBlankARM(armcpu_t * cpu) // si une(ou plusieurs) des interruptions que l'on attend s'est(se sont) produite(s) // on efface son(les) occurence(s). intr ^= intrFlag; - MMU_writeWord(cpu->proc_ID, intrFlagAdr, intr); + MMU_write32(cpu->proc_ID, intrFlagAdr, intr); //cpu->switchMode(oldmode[cpu->proc_ID]); return 1; } @@ -329,7 +329,7 @@ u32 copy(armcpu_t* cpu) cnt &= 0x1FFFFF; while(cnt) { - MMU_writeHWord(cpu->proc_ID, dst, MMU_readHWord(cpu->proc_ID, src)); + MMU_write16(cpu->proc_ID, dst, MMU_read16(cpu->proc_ID, src)); cnt--; dst+=2; src+=2; @@ -337,11 +337,11 @@ u32 copy(armcpu_t* cpu) break; case 1: { - u32 val = MMU_readHWord(cpu->proc_ID, src); + u32 val = MMU_read16(cpu->proc_ID, src); cnt &= 0x1FFFFF; while(cnt) { - MMU_writeHWord(cpu->proc_ID, dst, val); + MMU_write16(cpu->proc_ID, dst, val); cnt--; dst+=2; } @@ -358,7 +358,7 @@ u32 copy(armcpu_t* cpu) cnt &= 0x1FFFFF; while(cnt) { - MMU_writeWord(cpu->proc_ID, dst, MMU_readWord(cpu->proc_ID, src)); + MMU_write32(cpu->proc_ID, dst, MMU_read32(cpu->proc_ID, src)); cnt--; dst+=4; src+=4; @@ -366,11 +366,11 @@ u32 copy(armcpu_t* cpu) break; case 1: { - u32 val = MMU_readWord(cpu->proc_ID, src); + u32 val = MMU_read32(cpu->proc_ID, src); cnt &= 0x1FFFFF; while(cnt) { - MMU_writeWord(cpu->proc_ID, dst, val); + MMU_write32(cpu->proc_ID, dst, val); cnt--; dst+=4; } @@ -394,7 +394,7 @@ u32 fastCopy(armcpu_t* cpu) cnt &= 0x1FFFFF; while(cnt) { - MMU_writeWord(cpu->proc_ID, dst, MMU_readWord(cpu->proc_ID, src)); + MMU_write32(cpu->proc_ID, dst, MMU_read32(cpu->proc_ID, src)); cnt--; dst+=4; src+=4; @@ -402,11 +402,11 @@ u32 fastCopy(armcpu_t* cpu) break; case 1: { - u32 val = MMU_readWord(cpu->proc_ID, src); + u32 val = MMU_read32(cpu->proc_ID, src); cnt &= 0x1FFFFF; while(cnt) { - MMU_writeWord(cpu->proc_ID, dst, val); + MMU_write32(cpu->proc_ID, dst, val); cnt--; dst+=4; } @@ -425,7 +425,7 @@ u32 LZ77UnCompVram(armcpu_t* cpu) int len; u32 source = cpu->R[0]; u32 dest = cpu->R[1]; - u32 header = MMU_readWord(cpu->proc_ID, source); + u32 header = MMU_read32(cpu->proc_ID, source); source += 4; if(((source & 0xe000000) == 0) || @@ -439,7 +439,7 @@ u32 LZ77UnCompVram(armcpu_t* cpu) len = header >> 8; while(len > 0) { - u8 d = MMU_readByte(cpu->proc_ID, source++); + u8 d = MMU_read8(cpu->proc_ID, source++); if(d) { for(i1 = 0; i1 < 8; i1++) { @@ -447,18 +447,18 @@ u32 LZ77UnCompVram(armcpu_t* cpu) int length; int offset; u32 windowOffset; - u16 data = MMU_readByte(cpu->proc_ID, source++) << 8; - data |= MMU_readByte(cpu->proc_ID, source++); + u16 data = MMU_read8(cpu->proc_ID, source++) << 8; + data |= MMU_read8(cpu->proc_ID, source++); length = (data >> 12) + 3; offset = (data & 0x0FFF); windowOffset = dest + byteCount - offset - 1; for(i2 = 0; i2 < length; i2++) { - writeValue |= (MMU_readByte(cpu->proc_ID, windowOffset++) << byteShift); + writeValue |= (MMU_read8(cpu->proc_ID, windowOffset++) << byteShift); byteShift += 8; byteCount++; if(byteCount == 2) { - MMU_writeHWord(cpu->proc_ID, dest, writeValue); + MMU_write16(cpu->proc_ID, dest, writeValue); dest += 2; byteCount = 0; byteShift = 0; @@ -469,11 +469,11 @@ u32 LZ77UnCompVram(armcpu_t* cpu) return 0; } } else { - writeValue |= (MMU_readByte(cpu->proc_ID, source++) << byteShift); + writeValue |= (MMU_read8(cpu->proc_ID, source++) << byteShift); byteShift += 8; byteCount++; if(byteCount == 2) { - MMU_writeHWord(cpu->proc_ID, dest, writeValue); + MMU_write16(cpu->proc_ID, dest, writeValue); dest += 2; byteCount = 0; byteShift = 0; @@ -487,11 +487,11 @@ u32 LZ77UnCompVram(armcpu_t* cpu) } } else { for(i1 = 0; i1 < 8; i1++) { - writeValue |= (MMU_readByte(cpu->proc_ID, source++) << byteShift); + writeValue |= (MMU_read8(cpu->proc_ID, source++) << byteShift); byteShift += 8; byteCount++; if(byteCount == 2) { - MMU_writeHWord(cpu->proc_ID, dest, writeValue); + MMU_write16(cpu->proc_ID, dest, writeValue); dest += 2; byteShift = 0; byteCount = 0; @@ -513,7 +513,7 @@ u32 LZ77UnCompWram(armcpu_t* cpu) u32 source = cpu->R[0]; u32 dest = cpu->R[1]; - u32 header = MMU_readWord(cpu->proc_ID, source); + u32 header = MMU_read32(cpu->proc_ID, source); source += 4; if(((source & 0xe000000) == 0) || @@ -523,7 +523,7 @@ u32 LZ77UnCompWram(armcpu_t* cpu) len = header >> 8; while(len > 0) { - u8 d = MMU_readByte(cpu->proc_ID, source++); + u8 d = MMU_read8(cpu->proc_ID, source++); if(d) { for(i1 = 0; i1 < 8; i1++) { @@ -531,19 +531,19 @@ u32 LZ77UnCompWram(armcpu_t* cpu) int length; int offset; u32 windowOffset; - u16 data = MMU_readByte(cpu->proc_ID, source++) << 8; - data |= MMU_readByte(cpu->proc_ID, source++); + u16 data = MMU_read8(cpu->proc_ID, source++) << 8; + data |= MMU_read8(cpu->proc_ID, source++); length = (data >> 12) + 3; offset = (data & 0x0FFF); windowOffset = dest - offset - 1; for(i2 = 0; i2 < length; i2++) { - MMU_writeByte(cpu->proc_ID, dest++, MMU_readByte(cpu->proc_ID, windowOffset++)); + MMU_write8(cpu->proc_ID, dest++, MMU_read8(cpu->proc_ID, windowOffset++)); len--; if(len == 0) return 0; } } else { - MMU_writeByte(cpu->proc_ID, dest++, MMU_readByte(cpu->proc_ID, source++)); + MMU_write8(cpu->proc_ID, dest++, MMU_read8(cpu->proc_ID, source++)); len--; if(len == 0) return 0; @@ -552,7 +552,7 @@ u32 LZ77UnCompWram(armcpu_t* cpu) } } else { for(i1 = 0; i1 < 8; i1++) { - MMU_writeByte(cpu->proc_ID, dest++, MMU_readByte(cpu->proc_ID, source++)); + MMU_write8(cpu->proc_ID, dest++, MMU_read8(cpu->proc_ID, source++)); len--; if(len == 0) return 0; @@ -572,7 +572,7 @@ u32 RLUnCompVram(armcpu_t* cpu) u32 source = cpu->R[0]; u32 dest = cpu->R[1]; - u32 header = MMU_readWord(cpu->proc_ID, source); + u32 header = MMU_read32(cpu->proc_ID, source); source += 4; if(((source & 0xe000000) == 0) || @@ -585,10 +585,10 @@ u32 RLUnCompVram(armcpu_t* cpu) writeValue = 0; while(len > 0) { - u8 d = MMU_readByte(cpu->proc_ID, source++); + u8 d = MMU_read8(cpu->proc_ID, source++); int l = d & 0x7F; if(d & 0x80) { - u8 data = MMU_readByte(cpu->proc_ID, source++); + u8 data = MMU_read8(cpu->proc_ID, source++); l += 3; for(i = 0;i < l; i++) { writeValue |= (data << byteShift); @@ -596,7 +596,7 @@ u32 RLUnCompVram(armcpu_t* cpu) byteCount++; if(byteCount == 2) { - MMU_writeHWord(cpu->proc_ID, dest, writeValue); + MMU_write16(cpu->proc_ID, dest, writeValue); dest += 2; byteCount = 0; byteShift = 0; @@ -609,11 +609,11 @@ u32 RLUnCompVram(armcpu_t* cpu) } else { l++; for(i = 0; i < l; i++) { - writeValue |= (MMU_readByte(cpu->proc_ID, source++) << byteShift); + writeValue |= (MMU_read8(cpu->proc_ID, source++) << byteShift); byteShift += 8; byteCount++; if(byteCount == 2) { - MMU_writeHWord(cpu->proc_ID, dest, writeValue); + MMU_write16(cpu->proc_ID, dest, writeValue); dest += 2; byteCount = 0; byteShift = 0; @@ -635,7 +635,7 @@ u32 RLUnCompWram(armcpu_t* cpu) u32 source = cpu->R[0]; u32 dest = cpu->R[1]; - u32 header = MMU_readWord(cpu->proc_ID, source); + u32 header = MMU_read32(cpu->proc_ID, source); source += 4; if(((source & 0xe000000) == 0) || @@ -645,13 +645,13 @@ u32 RLUnCompWram(armcpu_t* cpu) len = header >> 8; while(len > 0) { - u8 d = MMU_readByte(cpu->proc_ID, source++); + u8 d = MMU_read8(cpu->proc_ID, source++); int l = d & 0x7F; if(d & 0x80) { - u8 data = MMU_readByte(cpu->proc_ID, source++); + u8 data = MMU_read8(cpu->proc_ID, source++); l += 3; for(i = 0;i < l; i++) { - MMU_writeByte(cpu->proc_ID, dest++, data); + MMU_write8(cpu->proc_ID, dest++, data); len--; if(len == 0) return 0; @@ -659,7 +659,7 @@ u32 RLUnCompWram(armcpu_t* cpu) } else { l++; for(i = 0; i < l; i++) { - MMU_writeByte(cpu->proc_ID, dest++, MMU_readByte(cpu->proc_ID, source++)); + MMU_write8(cpu->proc_ID, dest++, MMU_read8(cpu->proc_ID, source++)); len--; if(len == 0) return 0; @@ -680,14 +680,14 @@ u32 UnCompHuffman(armcpu_t* cpu) source = cpu->R[0]; dest = cpu->R[1]; - header = MMU_readByte(cpu->proc_ID, source); + header = MMU_read8(cpu->proc_ID, source); source += 4; if(((source & 0xe000000) == 0) || ((source + ((header >> 8) & 0x1fffff)) & 0xe000000) == 0) return 0; - treeSize = MMU_readByte(cpu->proc_ID, source++); + treeSize = MMU_read8(cpu->proc_ID, source++); treeStart = source; @@ -696,11 +696,11 @@ u32 UnCompHuffman(armcpu_t* cpu) len = header >> 8; mask = 0x80000000; - data = MMU_readByte(cpu->proc_ID, source); + data = MMU_read8(cpu->proc_ID, source); source += 4; pos = 0; - rootNode = MMU_readByte(cpu->proc_ID, treeStart); + rootNode = MMU_read8(cpu->proc_ID, treeStart); currentNode = rootNode; writeData = 0; byteShift = 0; @@ -719,12 +719,12 @@ u32 UnCompHuffman(armcpu_t* cpu) // right if(currentNode & 0x40) writeData = 1; - currentNode = MMU_readByte(cpu->proc_ID, treeStart+pos+1); + currentNode = MMU_read8(cpu->proc_ID, treeStart+pos+1); } else { // left if(currentNode & 0x80) writeData = 1; - currentNode = MMU_readByte(cpu->proc_ID, treeStart+pos); + currentNode = MMU_read8(cpu->proc_ID, treeStart+pos); } if(writeData) { @@ -739,7 +739,7 @@ u32 UnCompHuffman(armcpu_t* cpu) if(byteCount == 4) { byteCount = 0; byteShift = 0; - MMU_writeByte(cpu->proc_ID, dest, writeValue); + MMU_write8(cpu->proc_ID, dest, writeValue); writeValue = 0; dest += 4; len -= 4; @@ -748,7 +748,7 @@ u32 UnCompHuffman(armcpu_t* cpu) mask >>= 1; if(mask == 0) { mask = 0x80000000; - data = MMU_readByte(cpu->proc_ID, source); + data = MMU_read8(cpu->proc_ID, source); source += 4; } } @@ -766,12 +766,12 @@ u32 UnCompHuffman(armcpu_t* cpu) // right if(currentNode & 0x40) writeData = 1; - currentNode = MMU_readByte(cpu->proc_ID, treeStart+pos+1); + currentNode = MMU_read8(cpu->proc_ID, treeStart+pos+1); } else { // left if(currentNode & 0x80) writeData = 1; - currentNode = MMU_readByte(cpu->proc_ID, treeStart+pos); + currentNode = MMU_read8(cpu->proc_ID, treeStart+pos); } if(writeData) { @@ -792,7 +792,7 @@ u32 UnCompHuffman(armcpu_t* cpu) if(byteCount == 4) { byteCount = 0; byteShift = 0; - MMU_writeByte(cpu->proc_ID, dest, writeValue); + MMU_write8(cpu->proc_ID, dest, writeValue); dest += 4; writeValue = 0; len -= 4; @@ -805,7 +805,7 @@ u32 UnCompHuffman(armcpu_t* cpu) mask >>= 1; if(mask == 0) { mask = 0x80000000; - data = MMU_readByte(cpu->proc_ID, source); + data = MMU_read8(cpu->proc_ID, source); source += 4; } } @@ -823,15 +823,15 @@ u32 BitUnPack(armcpu_t* cpu) dest = cpu->R[1]; header = cpu->R[2]; - len = MMU_readHWord(cpu->proc_ID, header); + len = MMU_read16(cpu->proc_ID, header); // check address - bits = MMU_readByte(cpu->proc_ID, header+2); + bits = MMU_read8(cpu->proc_ID, header+2); revbits = 8 - bits; // u32 value = 0; - base = MMU_readByte(cpu->proc_ID, header+4); + base = MMU_read8(cpu->proc_ID, header+4); addBase = (base & 0x80000000) ? 1 : 0; base &= 0x7fffffff; - dataSize = MMU_readByte(cpu->proc_ID, header+3); + dataSize = MMU_read8(cpu->proc_ID, header+3); data = 0; bitwritecount = 0; @@ -840,7 +840,7 @@ u32 BitUnPack(armcpu_t* cpu) if(len < 0) break; mask = 0xff >> revbits; - b = MMU_readByte(cpu->proc_ID, source); + b = MMU_read8(cpu->proc_ID, source); source++; bitcount = 0; while(1) { @@ -854,7 +854,7 @@ u32 BitUnPack(armcpu_t* cpu) data |= temp << bitwritecount; bitwritecount += dataSize; if(bitwritecount >= 32) { - MMU_writeByte(cpu->proc_ID, dest, data); + MMU_write8(cpu->proc_ID, dest, data); dest += 4; data = 0; bitwritecount = 0; @@ -875,7 +875,7 @@ u32 Diff8bitUnFilterWram(armcpu_t* cpu) source = cpu->R[0]; dest = cpu->R[1]; - header = MMU_readByte(cpu->proc_ID, source); + header = MMU_read8(cpu->proc_ID, source); source += 4; if(((source & 0xe000000) == 0) || @@ -884,14 +884,14 @@ u32 Diff8bitUnFilterWram(armcpu_t* cpu) len = header >> 8; - data = MMU_readByte(cpu->proc_ID, source++); - MMU_writeByte(cpu->proc_ID, dest++, data); + data = MMU_read8(cpu->proc_ID, source++); + MMU_write8(cpu->proc_ID, dest++, data); len--; while(len > 0) { - diff = MMU_readByte(cpu->proc_ID, source++); + diff = MMU_read8(cpu->proc_ID, source++); data += diff; - MMU_writeByte(cpu->proc_ID, dest++, data); + MMU_write8(cpu->proc_ID, dest++, data); len--; } return 1; @@ -906,7 +906,7 @@ u32 Diff16bitUnFilter(armcpu_t* cpu) source = cpu->R[0]; dest = cpu->R[1]; - header = MMU_readByte(cpu->proc_ID, source); + header = MMU_read8(cpu->proc_ID, source); source += 4; if(((source & 0xe000000) == 0) || @@ -915,17 +915,17 @@ u32 Diff16bitUnFilter(armcpu_t* cpu) len = header >> 8; - data = MMU_readHWord(cpu->proc_ID, source); + data = MMU_read16(cpu->proc_ID, source); source += 2; - MMU_writeHWord(cpu->proc_ID, dest, data); + MMU_write16(cpu->proc_ID, dest, data); dest += 2; len -= 2; while(len >= 2) { - u16 diff = MMU_readHWord(cpu->proc_ID, source); + u16 diff = MMU_read16(cpu->proc_ID, source); source += 2; data += diff; - MMU_writeHWord(cpu->proc_ID, dest, data); + MMU_write16(cpu->proc_ID, dest, data); dest += 2; len -= 2; } @@ -940,7 +940,7 @@ u32 bios_sqrt(armcpu_t* cpu) u32 setHaltCR(armcpu_t* cpu) { - MMU_writeByte(cpu->proc_ID, 0x4000300+cpu->proc_ID, cpu->R[0]); + MMU_write8(cpu->proc_ID, 0x4000300+cpu->proc_ID, cpu->R[0]); return 1; } @@ -973,7 +973,7 @@ u32 getCRC16(armcpu_t* cpu) static u16 val[] = { 0xC0C1,0xC181,0xC301,0xC601,0xCC01,0xD801,0xF001,0xA001 }; for(i = 0; i < size; i++) { - crc = crc ^ MMU_readByte( cpu->proc_ID, datap + i); + crc = crc ^ MMU_read8( cpu->proc_ID, datap + i); for(j = 0; j < 8; j++) { int do_bit = 0; diff --git a/desmume/src/thumb_instructions.c b/desmume/src/thumb_instructions.c index 43b56e8f3..8a344bcc7 100644 --- a/desmume/src/thumb_instructions.c +++ b/desmume/src/thumb_instructions.c @@ -32,6 +32,23 @@ extern BOOL execute; +// Use this macros for reading/writing, so the GDB stub isn't broken +#ifdef GDB_STUB + #define READ32(a,b) cpu->mem_if->read32(a,b) + #define WRITE32(a,b,c) cpu->mem_if->write32(a,b,c) + #define READ16(a,b) cpu->mem_if->read16(a,b) + #define WRITE16(a,b,c) cpu->mem_if->write16(a,b,c) + #define READ8(a,b) cpu->mem_if->read8(a,b) + #define WRITE8(a,b,c) cpu->mem_if->write8(a,b,c) +#else + #define READ32(a,b) MMU_read32(cpu->proc_ID, b) + #define WRITE32(a,b,c) MMU_write32(cpu->proc_ID,b,c) + #define READ16(a,b) MMU_read16(cpu->proc_ID, b) + #define WRITE16(a,b,c) MMU_write16(cpu->proc_ID,b,c) + #define READ8(a,b) MMU_read8(cpu->proc_ID, b) + #define WRITE8(a,b,c) MMU_write8(cpu->proc_ID,b,c) +#endif + static u32 FASTCALL OP_UND_THUMB(armcpu_t *cpu) { execute = FALSE; @@ -538,7 +555,7 @@ static u32 FASTCALL OP_LDR_PCREL(armcpu_t *cpu) { u32 adr = (cpu->R[15]&0xFFFFFFFC) + ((cpu->instruction&0xFF)<<2); - cpu->R[REG_NUM(cpu->instruction, 8)] = cpu->mem_if->read32(cpu->mem_if->data, adr); + cpu->R[REG_NUM(cpu->instruction, 8)] = READ32(cpu->mem_if->data, adr); return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -547,7 +564,7 @@ static u32 FASTCALL OP_STR_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 6)] + cpu->R[REG_NUM(i, 3)]; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 0)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 0)]); return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -556,7 +573,7 @@ static u32 FASTCALL OP_STRH_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; - cpu->mem_if->write16(cpu->mem_if->data, adr, ((u16)cpu->R[REG_NUM(i, 0)])); + WRITE16(cpu->mem_if->data, adr, ((u16)cpu->R[REG_NUM(i, 0)])); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -565,7 +582,7 @@ static u32 FASTCALL OP_STRB_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; - cpu->mem_if->write8(cpu->mem_if->data, adr, ((u8)cpu->R[REG_NUM(i, 0)])); + WRITE8(cpu->mem_if->data, adr, ((u8)cpu->R[REG_NUM(i, 0)])); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -574,7 +591,7 @@ static u32 FASTCALL OP_LDRSB_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; - cpu->R[REG_NUM(i, 0)] = (s32)((s8)cpu->mem_if->read8(cpu->mem_if->data, adr)); + cpu->R[REG_NUM(i, 0)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -583,7 +600,7 @@ static u32 FASTCALL OP_LDR_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = (cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]); - u32 tempValue = cpu->mem_if->read32(cpu->mem_if->data, adr&0xFFFFFFFC); + u32 tempValue = READ32(cpu->mem_if->data, adr&0xFFFFFFFC); adr = (adr&3)*8; tempValue = (tempValue>>adr) | (tempValue<<(32-adr)); @@ -596,7 +613,7 @@ static u32 FASTCALL OP_LDRH_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; - cpu->R[REG_NUM(i, 0)] = (u32)cpu->mem_if->read16(cpu->mem_if->data, adr); + cpu->R[REG_NUM(i, 0)] = (u32)READ16(cpu->mem_if->data, adr); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -605,7 +622,7 @@ static u32 FASTCALL OP_LDRB_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; - cpu->R[REG_NUM(i, 0)] = (u32)cpu->mem_if->read8(cpu->mem_if->data, adr); + cpu->R[REG_NUM(i, 0)] = (u32)READ8(cpu->mem_if->data, adr); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -614,7 +631,7 @@ static u32 FASTCALL OP_LDRSH_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; - cpu->R[REG_NUM(i, 0)] = (s32)((s16)cpu->mem_if->read16(cpu->mem_if->data, adr)); + cpu->R[REG_NUM(i, 0)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -623,7 +640,7 @@ static u32 FASTCALL OP_STR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C); - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 0)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 0)]); return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -632,7 +649,7 @@ static u32 FASTCALL OP_LDR_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C); - u32 tempValue = cpu->mem_if->read32(cpu->mem_if->data, adr&0xFFFFFFFC); + u32 tempValue = READ32(cpu->mem_if->data, adr&0xFFFFFFFC); adr = (adr&3)*8; tempValue = (tempValue>>adr) | (tempValue<<(32-adr)); cpu->R[REG_NUM(i, 0)] = tempValue; @@ -644,7 +661,7 @@ static u32 FASTCALL OP_STRB_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F); - cpu->mem_if->write8(cpu->mem_if->data, adr, (u8)cpu->R[REG_NUM(i, 0)]); + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_NUM(i, 0)]); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -653,7 +670,7 @@ static u32 FASTCALL OP_LDRB_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F); - cpu->R[REG_NUM(i, 0)] = cpu->mem_if->read8(cpu->mem_if->data, adr); + cpu->R[REG_NUM(i, 0)] = READ8(cpu->mem_if->data, adr); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -662,7 +679,7 @@ static u32 FASTCALL OP_STRH_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E); - cpu->mem_if->write16(cpu->mem_if->data, adr, (u16)cpu->R[REG_NUM(i, 0)]); + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_NUM(i, 0)]); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -671,7 +688,7 @@ static u32 FASTCALL OP_LDRH_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E); - cpu->R[REG_NUM(i, 0)] = cpu->mem_if->read16(cpu->mem_if->data, adr); + cpu->R[REG_NUM(i, 0)] = READ16(cpu->mem_if->data, adr); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -680,7 +697,7 @@ static u32 FASTCALL OP_STR_SPREL(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[13] + ((i&0xFF)<<2); - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 8)]); + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 8)]); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -689,7 +706,7 @@ static u32 FASTCALL OP_LDR_SPREL(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[13] + ((i&0xFF)<<2); - cpu->R[REG_NUM(i, 8)] = cpu->mem_if->read32(cpu->mem_if->data, adr); + cpu->R[REG_NUM(i, 8)] = READ32(cpu->mem_if->data, adr); return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -733,7 +750,7 @@ static u32 FASTCALL OP_PUSH(armcpu_t *cpu) for(j = 0; j<8; ++j) if(BIT_N(i, 7-j)) { - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[7-j]); + WRITE32(cpu->mem_if->data, adr, cpu->R[7-j]); c += MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; adr -= 4; } @@ -748,14 +765,14 @@ static u32 FASTCALL OP_PUSH_LR(armcpu_t *cpu) u32 adr = cpu->R[13] - 4; u32 c = 0, j; - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[14]); + WRITE32(cpu->mem_if->data, adr, cpu->R[14]); c += MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; adr -= 4; for(j = 0; j<8; ++j) if(BIT_N(i, 7-j)) { - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[7-j]); + WRITE32(cpu->mem_if->data, adr, cpu->R[7-j]); c += MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; adr -= 4; } @@ -773,7 +790,7 @@ static u32 FASTCALL OP_POP(armcpu_t *cpu) for(j = 0; j<8; ++j) if(BIT_N(i, j)) { - cpu->R[j] = cpu->mem_if->read32(cpu->mem_if->data, adr); + cpu->R[j] = READ32(cpu->mem_if->data, adr); c += MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; adr += 4; } @@ -792,12 +809,12 @@ static u32 FASTCALL OP_POP_PC(armcpu_t *cpu) for(j = 0; j<8; ++j) if(BIT_N(i, j)) { - cpu->R[j] = cpu->mem_if->read32(cpu->mem_if->data, adr); + cpu->R[j] = READ32(cpu->mem_if->data, adr); c += MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; adr += 4; } - v = cpu->mem_if->read32(cpu->mem_if->data, adr); + v = READ32(cpu->mem_if->data, adr); c += MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; cpu->R[15] = v & 0xFFFFFFFE; cpu->next_instruction = v & 0xFFFFFFFE; @@ -823,7 +840,7 @@ static u32 FASTCALL OP_STMIA_THUMB(armcpu_t *cpu) for(j = 0; j<8; ++j) if(BIT_N(i, j)) { - cpu->mem_if->write32(cpu->mem_if->data, adr, cpu->R[j]); + WRITE32(cpu->mem_if->data, adr, cpu->R[j]); c += MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; adr += 4; } @@ -840,7 +857,7 @@ static u32 FASTCALL OP_LDMIA_THUMB(armcpu_t *cpu) for(j = 0; j<8; ++j) if(BIT_N(i, j)) { - cpu->R[j] = cpu->mem_if->read32(cpu->mem_if->data, adr); + cpu->R[j] = READ32(cpu->mem_if->data, adr); c += MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; adr += 4; } diff --git a/desmume/src/thumb_instructions.h b/desmume/src/thumb_instructions.h index 87a8c22b3..27088a6e3 100644 --- a/desmume/src/thumb_instructions.h +++ b/desmume/src/thumb_instructions.h @@ -24,7 +24,7 @@ #include "armcpu.h" -extern u32 (* FASTCALL thumb_instructions_set[1024])(armcpu_t * cpu); +extern u32 (FASTCALL* thumb_instructions_set[1024])(armcpu_t * cpu); #endif diff --git a/desmume/src/windows/disView.c b/desmume/src/windows/disView.c index ec9c9e548..2f9d465b4 100644 --- a/desmume/src/windows/disView.c +++ b/desmume/src/windows/disView.c @@ -91,7 +91,7 @@ LRESULT DesViewBox_OnPaint(CDesView * win, WPARAM wParam, LPARAM lParam) for(u32 i = 0; i < nbligne; ++i) { - u32 ins = MMU_readWord(win->cpu->proc_ID, adr); + u32 ins = MMU_read32(win->cpu->proc_ID, adr); des_arm_instructions_set[INDEX(ins)](adr, ins, txt); sprintf(text, "%04X:%04X %08X %s", (int)(adr>>16), (int)(adr&0xFFFF), (int)ins, txt); DrawText(mem_dc, text, -1, &rect, DT_TOP | DT_LEFT | DT_NOPREFIX); @@ -118,7 +118,7 @@ LRESULT DesViewBox_OnPaint(CDesView * win, WPARAM wParam, LPARAM lParam) for(u32 i = 0; i < nbligne; ++i) { - u32 ins = MMU_readHWord(win->cpu->proc_ID, adr); + u32 ins = MMU_read16(win->cpu->proc_ID, adr); des_thumb_instructions_set[ins>>6](adr, ins, txt); sprintf(text, "%04X:%04X %04X %s", (int)(adr>>16), (int)(adr&0xFFFF), (int)ins, txt); DrawText(mem_dc, text, -1, &rect, DT_TOP | DT_LEFT | DT_NOPREFIX); @@ -448,7 +448,7 @@ LRESULT DisViewBox_OnPaint(disview_struct *win, WPARAM wParam, LPARAM lParam) for(i = 0; i < nbligne; ++i) { - u32 ins = MMU_readWord(win->cpu->proc_ID, adr); + u32 ins = MMU_read32(win->cpu->proc_ID, adr); des_arm_instructions_set[INDEX(ins)](adr, ins, txt); sprintf(text, "%04X:%04X %08X %s", (int)(adr>>16), (int)(adr&0xFFFF), (int)ins, txt); DrawText(mem_dc, text, -1, &rect, DT_TOP | DT_LEFT | DT_NOPREFIX); @@ -482,7 +482,7 @@ LRESULT DisViewBox_OnPaint(disview_struct *win, WPARAM wParam, LPARAM lParam) for(i = 0; i < nbligne; ++i) { - u32 ins = MMU_readHWord(win->cpu->proc_ID, adr); + u32 ins = MMU_read16(win->cpu->proc_ID, adr); des_thumb_instructions_set[ins>>6](adr, ins, txt); sprintf(text, "%04X:%04X %04X %s", (int)(adr>>16), (int)(adr&0xFFFF), (int)ins, txt); DrawText(mem_dc, text, -1, &rect, DT_TOP | DT_LEFT | DT_NOPREFIX); diff --git a/desmume/src/windows/main.c b/desmume/src/windows/main.c index bc3f77864..134314893 100644 --- a/desmume/src/windows/main.c +++ b/desmume/src/windows/main.c @@ -590,14 +590,18 @@ int WINAPI WinMain (HINSTANCE hThisInstance, int nFunsterStil) { +#ifdef GDB_STUB gdbstub_handle_t arm9_gdb_stub; gdbstub_handle_t arm7_gdb_stub; struct armcpu_memory_iface *arm9_memio = &arm9_base_memory_iface; struct armcpu_memory_iface *arm7_memio = &arm7_base_memory_iface; struct armcpu_ctrl_iface *arm9_ctrl_iface; struct armcpu_ctrl_iface *arm7_ctrl_iface; +#endif + struct configured_features my_config; + MSG messages; /* Here messages to the application are saved */ char text[80]; cwindow_struct MainWindow; @@ -650,6 +654,7 @@ int WINAPI WinMain (HINSTANCE hThisInstance, LogStart(); #endif +#ifdef GDB_STUB if ( my_config.arm9_gdb_port != 0) { arm9_gdb_stub = createStub_gdb( my_config.arm9_gdb_port, &arm9_memio, &arm9_direct_memory_iface); @@ -670,22 +675,25 @@ int WINAPI WinMain (HINSTANCE hThisInstance, } } - NDS_Init( arm9_memio, &arm9_ctrl_iface, arm7_memio, &arm7_ctrl_iface); +#else + NDS_Init (); +#endif /* * Activate the GDB stubs * This has to come after the NDS_Init where the cpus are set up. */ - if ( my_config.arm9_gdb_port != 0) { - activateStub_gdb( arm9_gdb_stub, arm9_ctrl_iface); - } - if ( my_config.arm7_gdb_port != 0) { - activateStub_gdb( arm7_gdb_stub, arm7_ctrl_iface); - } - +#ifdef GDB_STUB + if ( my_config.arm9_gdb_port != 0) { + activateStub_gdb( arm9_gdb_stub, arm9_ctrl_iface); + } + if ( my_config.arm7_gdb_port != 0) { + activateStub_gdb( arm7_gdb_stub, arm7_ctrl_iface); + } +#endif GetPrivateProfileString("General", "Language", "0", text, 80, IniName); CheckLanguage(IDC_LANGENGLISH+atoi(text)); diff --git a/desmume/src/windows/memView.c b/desmume/src/windows/memView.c index 46741c5a5..cd159cf1e 100644 --- a/desmume/src/windows/memView.c +++ b/desmume/src/windows/memView.c @@ -97,7 +97,7 @@ LRESULT MemViewBox_OnPaint(CMemView * win, WPARAM wParam, LPARAM lParam) if(win->representation == 0) for(j=0; j<16; ++j) { - sprintf(text, "%02X", MMU_readByte(win->cpu, adr+j)); + sprintf(text, "%02X", MMU_read8(win->cpu, adr+j)); DrawText(mem_dc, text, -1, &r, DT_TOP | DT_LEFT | DT_NOPREFIX); r.left+=3*fontsize.cx; } @@ -105,14 +105,14 @@ LRESULT MemViewBox_OnPaint(CMemView * win, WPARAM wParam, LPARAM lParam) if(win->representation == 1) for(j=0; j<16; j+=2) { - sprintf(text, "%04X", MMU_readHWord(win->cpu, adr+j)); + sprintf(text, "%04X", MMU_read16(win->cpu, adr+j)); DrawText(mem_dc, text, -1, &r, DT_TOP | DT_LEFT | DT_NOPREFIX); r.left+=5*fontsize.cx; } else for(j=0; j<16; j+=4) { - sprintf(text, "%08X", (int)MMU_readWord(win->cpu, adr+j)); + sprintf(text, "%08X", (int)MMU_read32(win->cpu, adr+j)); DrawText(mem_dc, text, -1, &r, DT_TOP | DT_LEFT | DT_NOPREFIX); r.left+=9*fontsize.cx; } @@ -121,7 +121,7 @@ LRESULT MemViewBox_OnPaint(CMemView * win, WPARAM wParam, LPARAM lParam) for(j=0; j<16; ++j) { - u8 c = MMU_readByte(win->cpu, adr+j); + u8 c = MMU_read8(win->cpu, adr+j); if(c >= 32 && c <= 127) { text[j] = (char)c; } @@ -347,7 +347,7 @@ LRESULT MemViewBox_OnPaint(memview_struct * win, WPARAM wParam, LPARAM lParam) if(win->representation == 0) for(j=0; j<16; ++j) { - sprintf(text, "%02X", MMU_readByte(win->cpu, adr+j)); + sprintf(text, "%02X", MMU_read8(win->cpu, adr+j)); DrawText(mem_dc, text, -1, &r, DT_TOP | DT_LEFT | DT_NOPREFIX); r.left+=3*fontsize.cx; } @@ -355,14 +355,14 @@ LRESULT MemViewBox_OnPaint(memview_struct * win, WPARAM wParam, LPARAM lParam) if(win->representation == 1) for(j=0; j<16; j+=2) { - sprintf(text, "%04X", MMU_readHWord(win->cpu, adr+j)); + sprintf(text, "%04X", MMU_read16(win->cpu, adr+j)); DrawText(mem_dc, text, -1, &r, DT_TOP | DT_LEFT | DT_NOPREFIX); r.left+=5*fontsize.cx; } else for(j=0; j<16; j+=4) { - sprintf(text, "%08X", (int)MMU_readWord(win->cpu, adr+j)); + sprintf(text, "%08X", (int)MMU_read32(win->cpu, adr+j)); DrawText(mem_dc, text, -1, &r, DT_TOP | DT_LEFT | DT_NOPREFIX); r.left+=9*fontsize.cx; } @@ -371,7 +371,7 @@ LRESULT MemViewBox_OnPaint(memview_struct * win, WPARAM wParam, LPARAM lParam) for(j=0; j<16; ++j) { - u8 c = MMU_readByte(win->cpu, adr+j); + u8 c = MMU_read8(win->cpu, adr+j); if(c >= 32 && c <= 127) { text[j] = (char)c; }