diff --git a/trunk/desmume/src/GPU.c b/trunk/desmume/src/GPU.c index adec85514..2c428160d 100644 --- a/trunk/desmume/src/GPU.c +++ b/trunk/desmume/src/GPU.c @@ -27,8 +27,6 @@ #include "GPU.h" #include "debug.h" -#include "nds/video.h" - ARM9_struct ARM9Mem; extern BOOL click; @@ -150,12 +148,12 @@ void GPU_setVideoProp(GPU * gpu, u32 p) } gpu->nbBGActif = 0; - if(p & DISPLAY_SPR_1D_LAYOUT) + if(p & 0x10) { /* 1-d sprite mapping */ - gpu->sprBlock = 5 + DISPLAY_SPR_1D_SIZE_MASK(p); /* TODO: better comment (and understanding btw 8S) */ - if((gpu->core == GPU_SUB) && (DISPLAY_SPR_1D_SIZE_MASK(p) == 3)) + gpu->sprBlock = 5 + ((p>>20)&3); /* TODO: better comment (and understanding btw 8S) */ + if((gpu->core == GPU_SUB) && (((p>>20)&3) == 3)) { gpu->sprBlock = 7; } @@ -168,7 +166,7 @@ void GPU_setVideoProp(GPU * gpu, u32 p) gpu->spriteRender = sprite2D; } - if((p & DISPLAY_SPR_1D_BMP_SIZE_256) && (gpu->core == GPU_MAIN)) + if((p & 0x400000) && (gpu->core == GPU_MAIN)) { gpu->sprBMPBlock = 8; } @@ -182,7 +180,7 @@ void GPU_setVideoProp(GPU * gpu, u32 p) GPU_setBGProp(gpu, 1, T1ReadWord(ARM9Mem.ARM9_REG, (gpu->core * 0x800 + 5) << 1)); GPU_setBGProp(gpu, 0, T1ReadWord(ARM9Mem.ARM9_REG, (gpu->core * 0x800 + 4) << 1)); - if((p & DISPLAY_BG3_ACTIVE) && gpu->dispBG[3]) + if((p & 0x800) && gpu->dispBG[3]) { gpu->ordre[0] = 3; gpu->BGIndex[3] = 1; @@ -193,11 +191,11 @@ void GPU_setVideoProp(GPU * gpu, u32 p) gpu->BGIndex[3] = 0; } - if((p & DISPLAY_BG2_ACTIVE) && gpu->dispBG[2]) + if((p & 0x400) && gpu->dispBG[2]) { if(gpu->nbBGActif) { - if(BG_PRIORITY_MASK(gpu->BGProp[2]) > BG_PRIORITY_MASK(gpu->BGProp[3])) + if((gpu->BGProp[2] & 0x3) > (gpu->BGProp[3] & 0x3)) { gpu->ordre[0] = 2; gpu->BGIndex[2] = 1; @@ -224,7 +222,7 @@ void GPU_setVideoProp(GPU * gpu, u32 p) gpu->BGIndex[2] = 0; } - if((p & DISPLAY_BG1_ACTIVE) && gpu->dispBG[1]) + if((p & 0x200) && gpu->dispBG[1]) { if(gpu->nbBGActif == 0) { @@ -235,7 +233,7 @@ void GPU_setVideoProp(GPU * gpu, u32 p) { u8 i = 0; s8 j; - for(; (i < gpu->nbBGActif) && (BG_PRIORITY_MASK(gpu->BGProp[gpu->ordre[i]]) >= BG_PRIORITY_MASK(gpu->BGProp[1])); ++i); + for(; (i < gpu->nbBGActif) && ((gpu->BGProp[gpu->ordre[i]] & 0x3) >= (gpu->BGProp[1] & 0x3)); ++i); for(j = gpu->nbBGActif-1; j >= i; --j) { gpu->ordre[j+1] = gpu->ordre[j]; @@ -251,7 +249,7 @@ void GPU_setVideoProp(GPU * gpu, u32 p) gpu->BGIndex[1] = 0; } - if((p & DISPLAY_BG0_ACTIVE) && (!(p & ENABLE_3D)) && gpu->dispBG[0]) + if((p & 0x100) && (!(p & 0x8)) && gpu->dispBG[0]) { if(gpu->nbBGActif == 0) { @@ -262,7 +260,7 @@ void GPU_setVideoProp(GPU * gpu, u32 p) { u8 i = 0; s8 j; - for(; (i < gpu->nbBGActif) && (BG_PRIORITY_MASK(gpu->BGProp[gpu->ordre[i]]) >= BG_PRIORITY_MASK(gpu->BGProp[0])); ++i); + for(; (i < gpu->nbBGActif) && ((gpu->BGProp[gpu->ordre[i]] & 0x3) >= (gpu->BGProp[0] & 0x3)); ++i); for(j = gpu->nbBGActif-1; j >= i; --j) { gpu->ordre[j+1] = gpu->ordre[j]; @@ -299,7 +297,7 @@ void GPU_setBGProp(GPU * gpu, u16 num, u16 p) if((gpu->nbBGActif != 0) && (index != 0)) { index--; - if(BG_PRIORITY_MASK(gpu->BGProp[num]) < BG_PRIORITY_MASK(p)) + if((gpu->BGProp[num] & 0x3) < (p & 0x3)) { #ifdef DEBUG_TRI sprintf(logbuf, "INF NEW bg %d prio %d %d", num, p&3, index); @@ -311,7 +309,7 @@ void GPU_setBGProp(GPU * gpu, u16 num, u16 p) } #endif u8 i = 0; - for(; (i < index) && (((BG_PRIORITY_MASK(gpu->BGProp[gpu->ordre[i]]))>(BG_PRIORITY_MASK(p))) || (((BG_PRIORITY_MASK(gpu->BGProp[gpu->ordre[i]]))==(BG_PRIORITY_MASK(p)))&&(gpu->ordre[i]>num))); ++i); /* TODO: commenting and understanding */ + for(; (i < index) && ((((gpu->BGProp[gpu->ordre[i]] & 0x3))>((p & 0x3))) || ((((gpu->BGProp[gpu->ordre[i]] & 0x3))==((p & 0x3)))&&(gpu->ordre[i]>num))); ++i); /* TODO: commenting and understanding */ #ifdef DEBUG_TRI @@ -387,15 +385,15 @@ void GPU_setBGProp(GPU * gpu, u16 num, u16 p) if(gpu->core == GPU_SUB) { - gpu->BG_bmp_ram[num] = ((u8 *)ARM9Mem.ARM9_BBG) + BG_BMP_BASE_MASK(p) * 0x4000; - gpu->BG_tile_ram[num] = ((u8 *)ARM9Mem.ARM9_BBG) + BG_TILE_BASE_MASK(p) * 0x4000; - gpu->BG_map_ram[num] = ARM9Mem.ARM9_BBG + BG_MAP_BASE_MASK(p) * 0x800; + gpu->BG_bmp_ram[num] = ((u8 *)ARM9Mem.ARM9_BBG) + ((p>>8)&0x1F) * 0x4000; + gpu->BG_tile_ram[num] = ((u8 *)ARM9Mem.ARM9_BBG) + ((p>>2)&0xF) * 0x4000; + gpu->BG_map_ram[num] = ARM9Mem.ARM9_BBG + ((p>>8)&0x1F) * 0x800; } else { - gpu->BG_bmp_ram[num] = ((u8 *)ARM9Mem.ARM9_ABG) + BG_BMP_BASE_MASK(p) * 0x4000; - gpu->BG_tile_ram[num] = ((u8 *)ARM9Mem.ARM9_ABG) + BG_TILE_BASE_MASK(p) * 0x4000 + DISPLAY_TILE_BASE_MASK(gpu->prop) * 0x10000; - gpu->BG_map_ram[num] = ARM9Mem.ARM9_ABG + BG_MAP_BASE_MASK(p) * 0x800 + DISPLAY_MAP_BASE_MASK(gpu->prop) * 0x10000; + gpu->BG_bmp_ram[num] = ((u8 *)ARM9Mem.ARM9_ABG) + ((p>>8)&0x1F) * 0x4000; + gpu->BG_tile_ram[num] = ((u8 *)ARM9Mem.ARM9_ABG) + ((p>>2)&0xF) * 0x4000 + ((gpu->prop >> 24) & 0x7) * 0x10000; + gpu->BG_map_ram[num] = ARM9Mem.ARM9_ABG + ((p>>8)&0x1F) * 0x800 + ((gpu->prop >> 27) & 0x7) * 0x10000; } /*if(!(p&(1<<7))) @@ -406,12 +404,12 @@ void GPU_setBGProp(GPU * gpu, u16 num, u16 p) else*/ switch(num) { - case 0 : - gpu->BGExtPalSlot[num] = BG_PALETTE_SLOT_MASK(p) ? 2 : 0; + case 0 : + gpu->BGExtPalSlot[num] = (p & 0x2000) ? 2 : 0; break; case 1 : - gpu->BGExtPalSlot[num] = BG_PALETTE_SLOT_MASK(p) ? 3 : 1; + gpu->BGExtPalSlot[num] = (p & 0x2000) ? 3 : 1; break; default : @@ -425,9 +423,9 @@ void GPU_setBGProp(GPU * gpu, u16 num, u16 p) BGSize[num][1] = lcdSizeTab[p>>14][1]; return; }*/ - - gpu->BGSize[num][0] = sizeTab[mode2type[DISPLAY_MODE_MASK(gpu->prop)][num]][BG_SIZE_MASK(p)][0]; - gpu->BGSize[num][1] = sizeTab[mode2type[DISPLAY_MODE_MASK(gpu->prop)][num]][BG_SIZE_MASK(p)][1]; + + gpu->BGSize[num][0] = sizeTab[mode2type[gpu->prop & 0x7][num]][p >> 14][0]; + gpu->BGSize[num][1] = sizeTab[mode2type[gpu->prop & 0x7][num]][p >> 14][1]; } void GPU_remove(GPU * gpu, u8 num) @@ -563,7 +561,7 @@ INLINE void renderline_textBG(GPU * gpu, u8 num, u8 * DST, u16 X, u16 Y, u16 LG) if(tmp>31) { - switch(BG_SIZE_MASK(bgprop)) + switch(bgprop >> 14) { case 2 : map += 32 * 32 * 2; @@ -580,7 +578,7 @@ INLINE void renderline_textBG(GPU * gpu, u8 num, u8 * DST, u16 X, u16 Y, u16 LG) xoff = X; - if(!(bgprop & BG_256_COLOR)) + if(!(bgprop & 0x80)) { yoff = ((Y&7)<<2); pal = ARM9Mem.ARM9_VMEM + gpu->core * 0x400; @@ -599,19 +597,19 @@ INLINE void renderline_textBG(GPU * gpu, u8 num, u8 * DST, u16 X, u16 Y, u16 LG) mapinfovalue = T1ReadWord(mapinfo, 0); - line = (u8 * )tile + (MAP_ENTRY_TILEID_MASK(mapinfovalue) * 0x20) + (((mapinfovalue)& MAP_ENTRY_FLIP_Y ? (7*4)-yoff : yoff)); + line = (u8 * )tile + ((mapinfovalue&0x3FF) * 0x20) + (((mapinfovalue)& 0x800 ? (7*4)-yoff : yoff)); xfin = x + (8 - (xoff&7)); if (xfin > LG) xfin = LG; - if((mapinfovalue) & MAP_ENTRY_FLIP_X) + if((mapinfovalue) & 0x400) { line += 3 - ((xoff&7)>>1); for(; x < xfin; ) - { - if((*line)>>4) T2WriteWord(dst, 0, T1ReadWord(pal, (((*line)>>4) + MAP_ENTRY_PALETTE_MASK(mapinfovalue) * 0x10) << 1)); + { + if((*line)>>4) T2WriteWord(dst, 0, T1ReadWord(pal, (((*line)>>4) + ((mapinfovalue>>12)&0xF) * 0x10) << 1)); dst += 2; x++; xoff++; - if((*line)&0xF) T2WriteWord(dst, 0, T1ReadWord(pal, (((*line)&0xF) + MAP_ENTRY_PALETTE_MASK(mapinfovalue) * 0x10) << 1)); + if((*line)&0xF) T2WriteWord(dst, 0, T1ReadWord(pal, (((*line)&0xF) + ((mapinfovalue>>12)&0xF) * 0x10) << 1)); dst += 2; x++; xoff++; line--; } @@ -621,9 +619,9 @@ INLINE void renderline_textBG(GPU * gpu, u8 num, u8 * DST, u16 X, u16 Y, u16 LG) line += ((xoff&7)>>1); for(; x < xfin; ) { - if((*line)&0xF) T2WriteWord(dst, 0, T1ReadWord(pal, (((*line)&0xF) + MAP_ENTRY_PALETTE_MASK(mapinfovalue) * 0x10) << 1)); + if((*line)&0xF) T2WriteWord(dst, 0, T1ReadWord(pal, (((*line)&0xF) + ((mapinfovalue>>12)&0xF) * 0x10) << 1)); dst += 2; x++; xoff++; - if((*line)>>4) T2WriteWord(dst, 0, T1ReadWord(pal, (((*line)>>4) + MAP_ENTRY_PALETTE_MASK(mapinfovalue) * 0x10) << 1)); + if((*line)>>4) T2WriteWord(dst, 0, T1ReadWord(pal, (((*line)>>4) + ((mapinfovalue>>12)&0xF) * 0x10) << 1)); dst += 2; x++; xoff++; line++; } @@ -632,7 +630,7 @@ INLINE void renderline_textBG(GPU * gpu, u8 num, u8 * DST, u16 X, u16 Y, u16 LG) return; } - if(!(gpu->prop & DISPLAY_BG_EXT_PALETTE)) + if(!(gpu->prop & 0x40000000)) { yoff = ((Y&7)<<3); pal = ARM9Mem.ARM9_VMEM + gpu->core * 0x400; @@ -650,13 +648,13 @@ INLINE void renderline_textBG(GPU * gpu, u8 num, u8 * DST, u16 X, u16 Y, u16 LG) if(tmp > 31) mapinfo += 32*32*2; mapinfovalue = T1ReadWord(mapinfo, 0); - - line = (u8 * )tile + (MAP_ENTRY_TILEID_MASK(mapinfovalue)*0x40) + (((mapinfovalue)& MAP_ENTRY_FLIP_Y ? (7*8)-yoff : yoff)); + + line = (u8 * )tile + ((mapinfovalue&0x3FF)*0x40) + (((mapinfovalue)& 0x800 ? (7*8)-yoff : yoff)); xfin = x + (8 - (xoff&7)); if (xfin > LG) xfin = LG; - if((mapinfovalue)& MAP_ENTRY_FLIP_X) + if((mapinfovalue)& 0x400) { line += (7 - (xoff&7)); for(; x < xfin; ++x, ++xoff) @@ -700,12 +698,12 @@ INLINE void renderline_textBG(GPU * gpu, u8 num, u8 * DST, u16 X, u16 Y, u16 LG) mapinfovalue = T1ReadWord(mapinfo, 0); - line = (u8 * )tile + (MAP_ENTRY_TILEID_MASK(mapinfovalue)*0x40) + (((mapinfovalue)& MAP_ENTRY_FLIP_Y ? (7*8)-yoff : yoff)); + line = (u8 * )tile + ((mapinfovalue&0x3FF)*0x40) + (((mapinfovalue)& 0x800 ? (7*8)-yoff : yoff)); xfin = x + (8 - (xoff&7)); if (xfin > LG) xfin = LG; - if((mapinfovalue)& MAP_ENTRY_FLIP_X) + if((mapinfovalue)& 0x400) { line += (7 - (xoff&7)); for(; x < xfin; ++x, ++xoff) diff --git a/trunk/desmume/src/MMU.c b/trunk/desmume/src/MMU.c index 6f54a4766..9f68fa3ce 100644 --- a/trunk/desmume/src/MMU.c +++ b/trunk/desmume/src/MMU.c @@ -29,11 +29,7 @@ #include "NDSSystem.h" #include "cflash.h" -#include "nds/interrupts.h" -#include "nds/video.h" -#include "nds/system.h" -#include "nds/serial.h" -#include "nds/card.h" +#include "registers.h" #define ROM_MASK 3 @@ -554,7 +550,7 @@ u32 FASTCALL MMU_read32(u32 proc, u32 adr) LOG("point res\r\n"); return 0; - case CARD_DATA_RD: + case REG_GCDATAIN: { u32 val; @@ -570,15 +566,15 @@ u32 FASTCALL MMU_read32(u32 proc, u32 adr) return val; /* return data */ } else /* transfer is done */ - { - T1WriteLong(MMU.MMU_MEM[proc][(CARD_CR2 >> 20) & 0xff], CARD_CR2 & 0xfff, T1ReadLong(MMU.MMU_MEM[proc][(CARD_CR2 >> 20) & 0xff], CARD_CR2 & 0xfff) & ~(CARD_DATA_READY | CARD_ACTIVATE)); + { + T1WriteLong(MMU.MMU_MEM[proc][(REG_GCROMCTRL >> 20) & 0xff], REG_GCROMCTRL & 0xfff, T1ReadLong(MMU.MMU_MEM[proc][(REG_GCROMCTRL >> 20) & 0xff], REG_GCROMCTRL & 0xfff) & ~(0x00800000 | 0x80000000)); /* = 0x7f7fffff */ /* if needed, throw irq for the end of transfer */ - if(T1ReadWord(MMU.MMU_MEM[proc][(CARD_CR1 >> 20) & 0xff], CARD_CR1 & 0xfff) & CARD_CR1_IRQ) + if(T1ReadWord(MMU.MMU_MEM[proc][(REG_AUXSPICNT >> 20) & 0xff], REG_AUXSPICNT & 0xfff) & 0x4000) { - if(proc == ARMCPU_ARM7) NDS_makeARM7Int(IRQ_CARD); - else NDS_makeARM9Int(IRQ_CARD); + if(proc == ARMCPU_ARM7) NDS_makeARM7Int(19); + else NDS_makeARM9Int(19); } return val; @@ -625,17 +621,17 @@ void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val) { /* TODO: EEEK ! Controls for VRAMs A, B, C, D are missing ! */ /* TODO: Not all mappings of VRAMs are handled... (especially BG and OBJ modes) */ - case VRAM_E_CR : + case REG_VRAMCNTE : if(proc == ARMCPU_ARM9) { - if((val & 7) == VRAM_E_BG_EXT_PALETTE) + if((val & 7) == 5) { ARM9Mem.ExtPal[0][0] = ARM9Mem.ARM9_LCD + 0x80000; ARM9Mem.ExtPal[0][1] = ARM9Mem.ARM9_LCD + 0x82000; ARM9Mem.ExtPal[0][2] = ARM9Mem.ARM9_LCD + 0x84000; ARM9Mem.ExtPal[0][3] = ARM9Mem.ARM9_LCD + 0x86000; } - else if((val & 7) == VRAM_E_TEX_PALETTE) + else if((val & 7) == 3) { ARM9Mem.texPalSlot[0] = ARM9Mem.ARM9_LCD + 0x80000; ARM9Mem.texPalSlot[1] = ARM9Mem.ARM9_LCD + 0x82000; @@ -645,82 +641,82 @@ void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val) } break; - case VRAM_F_CR : + case REG_VRAMCNTF : if(proc == ARMCPU_ARM9) { switch(val & 0x1F) { - case VRAM_F_BG_EXT_PALETTE : + case 4 : ARM9Mem.ExtPal[0][0] = ARM9Mem.ARM9_LCD + 0x90000; ARM9Mem.ExtPal[0][1] = ARM9Mem.ARM9_LCD + 0x92000; break; - case VRAM_F_BG_EXT_PALETTE | VRAM_OFFSET(1) : + case 4 | (1 << 3) : ARM9Mem.ExtPal[0][2] = ARM9Mem.ARM9_LCD + 0x90000; ARM9Mem.ExtPal[0][3] = ARM9Mem.ARM9_LCD + 0x92000; break; - case VRAM_F_TEX_PALETTE : + case 3 : ARM9Mem.texPalSlot[0] = ARM9Mem.ARM9_LCD + 0x90000; break; - case VRAM_F_TEX_PALETTE | VRAM_OFFSET(1) : + case 3 | (1 << 3) : ARM9Mem.texPalSlot[1] = ARM9Mem.ARM9_LCD + 0x90000; break; - case VRAM_F_TEX_PALETTE | VRAM_OFFSET(2) : + case 3 | (2 << 3) : ARM9Mem.texPalSlot[2] = ARM9Mem.ARM9_LCD + 0x90000; break; - case VRAM_F_TEX_PALETTE | VRAM_OFFSET(3) : + case 3 | (3 << 3) : ARM9Mem.texPalSlot[3] = ARM9Mem.ARM9_LCD + 0x90000; break; - case VRAM_F_OBJ_EXT_PALETTE : - case VRAM_F_OBJ_EXT_PALETTE | VRAM_OFFSET(1) : - case VRAM_F_OBJ_EXT_PALETTE | VRAM_OFFSET(2) : - case VRAM_F_OBJ_EXT_PALETTE | VRAM_OFFSET(3) : + case 5 : + case 5 | (1 << 3) : + case 5 | (2 << 3) : + case 5 | (3 << 3) : ARM9Mem.ObjExtPal[0][0] = ARM9Mem.ARM9_LCD + 0x90000; ARM9Mem.ObjExtPal[0][1] = ARM9Mem.ARM9_LCD + 0x92000; break; } } break; - case VRAM_G_CR : + case REG_VRAMCNTG : if(proc == ARMCPU_ARM9) { switch(val & 0x1F) { - case VRAM_G_BG_EXT_PALETTE : + case 4 : ARM9Mem.ExtPal[0][0] = ARM9Mem.ARM9_LCD + 0x94000; ARM9Mem.ExtPal[0][1] = ARM9Mem.ARM9_LCD + 0x96000; break; - case VRAM_G_BG_EXT_PALETTE | VRAM_OFFSET(1) : + case 4 | (1 << 3) : ARM9Mem.ExtPal[0][2] = ARM9Mem.ARM9_LCD + 0x94000; ARM9Mem.ExtPal[0][3] = ARM9Mem.ARM9_LCD + 0x96000; break; - case VRAM_G_TEX_PALETTE : + case 3 : ARM9Mem.texPalSlot[0] = ARM9Mem.ARM9_LCD + 0x94000; break; - case VRAM_G_TEX_PALETTE | VRAM_OFFSET(1) : + case 3 | (1 << 3) : ARM9Mem.texPalSlot[1] = ARM9Mem.ARM9_LCD + 0x94000; break; - case VRAM_G_TEX_PALETTE | VRAM_OFFSET(2) : + case 3 | (2 << 3) : ARM9Mem.texPalSlot[2] = ARM9Mem.ARM9_LCD + 0x94000; break; - case VRAM_G_TEX_PALETTE | VRAM_OFFSET(3) : + case 3 | (3 << 3) : ARM9Mem.texPalSlot[3] = ARM9Mem.ARM9_LCD + 0x94000; break; - case VRAM_G_OBJ_EXT_PALETTE : - case VRAM_G_OBJ_EXT_PALETTE | VRAM_OFFSET(1) : - case VRAM_G_OBJ_EXT_PALETTE | VRAM_OFFSET(2) : - case VRAM_G_OBJ_EXT_PALETTE | VRAM_OFFSET(3) : + case 5 : + case 5 | (1 << 3) : + case 5 | (2 << 3) : + case 5 | (3 << 3) : ARM9Mem.ObjExtPal[0][0] = ARM9Mem.ARM9_LCD + 0x94000; ARM9Mem.ObjExtPal[0][1] = ARM9Mem.ARM9_LCD + 0x96000; break; @@ -728,10 +724,10 @@ void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val) } break; - case VRAM_H_CR : + case REG_VRAMCNTH : if(proc == ARMCPU_ARM9) { - if((val & 7) == VRAM_H_SUB_BG_EXT_PALETTE) + if((val & 7) == 2) { ARM9Mem.ExtPal[1][0] = ARM9Mem.ARM9_LCD + 0x98000; ARM9Mem.ExtPal[1][1] = ARM9Mem.ARM9_LCD + 0x9A000; @@ -741,10 +737,10 @@ void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val) } break; - case VRAM_I_CR : + case REG_VRAMCNTI : if(proc == ARMCPU_ARM9) { - if((val & 7) == VRAM_I_SUB_SPRITE_EXT_PALETTE) + if((val & 7) == 3) { ARM9Mem.ObjExtPal[1][0] = ARM9Mem.ARM9_LCD + 0xA0000; ARM9Mem.ObjExtPal[1][1] = ARM9Mem.ARM9_LCD + 0xA2000; @@ -833,7 +829,7 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val) return; #endif - case POWER_CR : + case REG_POWCNT1 : if(proc == ARMCPU_ARM9) { if(val & (1<<15)) @@ -853,21 +849,21 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val) T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x304, val); return; - case CARD_CR1: - T1WriteWord(MMU.MMU_MEM[proc][(CARD_CR1 >> 20) & 0xff], CARD_CR1 & 0xfff, val); + case REG_AUXSPICNT: + T1WriteWord(MMU.MMU_MEM[proc][(REG_AUXSPICNT >> 20) & 0xff], REG_AUXSPICNT & 0xfff, val); AUX_SPI_CNT = val; if (val == 0) mc_reset_com(&MMU.bupmem); /* reset backup memory device communication */ return; - case CARD_EEPDATA: + case REG_AUXSPIDATA: if(val!=0) { AUX_SPI_CMD = val & 0xFF; } - T1WriteWord(MMU.MMU_MEM[proc][(CARD_EEPDATA >> 20) & 0xff], CARD_EEPDATA & 0xfff, bm_transfer(&MMU.bupmem, val)); + T1WriteWord(MMU.MMU_MEM[proc][(REG_AUXSPIDATA >> 20) & 0xff], REG_AUXSPIDATA & 0xfff, bm_transfer(&MMU.bupmem, val)); return; case REG_SPICNT : @@ -895,13 +891,13 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val) spicnt = T1ReadWord(MMU.MMU_MEM[proc][(REG_SPICNT >> 20) & 0xff], REG_SPICNT & 0xfff); - switch(spicnt & 0x300) + switch((spicnt >> 8) & 0x3) { - case SPI_DEVICE_POWER : + case 0 : break; - case SPI_DEVICE_NVRAM : /* firmware memory device */ - if(SPI_BAUD_MASK(spicnt) != SPI_BAUD_4MHz) /* check SPI baudrate (must be 4mhz) */ + case 1 : /* firmware memory device */ + if(spicnt & 0x3 != 0) /* check SPI baudrate (must be 4mhz) */ { T1WriteWord(MMU.MMU_MEM[proc][(REG_SPIDATA >> 20) & 0xff], REG_SPIDATA & 0xfff, 0); break; @@ -909,7 +905,7 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val) T1WriteWord(MMU.MMU_MEM[proc][(REG_SPIDATA >> 20) & 0xff], REG_SPIDATA & 0xfff, fw_transfer(&MMU.fw, val)); return; - case SPI_DEVICE_TOUCH: + case 2 : switch(SPI_CMD & 0x70) { case 0x00 : @@ -943,7 +939,7 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val) val = 0; break; case 0x50 : - if(spicnt & SPI_CONTINUOUS) + if(spicnt & 0x800) { if(partie) { @@ -967,7 +963,7 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val) } break; - case 0x300 : + case 3 : /* NOTICE: Device 3 of SPI is reserved (unused and unusable) */ break; } @@ -978,186 +974,186 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val) /* NOTICE: Perhaps we have to use gbatek-like reg names instead of libnds-like ones ...*/ - case BG0_X0 : + case REG_DISPA_BG0HOFS : GPU_scrollX(MainScreen.gpu, 0, val); - return; - case BG1_X0 : + return; + case REG_DISPA_BG1HOFS : GPU_scrollX(MainScreen.gpu, 1, val); return; - case BG2_X0 : + case REG_DISPA_BG2HOFS : GPU_scrollX(MainScreen.gpu, 2, val); return; - case BG3_X0 : + case REG_DISPA_BG3HOFS : GPU_scrollX(MainScreen.gpu, 3, val); return; - case SUB_BG0_X0 : + case REG_DISPB_BG0HOFS : GPU_scrollX(SubScreen.gpu, 0, val); return; - case SUB_BG1_X0 : + case REG_DISPB_BG1HOFS : GPU_scrollX(SubScreen.gpu, 1, val); return; - case SUB_BG2_X0 : + case REG_DISPB_BG2HOFS : GPU_scrollX(SubScreen.gpu, 2, val); return; - case SUB_BG3_X0 : + case REG_DISPB_BG3HOFS : GPU_scrollX(SubScreen.gpu, 3, val); return; - case BG0_Y0 : + case REG_DISPA_BG0VOFS : GPU_scrollY(MainScreen.gpu, 0, val); return; - case BG1_Y0 : + case REG_DISPA_BG1VOFS : GPU_scrollY(MainScreen.gpu, 1, val); return; - case BG2_Y0 : + case REG_DISPA_BG2VOFS : GPU_scrollY(MainScreen.gpu, 2, val); return; - case BG3_Y0 : + case REG_DISPA_BG3VOFS : GPU_scrollY(MainScreen.gpu, 3, val); return; - case SUB_BG0_Y0 : + case REG_DISPB_BG0VOFS : GPU_scrollY(SubScreen.gpu, 0, val); return; - case SUB_BG1_Y0 : + case REG_DISPB_BG1VOFS : GPU_scrollY(SubScreen.gpu, 1, val); return; - case SUB_BG2_Y0 : + case REG_DISPB_BG2VOFS : GPU_scrollY(SubScreen.gpu, 2, val); return; - case SUB_BG3_Y0 : + case REG_DISPB_BG3VOFS : GPU_scrollY(SubScreen.gpu, 3, val); return; - case BG2_XDX : + case REG_DISPA_BG2PA : GPU_setPA(MainScreen.gpu, 2, val); return; - case BG2_XDY : + case REG_DISPA_BG2PB : GPU_setPB(MainScreen.gpu, 2, val); return; - case BG2_YDX : + case REG_DISPA_BG2PC : GPU_setPC(MainScreen.gpu, 2, val); return; - case BG2_YDY : + case REG_DISPA_BG2PD : GPU_setPD(MainScreen.gpu, 2, val); return; - case SUB_BG2_XDX : + case REG_DISPB_BG2PA : GPU_setPA(SubScreen.gpu, 2, val); return; - case SUB_BG2_XDY : + case REG_DISPB_BG2PB : GPU_setPB(SubScreen.gpu, 2, val); return; - case SUB_BG2_YDX : + case REG_DISPB_BG2PC : GPU_setPC(SubScreen.gpu, 2, val); return; - case SUB_BG2_YDY : + case REG_DISPB_BG2PD : GPU_setPD(SubScreen.gpu, 2, val); return; - case BG3_XDX : + case REG_DISPA_BG3PA : GPU_setPA(MainScreen.gpu, 3, val); return; - case BG3_XDY : + case REG_DISPA_BG3PB : GPU_setPB(MainScreen.gpu, 3, val); return; - case BG3_YDX : + case REG_DISPA_BG3PC : GPU_setPC(MainScreen.gpu, 3, val); return; - case BG3_YDY : + case REG_DISPA_BG3PD : GPU_setPD(MainScreen.gpu, 3, val); return; - case SUB_BG3_XDX : + case REG_DISPB_BG3PA : GPU_setPA(SubScreen.gpu, 3, val); return; - case SUB_BG3_XDY : + case REG_DISPB_BG3PB : GPU_setPB(SubScreen.gpu, 3, val); return; - case SUB_BG3_YDX : + case REG_DISPB_BG3PC : GPU_setPC(SubScreen.gpu, 3, val); return; - case SUB_BG3_YDY : + case REG_DISPB_BG3PD : GPU_setPD(SubScreen.gpu, 3, val); return; - case BG2_CX : + case REG_DISPA_BG2XL : GPU_setXL(MainScreen.gpu, 2, val); return; - case BG2_CX + 2 : + case REG_DISPA_BG2XH : GPU_setXH(MainScreen.gpu, 2, val); return; - case SUB_BG2_CX : + case REG_DISPB_BG2XL : GPU_setXL(SubScreen.gpu, 2, val); return; - case SUB_BG2_CX + 2 : + case REG_DISPB_BG2XH : GPU_setXH(SubScreen.gpu, 2, val); return; - case BG3_CX : + case REG_DISPA_BG3XL : GPU_setXL(MainScreen.gpu, 3, val); return; - case BG3_CX + 2 : + case REG_DISPA_BG3XH : GPU_setXH(MainScreen.gpu, 3, val); return; - case SUB_BG3_CX : + case REG_DISPB_BG3XL : GPU_setXL(SubScreen.gpu, 3, val); return; - case SUB_BG3_CX + 2 : + case REG_DISPB_BG3XH : GPU_setXH(SubScreen.gpu, 3, val); return; - case BG2_CY : + case REG_DISPA_BG2YL : GPU_setYL(MainScreen.gpu, 2, val); return; - case BG2_CY + 2 : + case REG_DISPA_BG2YH : GPU_setYH(MainScreen.gpu, 2, val); return; - case SUB_BG2_CY : + case REG_DISPB_BG2YL : GPU_setYL(SubScreen.gpu, 2, val); return; - case SUB_BG2_CY + 2 : + case REG_DISPB_BG2YH : GPU_setYH(SubScreen.gpu, 2, val); return; - case BG3_CY : + case REG_DISPA_BG3YL : GPU_setYL(MainScreen.gpu, 3, val); return; - case BG3_CY + 2 : + case REG_DISPA_BG3YH : GPU_setYH(MainScreen.gpu, 3, val); return; - case SUB_BG3_CY : + case REG_DISPB_BG3YL : GPU_setYL(SubScreen.gpu, 3, val); return; - case SUB_BG3_CY + 2 : + case REG_DISPB_BG3YH : GPU_setYH(SubScreen.gpu, 3, val); return; - case BG0_CR : + case REG_DISPA_BG0CNT : //GPULOG("MAIN BG0 SETPROP 16B %08X\r\n", val); GPU_setBGProp(MainScreen.gpu, 0, val); T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x8, val); return; - case BG1_CR : + case REG_DISPA_BG1CNT : //GPULOG("MAIN BG1 SETPROP 16B %08X\r\n", val); GPU_setBGProp(MainScreen.gpu, 1, val); T1WriteWord(MMU.MMU_MEM[proc][0x40], 0xA, val); return; - case BG2_CR : + case REG_DISPA_BG2CNT : //GPULOG("MAIN BG2 SETPROP 16B %08X\r\n", val); GPU_setBGProp(MainScreen.gpu, 2, val); T1WriteWord(MMU.MMU_MEM[proc][0x40], 0xC, val); return; - case BG3_CR : + case REG_DISPA_BG3CNT : //GPULOG("MAIN BG3 SETPROP 16B %08X\r\n", val); GPU_setBGProp(MainScreen.gpu, 3, val); T1WriteWord(MMU.MMU_MEM[proc][0x40], 0xE, val); return; - case SUB_BG0_CR : + case REG_DISPB_BG0CNT : //GPULOG("SUB BG0 SETPROP 16B %08X\r\n", val); GPU_setBGProp(SubScreen.gpu, 0, val); T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x1008, val); return; - case SUB_BG1_CR : + case REG_DISPB_BG1CNT : //GPULOG("SUB BG1 SETPROP 16B %08X\r\n", val); GPU_setBGProp(SubScreen.gpu, 1, val); T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x100A, val); return; - case SUB_BG2_CR : + case REG_DISPB_BG2CNT : //GPULOG("SUB BG2 SETPROP 16B %08X\r\n", val); GPU_setBGProp(SubScreen.gpu, 2, val); T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x100C, val); return; - case SUB_BG3_CR : + case REG_DISPB_BG3CNT : //GPULOG("SUB BG3 SETPROP 16B %08X\r\n", val); GPU_setBGProp(SubScreen.gpu, 3, val); T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x100E, val); @@ -1969,37 +1965,37 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val) } #endif return; - case CARD_CR2 : + case REG_GCROMCTRL : { int i; - if(MEM_8(MMU.MMU_MEM[proc], CARD_COMMAND) == 0xB7) + if(MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT) == 0xB7) { - MMU.dscard[proc].adress = (MEM_8(MMU.MMU_MEM[proc], CARD_COMMAND+1) << 24) | (MEM_8(MMU.MMU_MEM[proc], CARD_COMMAND+2) << 16) | (MEM_8(MMU.MMU_MEM[proc], CARD_COMMAND+3) << 8) | (MEM_8(MMU.MMU_MEM[proc], CARD_COMMAND+4)); + MMU.dscard[proc].adress = (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT+1) << 24) | (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT+2) << 16) | (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT+3) << 8) | (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT+4)); MMU.dscard[proc].transfer_count = 0x80;// * ((val>>24)&7)); } - else if (MEM_8(MMU.MMU_MEM[proc], CARD_COMMAND) == 0xB8) + else if (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT) == 0xB8) { // Get ROM chip ID val |= 0x800000; // Data-Word Status - T1WriteLong(MMU.MMU_MEM[proc][(CARD_CR2 >> 20) & 0xff], CARD_CR2 & 0xfff, val); + T1WriteLong(MMU.MMU_MEM[proc][(REG_GCROMCTRL >> 20) & 0xff], REG_GCROMCTRL & 0xfff, val); MMU.dscard[proc].adress = 0; } else { - LOG("CARD command: %02X\n", MEM_8(MMU.MMU_MEM[proc], CARD_COMMAND)); + LOG("CARD command: %02X\n", MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT)); } CARDLOG("%08X : %08X %08X\r\n", adr, val, adresse[proc]); - val |= CARD_DATA_READY; + val |= 0x00800000; if(MMU.dscard[proc].adress == 0) { - val &= ~CARD_ACTIVATE; - T1WriteLong(MMU.MMU_MEM[proc][(CARD_CR2 >> 20) & 0xff], CARD_CR2 & 0xfff, val); + val &= ~0x80000000; + T1WriteLong(MMU.MMU_MEM[proc][(REG_GCROMCTRL >> 20) & 0xff], REG_GCROMCTRL & 0xfff, val); return; } - T1WriteLong(MMU.MMU_MEM[proc][(CARD_CR2 >> 20) & 0xff], CARD_CR2 & 0xfff, val); + T1WriteLong(MMU.MMU_MEM[proc][(REG_GCROMCTRL >> 20) & 0xff], REG_GCROMCTRL & 0xfff, val); /* launch DMA if start flag was set to "DS Cart" */ if(proc == ARMCPU_ARM7) i = 2; diff --git a/trunk/desmume/src/MMU.h b/trunk/desmume/src/MMU.h index d9e577a64..6362fe458 100644 --- a/trunk/desmume/src/MMU.h +++ b/trunk/desmume/src/MMU.h @@ -26,7 +26,6 @@ #include "dscard.h" #include "ARM9.h" -#include "nds/serial.h" #include "mc.h" #ifdef __cplusplus diff --git a/trunk/desmume/src/Makefile.am b/trunk/desmume/src/Makefile.am index 7b3455db7..18be5aaa6 100644 --- a/trunk/desmume/src/Makefile.am +++ b/trunk/desmume/src/Makefile.am @@ -10,7 +10,7 @@ libdesmume_a_SOURCES = \ FIFO.c FIFO.h \ GPU.c GPU.h \ mc.c mc.h \ - MMU.c MMU.h NDSSystem.c NDSSystem.h \ + MMU.c MMU.h NDSSystem.c NDSSystem.h registers.h \ saves.c saves.h \ SPU.c SPU.h \ thumb_instructions.c thumb_instructions.h diff --git a/trunk/desmume/src/NDSSystem.c b/trunk/desmume/src/NDSSystem.c index 845298f9e..7461c1e1b 100644 --- a/trunk/desmume/src/NDSSystem.c +++ b/trunk/desmume/src/NDSSystem.c @@ -258,6 +258,9 @@ void NDS_FreeROM(void) if (MMU.CART_ROM != MMU.UNUSED_RAM) free(MMU.CART_ROM); MMU_unsetRom(); + if (MMU.bupmem.fp) + fclose(MMU.bupmem.fp); + MMU.bupmem.fp = NULL; } void NDS_Reset(void) diff --git a/trunk/desmume/src/NDSSystem.h b/trunk/desmume/src/NDSSystem.h index da72812e9..58902a470 100644 --- a/trunk/desmume/src/NDSSystem.h +++ b/trunk/desmume/src/NDSSystem.h @@ -40,22 +40,6 @@ extern BOOL click; //#define LOG_ARM9 //#define LOG_ARM7 -#define REG_DIVCNT (0x280>>2) -#define REG_DIV_NUMER_L (0x290>>2) -#define REG_DIV_NUMER_H (0x294>>2) -#define REG_DIV_DENOM_L (0x298>>2) -#define REG_DIV_DENOM_H (0x29C>>2) -#define REG_DIV_RESULT_L (0x2A0>>2) -#define REG_DIV_RESULT_H (0x2A4>>2) -#define REG_DIV_REMAIN_L (0x2A8>>2) -#define REG_DIV_REMAIN_H (0x2AC>>2) -#define REG_SQRTCNT (0x2B0>>2) -#define REG_SQRT_PARAM_L (0x2B8>>2) -#define REG_SQRT_PARAM_H (0x2BC>>2) -#define REG_SQRT_RESULT (0x2B4>>2) -#define reg_IPCSYNC (0x180>>1) -#define reg_IPCFIFOCNT (0x184>>1) - typedef struct { char gameTile[12]; diff --git a/trunk/desmume/src/mc.h b/trunk/desmume/src/mc.h index 16098dd4f..bd8a5e138 100644 --- a/trunk/desmume/src/mc.h +++ b/trunk/desmume/src/mc.h @@ -7,7 +7,6 @@ extern "C" { #include #include "types.h" -#include "nds/serial.h" #define MC_TYPE_AUTODETECT 0x0 #define MC_TYPE_EEPROM1 0x1 diff --git a/trunk/desmume/src/registers.h b/trunk/desmume/src/registers.h new file mode 100644 index 000000000..5d42a46fd --- /dev/null +++ b/trunk/desmume/src/registers.h @@ -0,0 +1,187 @@ +#ifndef REGISTERS_H +#define REGISTERS_H + +// Display Engine A +#define REG_DISPA_DISPCNT 0x04000000 +#define REG_DISPA_DISPSTAT 0x04000004 +#define REG_DISPA_VCOUNT 0x04000006 +#define REG_DISPA_BG0CNT 0x04000008 +#define REG_DISPA_BG1CNT 0x0400000A +#define REG_DISPA_BG2CNT 0x0400000C +#define REG_DISPA_BG3CNT 0x0400000E +#define REG_DISPA_BG0HOFS 0x04000010 +#define REG_DISPA_BG0VOFS 0x04000012 +#define REG_DISPA_BG1HOFS 0x04000014 +#define REG_DISPA_BG1VOFS 0x04000016 +#define REG_DISPA_BG2HOFS 0x04000018 +#define REG_DISPA_BG2VOFS 0x0400001A +#define REG_DISPA_BG3HOFS 0x0400001C +#define REG_DISPA_BG3VOFS 0x0400001E +#define REG_DISPA_BG2PA 0x04000020 +#define REG_DISPA_BG2PB 0x04000022 +#define REG_DISPA_BG2PC 0x04000024 +#define REG_DISPA_BG2PD 0x04000026 +#define REG_DISPA_BG2XL 0x04000028 +#define REG_DISPA_BG2XH 0x0400002A +#define REG_DISPA_BG2YL 0x0400002C +#define REG_DISPA_BG2YH 0x0400002E +#define REG_DISPA_BG3PA 0x04000030 +#define REG_DISPA_BG3PB 0x04000032 +#define REG_DISPA_BG3PC 0x04000034 +#define REG_DISPA_BG3PD 0x04000036 +#define REG_DISPA_BG3XL 0x04000038 +#define REG_DISPA_BG3XH 0x0400003A +#define REG_DISPA_BG3YL 0x0400003C +#define REG_DISPA_BG3YH 0x0400003E +#define REG_DISPA_WIN0H 0x04000040 +#define REG_DISPA_WIN1H 0x04000042 +#define REG_DISPA_WIN0V 0x04000044 +#define REG_DISPA_WIN1V 0x04000046 +#define REG_DISPA_WININ 0x04000048 +#define REG_DISPA_WINOUT 0x0400004A +#define REG_DISPA_MOSAIC 0x0400004C +#define REG_DISPA_BLDCNT 0x04000050 +#define REG_DISPA_BLDALPHA 0x04000052 +#define REG_DISPA_BLDY 0x04000054 +#define REG_DISPA_DISP3DCNT 0x04000060 +#define REG_DISPA_DISPCAPCNT 0x04000064 +#define REG_DISPA_DISPMMEMFIFO 0x04000068 +#define REG_DISPA_MASTERBRIGHT 0x0400006C + +// DMA +#define REG_DMA0SAD 0x040000B0 +#define REG_DMA0DAD 0x040000B4 +#define REG_DMA0CNTL 0x040000B8 +#define REG_DMA0CNTH 0x040000BA +#define REG_DMA1SAD 0x040000BC +#define REG_DMA1DAD 0x040000C0 +#define REG_DMA1CNTL 0x040000C4 +#define REG_DMA1CNTH 0x040000C6 +#define REG_DMA2SAD 0x040000C8 +#define REG_DMA2DAD 0x040000CC +#define REG_DMA2CNTL 0x040000D0 +#define REG_DMA2CNTH 0x040000D2 +#define REG_DMA3SAD 0x040000D4 +#define REG_DMA3DAD 0x040000D8 +#define REG_DMA3CNTL 0x040000DC +#define REG_DMA3CNTH 0x040000DE +#define REG_DMA0FILL 0x040000E0 +#define REG_DMA1FILL 0x040000E4 +#define REG_DMA2FILL 0x040000E8 +#define REG_DMA3FILL 0x040000EC + +// Timers +#define REG_TM0CNTL 0x04000100 +#define REG_TM0CNTH 0x04000102 +#define REG_TM1CNTL 0x04000104 +#define REG_TM1CNTH 0x04000106 +#define REG_TM2CNTL 0x04000108 +#define REG_TM2CNTH 0x0400010A +#define REG_TM3CNTL 0x0400010C +#define REG_TM3CNTH 0x0400010E + +// SIO/Keypad Input/RTC +#define REG_SIODATA32 0x04000120 +#define REG_SIOCNT 0x04000128 +#define REG_KEYINPUT 0x04000130 +#define REG_KEYCNT 0x04000132 +#define REG_RCNT 0x04000134 +#define REG_EXTKEYIN 0x04000136 +#define REG_RTC 0x04000138 + +// IPC +#define REG_IPCSYNC 0x04000180 +#define REG_IPCFIFOCNT 0x04000184 +#define REG_IPCFIFOSEND 0x04000188 + +// ROM +#define REG_AUXSPICNT 0x040001A0 +#define REG_AUXSPIDATA 0x040001A2 +#define REG_GCROMCTRL 0x040001A4 +#define REG_GCCMDOUT 0x040001A8 +#define REG_GCDATAIN 0x04100010 +#define REG_ENCSEED0L 0x040001B0 +#define REG_ENCSEED1L 0x040001B4 +#define REG_ENCSEED0H 0x040001B8 +#define REG_ENCSEED1H 0x040001BC +#define REG_SPICNT 0x040001C0 +#define REG_SPIDATA 0x040001C2 + +// Memory/IRQ +#define REG_EXMEMCNT 0x04000204 +#define REG_WIFIWAITCNT 0x04000206 +#define REG_IME 0x04000208 +#define REG_IE 0x04000210 +#define REG_IF 0x04000214 +#define REG_VRAMCNTA 0x04000240 +#define REG_VRAMSTAT 0x04000240 +#define REG_VRAMCNTB 0x04000241 +#define REG_WRAMSTAT 0x04000241 +#define REG_VRAMCNTC 0x04000242 +#define REG_VRAMCNTD 0x04000243 +#define REG_VRAMCNTE 0x04000244 +#define REG_VRAMCNTF 0x04000245 +#define REG_VRAMCNTG 0x04000246 +#define REG_WRAMCNT 0x04000247 +#define REG_VRAMCNTH 0x04000248 +#define REG_VRAMCNTI 0x04000249 + +// Math +#define REG_DIVCNT 0x04000280 +#define REG_DIVNUMER 0x04000290 +#define REG_DIVDENOM 0x04000298 +#define REG_DIVRESULT 0x040002A0 +#define REG_DIVREMRESULT 0x040002A8 +#define REG_SQRTCNT 0x040002B0 +#define REG_SQRTRESULT 0x040002B4 +#define REG_SQRTPARAM 0x040002B8 + +// Other +#define REG_POSTFLG 0x04000300 +#define REG_HALTCNT 0x04000301 +#define REG_POWCNT1 0x04000304 +#define REG_POWCNT2 0x04000304 +#define REG_BIOSPROT 0x04000308 + +#define REG_DISPB_DISPCNT 0x04001000 +#define REG_DISPB_BG0CNT 0x04001008 +#define REG_DISPB_BG1CNT 0x0400100A +#define REG_DISPB_BG2CNT 0x0400100C +#define REG_DISPB_BG3CNT 0x0400100E +#define REG_DISPB_BG0HOFS 0x04001010 +#define REG_DISPB_BG0VOFS 0x04001012 +#define REG_DISPB_BG1HOFS 0x04001014 +#define REG_DISPB_BG1VOFS 0x04001016 +#define REG_DISPB_BG2HOFS 0x04001018 +#define REG_DISPB_BG2VOFS 0x0400101A +#define REG_DISPB_BG3HOFS 0x0400101C +#define REG_DISPB_BG3VOFS 0x0400101E +#define REG_DISPB_BG2PA 0x04001020 +#define REG_DISPB_BG2PB 0x04001022 +#define REG_DISPB_BG2PC 0x04001024 +#define REG_DISPB_BG2PD 0x04001026 +#define REG_DISPB_BG2XL 0x04001028 +#define REG_DISPB_BG2XH 0x0400102A +#define REG_DISPB_BG2YL 0x0400102C +#define REG_DISPB_BG2YH 0x0400102E +#define REG_DISPB_BG3PA 0x04001030 +#define REG_DISPB_BG3PB 0x04001032 +#define REG_DISPB_BG3PC 0x04001034 +#define REG_DISPB_BG3PD 0x04001036 +#define REG_DISPB_BG3XL 0x04001038 +#define REG_DISPB_BG3XH 0x0400103A +#define REG_DISPB_BG3YL 0x0400103C +#define REG_DISPB_BG3YH 0x0400103E +#define REG_DISPB_WIN0H 0x04001040 +#define REG_DISPB_WIN1H 0x04001042 +#define REG_DISPB_WIN0V 0x04001044 +#define REG_DISPB_WIN1V 0x04001046 +#define REG_DISPB_WININ 0x04001048 +#define REG_DISPB_WINOUT 0x0400104A +#define REG_DISPB_MOSAIC 0x0400104C +#define REG_DISPB_BLDCNT 0x04001050 +#define REG_DISPB_BLDALPHA 0x04001052 +#define REG_DISPB_BLDY 0x04001054 +#define REG_DISPB_MASTERBRIGHT 0x0400106C + +#endif