diff --git a/desmume/src/MMU.cpp b/desmume/src/MMU.cpp index 0e49264cc..87e0f198f 100644 --- a/desmume/src/MMU.cpp +++ b/desmume/src/MMU.cpp @@ -1162,6 +1162,14 @@ void FASTCALL MMU_writeToGCControl(u32 val) card.transfer_count = 1; } break; + // Nand Write? + //case 0x8B: + case 0x85: + { + card.address = 0; + card.transfer_count = 0x80; + } + break; // Data read case 0x00: @@ -1256,10 +1264,10 @@ void FASTCALL MMU_writeToGCControl(u32 val) default: { - LOG("WRITE CARD command: %02X%02X%02X%02X%02X%02X%02X%02X\t", + INFO("WRITE CARD command: %02X%02X%02X%02X%02X%02X%02X%02X\t", card.command[0], card.command[1], card.command[2], card.command[3], card.command[4], card.command[5], card.command[6], card.command[7]); - LOG("FROM: %08X\n", (PROCNUM ? NDS_ARM7:NDS_ARM9).instruct_adr); + INFO("FROM: %08X\n", (PROCNUM ? NDS_ARM7:NDS_ARM9).instruct_adr); card.address = 0; card.transfer_count = 0; @@ -1305,9 +1313,15 @@ u32 MMU_readFromGC() val = 0; //Unsure what to return here so return 0 for now break; - // Nand Error? + // Nand Status? case 0xD6: - val = 0x80; //0x80 == ok? + //0x80 == busy + val = 0x20; //0x20 == ready + break; + + //case 0x8B: + case 0x85: + val = 0; //Unsure what to return here so return 0 for now break; // Data read @@ -1318,7 +1332,7 @@ u32 MMU_readFromGC() // Make sure any reads below 0x8000 redirect to 0x8000+(adr&0x1FF) as on real cart if((card.command[0] == 0xB7) && (card.address < 0x8000)) { - LOG("Read below 0x8000 (0x%04X) from: ARM%s %08X\n", + INFO("Read below 0x8000 (0x%04X) from: ARM%s %08X\n", card.address, (PROCNUM ? "7":"9"), (PROCNUM ? NDS_ARM7:NDS_ARM9).instruct_adr); card.address = (0x8000 + (card.address&0x1FF)); @@ -1394,10 +1408,10 @@ u32 MMU_readFromGC() // --- Ninja SD commands end --------------------------------- default: - LOG("READ CARD command: %02X%02X%02X%02X%02X%02X%02X%02X\t", + INFO("READ CARD command: %02X%02X%02X%02X%02X%02X%02X%02X\t", card.command[0], card.command[1], card.command[2], card.command[3], card.command[4], card.command[5], card.command[6], card.command[7]); - LOG("FROM: %08X\n", (PROCNUM ? NDS_ARM7:NDS_ARM9).instruct_adr); + INFO("FROM: %08X\n", (PROCNUM ? NDS_ARM7:NDS_ARM9).instruct_adr); break; } @@ -2616,7 +2630,6 @@ void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val) // raise an interrupt request to the CPU if needed if ( MMU.reg_IE[ARMCPU_ARM9] & MMU.reg_IF[ARMCPU_ARM9]) { - NDS_ARM9.wIRQ = TRUE; NDS_ARM9.waitIRQ = FALSE; } } @@ -2632,7 +2645,6 @@ void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val) // raise an interrupt request to the CPU if needed if ( MMU.reg_IE[ARMCPU_ARM9] & MMU.reg_IF[ARMCPU_ARM9]) { - NDS_ARM9.wIRQ = TRUE; NDS_ARM9.waitIRQ = FALSE; } } @@ -2647,7 +2659,6 @@ void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val) // raise an interrupt request to the CPU if needed if ( MMU.reg_IE[ARMCPU_ARM9] & MMU.reg_IF[ARMCPU_ARM9]) { - NDS_ARM9.wIRQ = TRUE; NDS_ARM9.waitIRQ = FALSE; } } @@ -3024,7 +3035,6 @@ void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val) // raise an interrupt request to the CPU if needed if ( MMU.reg_IE[ARMCPU_ARM9] & MMU.reg_IF[ARMCPU_ARM9]) { - NDS_ARM9.wIRQ = TRUE; NDS_ARM9.waitIRQ = FALSE; } } @@ -3041,7 +3051,6 @@ void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val) // raise an interrupt request to the CPU if needed if ( MMU.reg_IE[ARMCPU_ARM9] & MMU.reg_IF[ARMCPU_ARM9]) { - NDS_ARM9.wIRQ = TRUE; NDS_ARM9.waitIRQ = FALSE; } } @@ -3661,7 +3670,6 @@ void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val) /* raise an interrupt request to the CPU if needed */ if ( MMU.reg_IE[ARMCPU_ARM7] & MMU.reg_IF[ARMCPU_ARM7]) { - NDS_ARM7.wIRQ = TRUE; NDS_ARM7.waitIRQ = FALSE; } } @@ -3677,7 +3685,6 @@ void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val) /* raise an interrupt request to the CPU if needed */ if ( MMU.reg_IE[ARMCPU_ARM7] & MMU.reg_IF[ARMCPU_ARM7]) { - NDS_ARM7.wIRQ = TRUE; NDS_ARM7.waitIRQ = FALSE; } } @@ -3693,7 +3700,6 @@ void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val) /* raise an interrupt request to the CPU if needed */ if ( MMU.reg_IE[ARMCPU_ARM7] & MMU.reg_IF[ARMCPU_ARM7]) { - NDS_ARM7.wIRQ = TRUE; NDS_ARM7.waitIRQ = FALSE; } } @@ -3800,7 +3806,6 @@ void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val) // raise an interrupt request to the CPU if needed if ( MMU.reg_IE[ARMCPU_ARM7] & MMU.reg_IF[ARMCPU_ARM7]) { - NDS_ARM7.wIRQ = TRUE; NDS_ARM7.waitIRQ = FALSE; } } @@ -3817,7 +3822,6 @@ void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val) /* raise an interrupt request to the CPU if needed */ if ( MMU.reg_IE[ARMCPU_ARM7] & MMU.reg_IF[ARMCPU_ARM7]) { - NDS_ARM7.wIRQ = TRUE; NDS_ARM7.waitIRQ = FALSE; } } diff --git a/desmume/src/NDSSystem.h b/desmume/src/NDSSystem.h index 9bd2e9654..257ef1580 100644 --- a/desmume/src/NDSSystem.h +++ b/desmume/src/NDSSystem.h @@ -380,7 +380,6 @@ static INLINE void NDS_ARM9HBlankInt(void) { //MMU.reg_IF[0] |= 2;// & (MMU.reg_IME[0] << 1);// (MMU.reg_IE[0] & (1<<1)); setIF(0, 2); - NDS_ARM9.wIRQ = TRUE; } } @@ -390,7 +389,6 @@ static INLINE void NDS_ARM7HBlankInt(void) { // MMU.reg_IF[1] |= 2;// & (MMU.reg_IME[1] << 1);// (MMU.reg_IE[1] & (1<<1)); setIF(1, 2); - NDS_ARM7.wIRQ = TRUE; } } @@ -400,7 +398,6 @@ static INLINE void NDS_ARM9VBlankInt(void) { // MMU.reg_IF[0] |= 1;// & (MMU.reg_IME[0]);// (MMU.reg_IE[0] & 1); setIF(0, 1); - NDS_ARM9.wIRQ = TRUE; //emu_halt(); /*logcount++;*/ } @@ -411,7 +408,6 @@ static INLINE void NDS_ARM7VBlankInt(void) if(T1ReadWord(MMU.ARM7_REG, 4) & 0x8) // MMU.reg_IF[1] |= 1;// & (MMU.reg_IME[1]);// (MMU.reg_IE[1] & 1); setIF(1, 1); - NDS_ARM7.wIRQ = TRUE; //emu_halt(); } diff --git a/desmume/src/armcpu.h b/desmume/src/armcpu.h index 7e28411ef..09e324b90 100644 --- a/desmume/src/armcpu.h +++ b/desmume/src/armcpu.h @@ -172,7 +172,6 @@ typedef struct armcpu_t u32 intVector; u8 LDTBit; //1 : ARMv5 style 0 : non ARMv5 BOOL waitIRQ; - BOOL wIRQ; BOOL wirq; u32 (* *swi_tab)(); @@ -235,7 +234,6 @@ static INLINE void NDS_makeARM9Int(u32 num) /* generate the interrupt if enabled */ if ((MMU.reg_IE[0] & (1 << num)) && MMU.reg_IME[0]) { - NDS_ARM9.wIRQ = TRUE; NDS_ARM9.waitIRQ = FALSE; } } @@ -249,7 +247,6 @@ static INLINE void NDS_makeARM7Int(u32 num) /* generate the interrupt if enabled */ if ((MMU.reg_IE[1] & (1 << num)) && MMU.reg_IME[1]) { - NDS_ARM7.wIRQ = TRUE; NDS_ARM7.waitIRQ = FALSE; } } diff --git a/desmume/src/cp15.cpp b/desmume/src/cp15.cpp index 2b646c5c6..390a27c25 100644 --- a/desmume/src/cp15.cpp +++ b/desmume/src/cp15.cpp @@ -409,6 +409,7 @@ BOOL armcp15_moveCP2ARM(armcp15_t *armcp15, u32 * R, u8 CRn, u8 CRm, u8 opcode1, static u32 CP15wait4IRQ(armcpu_t *cpu) { + u32 instructAddr = cpu->instruct_adr; /* on the first call, wirq is not set */ if(cpu->wirq) { @@ -420,16 +421,16 @@ static u32 CP15wait4IRQ(armcpu_t *cpu) return 1; /* return execution */ } /* otherwise, repeat this instruction */ - cpu->R[15] = cpu->instruct_adr; - cpu->next_instruction = cpu->R[15]; + cpu->R[15] = instructAddr; + cpu->next_instruction = instructAddr; return 1; } /* first run, set us into waiting state */ cpu->waitIRQ = 1; cpu->wirq = 1; /* and set next instruction to repeat this */ - cpu->R[15] = cpu->instruct_adr; - cpu->next_instruction = cpu->R[15]; + cpu->R[15] = instructAddr; + cpu->next_instruction = instructAddr; /* CHECKME: IME shouldn't be modified (?) */ MMU.reg_IME[0] = 1; return 1; diff --git a/desmume/src/mc.cpp b/desmume/src/mc.cpp index d82fb680d..f1c8761bb 100644 --- a/desmume/src/mc.cpp +++ b/desmume/src/mc.cpp @@ -485,7 +485,7 @@ u8 BackupDevice::data_command(u8 val, int cpu) break; default: - printf("COMMAND%c: Unhandled Backup Memory command: %02X FROM %08X\n",(cpu==ARMCPU_ARM9)?'9':'7',val, NDS_ARM9.instruct_adr); + printf("COMMAND%c: Unhandled Backup Memory command: %02X FROM %08X\n",(cpu==ARMCPU_ARM9)?'9':'7',val, (cpu==ARMCPU_ARM9)?NDS_ARM9.instruct_adr:NDS_ARM7.instruct_adr); break; } } @@ -857,7 +857,7 @@ u32 BackupDevice::pad_up_size(u32 startSize) printf("PANIC! Couldn't pad up save size. Refusing to pad.\n"); padSize = startSize; } - return padSize; + return padSize; } void BackupDevice::lazy_flush() diff --git a/desmume/src/saves.cpp b/desmume/src/saves.cpp index 95e493df3..ab93259fe 100644 --- a/desmume/src/saves.cpp +++ b/desmume/src/saves.cpp @@ -101,7 +101,7 @@ SFORMAT SF_ARM7[]={ { "7int", 4, 1, &NDS_ARM7.intVector }, { "7LDT", 1, 1, &NDS_ARM7.LDTBit }, { "7Wai", 4, 1, &NDS_ARM7.waitIRQ }, - { "7wIR", 4, 1, &NDS_ARM7.wIRQ, }, + //{ "7wIR", 4, 1, &NDS_ARM7.wIRQ, }, { "7wir", 4, 1, &NDS_ARM7.wirq, }, { 0 } }; @@ -138,7 +138,7 @@ SFORMAT SF_ARM9[]={ { "9int", 4, 1, &NDS_ARM9.intVector}, { "9LDT", 1, 1, &NDS_ARM9.LDTBit}, { "9Wai", 4, 1, &NDS_ARM9.waitIRQ}, - { "9wIR", 4, 1, &NDS_ARM9.wIRQ}, + //{ "9wIR", 4, 1, &NDS_ARM9.wIRQ}, { "9wir", 4, 1, &NDS_ARM9.wirq}, { 0 } }; diff --git a/desmume/src/thumb_instructions.cpp b/desmume/src/thumb_instructions.cpp index 48aa63cf5..3fb57349b 100644 --- a/desmume/src/thumb_instructions.cpp +++ b/desmume/src/thumb_instructions.cpp @@ -882,37 +882,52 @@ TEMPLATE static u32 FASTCALL OP_STMIA_THUMB(const u32 i) { u32 adr = cpu->R[REG_NUM(i, 8)]; u32 c = 0, j; + u32 erList = 1; //Empty Register List - if (BIT_N(i, REG_NUM(i, 8))) - printf("STMIA with Rb in Rlist\n"); + if (BIT_N(i, REG_NUM(i, 8))) + printf("STMIA with Rb in Rlist\n"); for(j = 0; j<8; ++j) + { if(BIT_N(i, j)) { WRITE32(cpu->mem_if->data, adr, cpu->R[j]); c += MMU_memAccessCycles(adr); adr += 4; + erList = 0; //Register List isnt empty } + } + + if (erList) + printf("STMIA with Empty Rlist\n"); + cpu->R[REG_NUM(i, 8)] = adr; - return MMU_aluMemCycles(2, c); + return MMU_aluMemCycles(2, c); } TEMPLATE static u32 FASTCALL OP_LDMIA_THUMB(const u32 i) { - u32 regIndex = REG_NUM(i, 8); + u32 regIndex = REG_NUM(i, 8); u32 adr = cpu->R[regIndex]; u32 c = 0, j; + u32 erList = 1; //Empty Register List - if (BIT_N(i, REG_NUM(i, 8))) - printf("LDMIA with Rb in Rlist\n"); + //if (BIT_N(i, regIndex)) + // printf("LDMIA with Rb in Rlist at %08X\n",cpu->instruct_adr); for(j = 0; j<8; ++j) + { if(BIT_N(i, j)) { cpu->R[j] = READ32(cpu->mem_if->data, adr); c += MMU_memAccessCycles(adr); adr += 4; + erList = 0; //Register List isnt empty } + } + + if (erList) + printf("LDMIA with Empty Rlist\n"); // Only over-write if not on the read list if(!BIT_N(i, regIndex))