diff --git a/desmume/src/arm_instructions.cpp b/desmume/src/arm_instructions.cpp
index 484672220..d4dadfd81 100644
--- a/desmume/src/arm_instructions.cpp
+++ b/desmume/src/arm_instructions.cpp
@@ -349,63 +349,63 @@ TEMPLATE static u32 FASTCALL  OP_AND_S_LSL_IMM()
 {
      const u32 &i = cpu->instruction;
      S_LSL_IMM;
-     OP_ANDS(2, 4);
+     OP_ANDS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_AND_S_LSL_REG()
 {
      const u32 &i = cpu->instruction;
      S_LSL_REG;
-     OP_ANDS(3, 5);
+     OP_ANDS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_AND_S_LSR_IMM()
 {
      const u32 &i = cpu->instruction;
      S_LSR_IMM;            
-     OP_ANDS(2, 4);
+     OP_ANDS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_AND_S_LSR_REG()
 {
      const u32 &i = cpu->instruction;
      S_LSR_REG;             
-     OP_ANDS(3, 5);
+     OP_ANDS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_AND_S_ASR_IMM()
 {
      const u32 &i = cpu->instruction;
      S_ASR_IMM;
-     OP_ANDS(2, 4);
+     OP_ANDS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_AND_S_ASR_REG()
 {
      const u32 &i = cpu->instruction;
      S_ASR_REG;                     
-     OP_ANDS(3, 5);
+     OP_ANDS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_AND_S_ROR_IMM()
 {
      const u32 &i = cpu->instruction;
      S_ROR_IMM;
-     OP_ANDS(2, 4);
+     OP_ANDS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_AND_S_ROR_REG()
 {
      const u32 &i = cpu->instruction;
      S_ROR_REG;
-     OP_ANDS(3, 5);
+     OP_ANDS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_AND_S_IMM_VAL()
 {
      const u32 &i = cpu->instruction;
      S_IMM_VALUE;
-     OP_ANDS(2, 4);
+     OP_ANDS(1, 3);
 }
 
 //--------------EOR------------------------------
@@ -504,63 +504,63 @@ TEMPLATE static u32 FASTCALL  OP_EOR_S_LSL_IMM()
 {
      const u32 &i = cpu->instruction;
      S_LSL_IMM;
-     OP_EORS(2, 4);
+     OP_EORS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_EOR_S_LSL_REG()
 {
      const u32 &i = cpu->instruction;
      S_LSL_REG;
-     OP_EORS(3, 5);
+     OP_EORS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_EOR_S_LSR_IMM()
 {
      const u32 &i = cpu->instruction;
      S_LSR_IMM;            
-     OP_EORS(2, 4);
+     OP_EORS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_EOR_S_LSR_REG()
 {
      const u32 &i = cpu->instruction;
      S_LSR_REG;            
-     OP_EORS(3, 5);
+     OP_EORS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_EOR_S_ASR_IMM()
 {
      const u32 &i = cpu->instruction;
      S_ASR_IMM;
-     OP_EORS(2, 4);
+     OP_EORS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_EOR_S_ASR_REG()
 {
      const u32 &i = cpu->instruction;
      S_ASR_REG;                     
-     OP_EORS(3, 5);
+     OP_EORS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_EOR_S_ROR_IMM()
 {
      const u32 &i = cpu->instruction;
      S_ROR_IMM;
-     OP_EORS(2, 4);
+     OP_EORS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_EOR_S_ROR_REG()
 {
      const u32 &i = cpu->instruction;
      S_ROR_REG;
-     OP_EORS(3, 5);
+     OP_EORS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_EOR_S_IMM_VAL()
 {
      const u32 &i = cpu->instruction;
      S_IMM_VALUE;
-     OP_EORS(2, 4);
+     OP_EORS(1, 3);
 }
 
 //-------------SUB-------------------------------------
@@ -662,7 +662,7 @@ TEMPLATE static u32 FASTCALL  OP_SUB_S_LSL_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      LSL_IMM;
-     OPSUBS(2, 4);
+     OPSUBS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_SUB_S_LSL_REG()
@@ -670,7 +670,7 @@ TEMPLATE static u32 FASTCALL  OP_SUB_S_LSL_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      LSL_REG;
-     OPSUBS(3, 5);
+     OPSUBS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_SUB_S_LSR_IMM()
@@ -679,7 +679,7 @@ TEMPLATE static u32 FASTCALL  OP_SUB_S_LSR_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      LSR_IMM;            
-     OPSUBS(2, 4);
+     OPSUBS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_SUB_S_LSR_REG()
@@ -687,7 +687,7 @@ TEMPLATE static u32 FASTCALL  OP_SUB_S_LSR_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      LSR_REG;             
-     OPSUBS(3, 5);
+     OPSUBS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_SUB_S_ASR_IMM()
@@ -696,7 +696,7 @@ TEMPLATE static u32 FASTCALL  OP_SUB_S_ASR_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      ASR_IMM;
-     OPSUBS(2, 4);
+     OPSUBS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_SUB_S_ASR_REG()
@@ -704,7 +704,7 @@ TEMPLATE static u32 FASTCALL  OP_SUB_S_ASR_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      ASR_REG;                     
-     OPSUBS(3, 5);
+     OPSUBS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_SUB_S_ROR_IMM()
@@ -713,7 +713,7 @@ TEMPLATE static u32 FASTCALL  OP_SUB_S_ROR_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      ROR_IMM;
-     OPSUBS(2, 4);
+     OPSUBS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_SUB_S_ROR_REG()
@@ -721,7 +721,7 @@ TEMPLATE static u32 FASTCALL  OP_SUB_S_ROR_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      ROR_REG;
-     OPSUBS(3, 5);
+     OPSUBS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_SUB_S_IMM_VAL()
@@ -729,7 +729,7 @@ TEMPLATE static u32 FASTCALL  OP_SUB_S_IMM_VAL()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      IMM_VALUE;
-     OPSUBS(2, 4);
+     OPSUBS(1, 3);
 }
 
 //------------------RSB------------------------
@@ -831,7 +831,7 @@ TEMPLATE static u32 FASTCALL  OP_RSB_S_LSL_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      LSL_IMM;
-     OP_RSBS(2, 4);
+     OP_RSBS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_RSB_S_LSL_REG()
@@ -839,7 +839,7 @@ TEMPLATE static u32 FASTCALL  OP_RSB_S_LSL_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      LSL_REG;
-     OP_RSBS(3, 5);
+     OP_RSBS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_RSB_S_LSR_IMM()
@@ -848,7 +848,7 @@ TEMPLATE static u32 FASTCALL  OP_RSB_S_LSR_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      LSR_IMM;            
-     OP_RSBS(2, 4);
+     OP_RSBS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_RSB_S_LSR_REG()
@@ -856,7 +856,7 @@ TEMPLATE static u32 FASTCALL  OP_RSB_S_LSR_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      LSR_REG;             
-     OP_RSBS(3, 5);
+     OP_RSBS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_RSB_S_ASR_IMM()
@@ -865,7 +865,7 @@ TEMPLATE static u32 FASTCALL  OP_RSB_S_ASR_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      ASR_IMM;
-     OP_RSBS(2, 4);
+     OP_RSBS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_RSB_S_ASR_REG()
@@ -873,7 +873,7 @@ TEMPLATE static u32 FASTCALL  OP_RSB_S_ASR_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      ASR_REG;                     
-     OP_RSBS(3, 5);
+     OP_RSBS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_RSB_S_ROR_IMM()
@@ -882,7 +882,7 @@ TEMPLATE static u32 FASTCALL  OP_RSB_S_ROR_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      ROR_IMM;
-     OP_RSBS(2, 4);
+     OP_RSBS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_RSB_S_ROR_REG()
@@ -890,7 +890,7 @@ TEMPLATE static u32 FASTCALL  OP_RSB_S_ROR_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      ROR_REG;
-     OP_RSBS(3, 5);
+     OP_RSBS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_RSB_S_IMM_VAL()
@@ -898,7 +898,7 @@ TEMPLATE static u32 FASTCALL  OP_RSB_S_IMM_VAL()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      IMM_VALUE;
-     OP_RSBS(2, 4);
+     OP_RSBS(1, 3);
 }
 
 //------------------ADD-----------------------------------
@@ -1000,7 +1000,7 @@ TEMPLATE static u32 FASTCALL  OP_ADD_S_LSL_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      LSL_IMM;
-     OP_ADDS(2, 4);
+     OP_ADDS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ADD_S_LSL_REG()
@@ -1008,7 +1008,7 @@ TEMPLATE static u32 FASTCALL  OP_ADD_S_LSL_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      LSL_REG;
-     OP_ADDS(3, 5);
+     OP_ADDS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ADD_S_LSR_IMM()
@@ -1017,7 +1017,7 @@ TEMPLATE static u32 FASTCALL  OP_ADD_S_LSR_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      LSR_IMM;            
-     OP_ADDS(2, 4);
+     OP_ADDS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ADD_S_LSR_REG()
@@ -1025,7 +1025,7 @@ TEMPLATE static u32 FASTCALL  OP_ADD_S_LSR_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      LSR_REG;             
-     OP_ADDS(3, 5);
+     OP_ADDS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ADD_S_ASR_IMM()
@@ -1034,7 +1034,7 @@ TEMPLATE static u32 FASTCALL  OP_ADD_S_ASR_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      ASR_IMM;
-     OP_ADDS(2, 4);
+     OP_ADDS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ADD_S_ASR_REG()
@@ -1042,7 +1042,7 @@ TEMPLATE static u32 FASTCALL  OP_ADD_S_ASR_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      ASR_REG;                     
-     OP_ADDS(3, 5);
+     OP_ADDS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ADD_S_ROR_IMM()
@@ -1051,7 +1051,7 @@ TEMPLATE static u32 FASTCALL  OP_ADD_S_ROR_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      ROR_IMM;
-     OP_ADDS(2, 4);
+     OP_ADDS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ADD_S_ROR_REG()
@@ -1059,7 +1059,7 @@ TEMPLATE static u32 FASTCALL  OP_ADD_S_ROR_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      ROR_REG;
-     OP_ADDS(3, 5);
+     OP_ADDS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ADD_S_IMM_VAL()
@@ -1067,7 +1067,7 @@ TEMPLATE static u32 FASTCALL  OP_ADD_S_IMM_VAL()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      IMM_VALUE;
-     OP_ADDS(2, 4);
+     OP_ADDS(1, 3);
 }
 
 //------------------ADC-----------------------------------
@@ -1173,7 +1173,7 @@ TEMPLATE static u32 FASTCALL  OP_ADC_S_LSL_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      LSL_IMM;
-     OP_ADCS(2, 4);
+     OP_ADCS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ADC_S_LSL_REG()
@@ -1181,7 +1181,7 @@ TEMPLATE static u32 FASTCALL  OP_ADC_S_LSL_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      LSL_REG;
-     OP_ADCS(3, 5);
+     OP_ADCS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ADC_S_LSR_IMM()
@@ -1190,7 +1190,7 @@ TEMPLATE static u32 FASTCALL  OP_ADC_S_LSR_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      LSR_IMM;            
-     OP_ADCS(2, 4);
+     OP_ADCS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ADC_S_LSR_REG()
@@ -1198,7 +1198,7 @@ TEMPLATE static u32 FASTCALL  OP_ADC_S_LSR_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      LSR_REG;             
-     OP_ADCS(3, 5);
+     OP_ADCS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ADC_S_ASR_IMM()
@@ -1207,7 +1207,7 @@ TEMPLATE static u32 FASTCALL  OP_ADC_S_ASR_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      ASR_IMM;
-     OP_ADCS(2, 4);
+     OP_ADCS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ADC_S_ASR_REG()
@@ -1215,7 +1215,7 @@ TEMPLATE static u32 FASTCALL  OP_ADC_S_ASR_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      ASR_REG;                     
-     OP_ADCS(3, 5);
+     OP_ADCS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ADC_S_ROR_IMM()
@@ -1224,7 +1224,7 @@ TEMPLATE static u32 FASTCALL  OP_ADC_S_ROR_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      ROR_IMM;
-     OP_ADCS(2, 4);
+     OP_ADCS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ADC_S_ROR_REG()
@@ -1232,7 +1232,7 @@ TEMPLATE static u32 FASTCALL  OP_ADC_S_ROR_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      ROR_REG;
-     OP_ADCS(3, 5);
+     OP_ADCS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ADC_S_IMM_VAL()
@@ -1240,7 +1240,7 @@ TEMPLATE static u32 FASTCALL  OP_ADC_S_IMM_VAL()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      IMM_VALUE;
-     OP_ADCS(2, 4);
+     OP_ADCS(1, 3);
 }
 
 //-------------SBC-------------------------------------
@@ -1348,7 +1348,7 @@ TEMPLATE static u32 FASTCALL  OP_SBC_S_LSL_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      LSL_IMM;
-     OP_SBCS(2, 4);
+     OP_SBCS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_SBC_S_LSL_REG()
@@ -1356,7 +1356,7 @@ TEMPLATE static u32 FASTCALL  OP_SBC_S_LSL_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      LSL_REG;
-     OP_SBCS(3, 5);
+     OP_SBCS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_SBC_S_LSR_IMM()
@@ -1365,7 +1365,7 @@ TEMPLATE static u32 FASTCALL  OP_SBC_S_LSR_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      LSR_IMM;            
-     OP_SBCS(2, 4);
+     OP_SBCS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_SBC_S_LSR_REG()
@@ -1373,7 +1373,7 @@ TEMPLATE static u32 FASTCALL  OP_SBC_S_LSR_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      LSR_REG;             
-     OP_SBCS(3, 5);
+     OP_SBCS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_SBC_S_ASR_IMM()
@@ -1382,7 +1382,7 @@ TEMPLATE static u32 FASTCALL  OP_SBC_S_ASR_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      ASR_IMM;
-     OP_SBCS(2, 4);
+     OP_SBCS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_SBC_S_ASR_REG()
@@ -1390,7 +1390,7 @@ TEMPLATE static u32 FASTCALL  OP_SBC_S_ASR_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      ASR_REG;                     
-     OP_SBCS(3, 5);
+     OP_SBCS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_SBC_S_ROR_IMM()
@@ -1399,7 +1399,7 @@ TEMPLATE static u32 FASTCALL  OP_SBC_S_ROR_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      ROR_IMM;
-     OP_SBCS(2, 4);
+     OP_SBCS(1, 3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_SBC_S_ROR_REG()
@@ -1407,7 +1407,7 @@ TEMPLATE static u32 FASTCALL  OP_SBC_S_ROR_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      ROR_REG;
-     OP_SBCS(3, 5);
+     OP_SBCS(2, 4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_SBC_S_IMM_VAL()
@@ -1415,7 +1415,7 @@ TEMPLATE static u32 FASTCALL  OP_SBC_S_IMM_VAL()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      IMM_VALUE;
-     OP_SBCS(2, 4);
+     OP_SBCS(1, 3);
 }
 
 //---------------RSC----------------------------------
@@ -1522,7 +1522,7 @@ TEMPLATE static u32 FASTCALL  OP_RSC_S_LSL_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      LSL_IMM;
-     OP_RSCS(2,4);
+     OP_RSCS(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_RSC_S_LSL_REG()
@@ -1530,7 +1530,7 @@ TEMPLATE static u32 FASTCALL  OP_RSC_S_LSL_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      LSL_REG;
-     OP_RSCS(3,5);
+     OP_RSCS(2,4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_RSC_S_LSR_IMM()
@@ -1539,7 +1539,7 @@ TEMPLATE static u32 FASTCALL  OP_RSC_S_LSR_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      LSR_IMM;            
-     OP_RSCS(2,4);
+     OP_RSCS(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_RSC_S_LSR_REG()
@@ -1547,7 +1547,7 @@ TEMPLATE static u32 FASTCALL  OP_RSC_S_LSR_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      LSR_REG;             
-     OP_RSCS(3,5);
+     OP_RSCS(2,4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_RSC_S_ASR_IMM()
@@ -1556,7 +1556,7 @@ TEMPLATE static u32 FASTCALL  OP_RSC_S_ASR_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      ASR_IMM;
-     OP_RSCS(2,4);
+     OP_RSCS(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_RSC_S_ASR_REG()
@@ -1564,7 +1564,7 @@ TEMPLATE static u32 FASTCALL  OP_RSC_S_ASR_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      ASR_REG;                     
-     OP_RSCS(3,5);
+     OP_RSCS(2,4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_RSC_S_ROR_IMM()
@@ -1573,7 +1573,7 @@ TEMPLATE static u32 FASTCALL  OP_RSC_S_ROR_IMM()
      u32 v = cpu->R[REG_POS(i,16)];
      u32 shift_op;
      ROR_IMM;
-     OP_RSCS(2,4);
+     OP_RSCS(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_RSC_S_ROR_REG()
@@ -1581,7 +1581,7 @@ TEMPLATE static u32 FASTCALL  OP_RSC_S_ROR_REG()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      ROR_REG;
-     OP_RSCS(3,5);
+     OP_RSCS(2,4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_RSC_S_IMM_VAL()
@@ -1589,7 +1589,7 @@ TEMPLATE static u32 FASTCALL  OP_RSC_S_IMM_VAL()
      const u32 &i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
      IMM_VALUE;
-     OP_RSCS(2,4);
+     OP_RSCS(1,3);
 }
 
 //-------------------TST----------------------------
@@ -1997,63 +1997,63 @@ TEMPLATE static u32 FASTCALL  OP_ORR_S_LSL_IMM()
 {
      const u32 &i = cpu->instruction;
      S_LSL_IMM;
-     OP_ORRS(2,4);
+     OP_ORRS(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ORR_S_LSL_REG()
 {
      const u32 &i = cpu->instruction;
      S_LSL_REG;
-     OP_ORRS(3,5);
+     OP_ORRS(2,4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ORR_S_LSR_IMM()
 {
      const u32 &i = cpu->instruction;
      S_LSR_IMM;            
-     OP_ORRS(2,4);
+     OP_ORRS(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ORR_S_LSR_REG()
 {
      const u32 &i = cpu->instruction;
      S_LSR_REG;             
-     OP_ORRS(3,5);
+     OP_ORRS(2,4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ORR_S_ASR_IMM()
 {
      const u32 &i = cpu->instruction;
      S_ASR_IMM;
-     OP_ORRS(2,4);
+     OP_ORRS(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ORR_S_ASR_REG()
 {
      const u32 &i = cpu->instruction;
      S_ASR_REG;                     
-     OP_ORRS(3,5);
+     OP_ORRS(2,4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ORR_S_ROR_IMM()
 {
      const u32 &i = cpu->instruction;
      S_ROR_IMM;
-     OP_ORRS(2,4);
+     OP_ORRS(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ORR_S_ROR_REG()
 {
      const u32 &i = cpu->instruction;
      S_ROR_REG;
-     OP_ORRS(3,5);
+     OP_ORRS(2,4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_ORR_S_IMM_VAL()
 {
      const u32 &i = cpu->instruction;
      S_IMM_VALUE;
-     OP_ORRS(2,4);
+     OP_ORRS(1,3);
 }
 
 //------------------MOV-------------------
@@ -2154,7 +2154,7 @@ TEMPLATE static u32 FASTCALL  OP_MOV_S_LSL_IMM()
 {
      const u32 &i = cpu->instruction;
      S_LSL_IMM;
-     OP_MOV_S(2,4);
+     OP_MOV_S(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_MOV_S_LSL_REG()
@@ -2162,14 +2162,14 @@ TEMPLATE static u32 FASTCALL  OP_MOV_S_LSL_REG()
      const u32 &i = cpu->instruction;
      S_LSL_REG;
 	 if (REG_POS(i,0) == 15) shift_op += 4;
-     OP_MOV_S(3,5);
+     OP_MOV_S(2,4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_MOV_S_LSR_IMM()
 {
      const u32 &i = cpu->instruction;
      S_LSR_IMM;   
-     OP_MOV_S(2,4);
+     OP_MOV_S(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_MOV_S_LSR_REG()
@@ -2177,42 +2177,42 @@ TEMPLATE static u32 FASTCALL  OP_MOV_S_LSR_REG()
      const u32 &i = cpu->instruction;
      S_LSR_REG;  
 	 if (REG_POS(i,0) == 15) shift_op += 4;
-     OP_MOV_S(3,5);           
+     OP_MOV_S(2,4);           
 }
 
 TEMPLATE static u32 FASTCALL  OP_MOV_S_ASR_IMM()
 {
      const u32 &i = cpu->instruction;
      S_ASR_IMM;
-     OP_MOV_S(2,4);
+     OP_MOV_S(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_MOV_S_ASR_REG()
 {
      const u32 &i = cpu->instruction;
      S_ASR_REG;  
-     OP_MOV_S(3,5);                   
+     OP_MOV_S(2,4);                   
 }
 
 TEMPLATE static u32 FASTCALL  OP_MOV_S_ROR_IMM()
 {
      const u32 &i = cpu->instruction;
      S_ROR_IMM;
-     OP_MOV_S(2,4);
+     OP_MOV_S(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_MOV_S_ROR_REG()
 {
      const u32 &i = cpu->instruction;
      S_ROR_REG;
-     OP_MOV_S(3,5);
+     OP_MOV_S(2,4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_MOV_S_IMM_VAL()
 {
      const u32 &i = cpu->instruction;
      S_IMM_VALUE;
-     OP_MOV_S(2,4);
+     OP_MOV_S(1,3);
 }
 
 //------------------BIC-------------------
@@ -2310,63 +2310,63 @@ TEMPLATE static u32 FASTCALL  OP_BIC_S_LSL_IMM()
 {
      const u32 &i = cpu->instruction;
      S_LSL_IMM;
-     OPP_BIC_S(2,4);
+     OPP_BIC_S(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_BIC_S_LSL_REG()
 {
      const u32 &i = cpu->instruction;
      S_LSL_REG;
-     OPP_BIC_S(3,5);
+     OPP_BIC_S(2,4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_BIC_S_LSR_IMM()
 {
      const u32 &i = cpu->instruction;
      S_LSR_IMM;            
-     OPP_BIC_S(2,4);
+     OPP_BIC_S(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_BIC_S_LSR_REG()
 {
      const u32 &i = cpu->instruction;
      S_LSR_REG;
-     OPP_BIC_S(3,5);
+     OPP_BIC_S(2,4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_BIC_S_ASR_IMM()
 {
      const u32 &i = cpu->instruction;
      S_ASR_IMM;
-     OPP_BIC_S(2,4);
+     OPP_BIC_S(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_BIC_S_ASR_REG()
 {
      const u32 &i = cpu->instruction;
      S_ASR_REG;
-     OPP_BIC_S(3,5);
+     OPP_BIC_S(2,4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_BIC_S_ROR_IMM()
 {
      const u32 &i = cpu->instruction;
      S_ROR_IMM;
-     OPP_BIC_S(2,4);
+     OPP_BIC_S(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_BIC_S_ROR_REG()
 {
      const u32 &i = cpu->instruction;
      S_ROR_REG;
-     OPP_BIC_S(3,5);
+     OPP_BIC_S(2,4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_BIC_S_IMM_VAL()
 {
      const u32 &i = cpu->instruction;
      S_IMM_VALUE;
-     OPP_BIC_S(2,4);
+     OPP_BIC_S(1,3);
 }
 
 //------------------MVN-------------------
@@ -2464,63 +2464,63 @@ TEMPLATE static u32 FASTCALL  OP_MVN_S_LSL_IMM()
 {
      const u32 &i = cpu->instruction;
      S_LSL_IMM;
-     OPP_MVN_S(2,4);
+     OPP_MVN_S(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_MVN_S_LSL_REG()
 {
      const u32 &i = cpu->instruction;
      S_LSL_REG;
-     OPP_MVN_S(3,5);
+     OPP_MVN_S(2,4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_MVN_S_LSR_IMM()
 {
      const u32 &i = cpu->instruction;
      S_LSR_IMM;            
-     OPP_MVN_S(2,4);
+     OPP_MVN_S(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_MVN_S_LSR_REG()
 {
      const u32 &i = cpu->instruction;
      S_LSR_REG;
-     OPP_MVN_S(3,5);
+     OPP_MVN_S(2,4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_MVN_S_ASR_IMM()
 {
      const u32 &i = cpu->instruction;
      S_ASR_IMM;
-     OPP_MVN_S(2,4);
+     OPP_MVN_S(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_MVN_S_ASR_REG()
 {
      const u32 &i = cpu->instruction;
      S_ASR_REG;
-     OPP_MVN_S(3,5);
+     OPP_MVN_S(2,4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_MVN_S_ROR_IMM()
 {
      const u32 &i = cpu->instruction;
      S_ROR_IMM;
-     OPP_MVN_S(2,4);
+     OPP_MVN_S(1,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_MVN_S_ROR_REG()
 {
      const u32 &i = cpu->instruction;
      S_ROR_REG;
-     OPP_MVN_S(3,5);
+     OPP_MVN_S(2,4);
 }
 
 TEMPLATE static u32 FASTCALL  OP_MVN_S_IMM_VAL()
 {
      const u32 &i = cpu->instruction;
      S_IMM_VALUE;
-     OPP_MVN_S(2,4);
+     OPP_MVN_S(1,3);
 }
 
 //-------------MUL------------------------
@@ -2563,7 +2563,7 @@ TEMPLATE static u32 FASTCALL  OP_MUL_S()
      cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]);
      cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0);
      
-     OPP_M(6,3);
+     OPP_M(5,2);
 }
 
 TEMPLATE static u32 FASTCALL  OP_MLA_S()
@@ -2573,7 +2573,7 @@ TEMPLATE static u32 FASTCALL  OP_MLA_S()
      cpu->R[REG_POS(i,16)] = cpu->R[REG_POS(i,8)] * v + cpu->R[REG_POS(i,12)];
      cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]);
      cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0);
-     OPP_M(7,4);
+     OPP_M(6,3);
 }
 
 //----------UMUL--------------------------
@@ -2614,7 +2614,7 @@ TEMPLATE static u32 FASTCALL  OP_UMULL_S()
      cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]);
      cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0);
 
-     OPP_M(7,4);
+     OPP_M(6,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_UMLAL_S()
@@ -2629,7 +2629,7 @@ TEMPLATE static u32 FASTCALL  OP_UMLAL_S()
      cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]);
      cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0);
      
-     OPP_M(8,5);
+     OPP_M(7,4);
 }
 
 //----------SMUL--------------------------
@@ -2684,7 +2684,7 @@ TEMPLATE static u32 FASTCALL  OP_SMULL_S()
 
      v &= 0xFFFFFFFF;
           
-     OPP_M(7,4);
+     OPP_M(6,3);
 }
 
 TEMPLATE static u32 FASTCALL  OP_SMLAL_S()
@@ -2702,7 +2702,7 @@ TEMPLATE static u32 FASTCALL  OP_SMLAL_S()
 
      v &= 0xFFFFFFFF;
           
-     OPP_M(8,5);
+     OPP_M(7,4);
 }
 
 //---------------SWP------------------------------