From 3bd57c4c95d51c3e83e768607cc6647de0dedf72 Mon Sep 17 00:00:00 2001 From: luigi__ Date: Wed, 7 Apr 2010 16:54:12 +0000 Subject: [PATCH] Add more TODO, and nuke the useless OP_LDR_M_IMM_OFF_POSTIND2. --- desmume/src/arm_instructions.cpp | 33 +++++--------------------------- 1 file changed, 5 insertions(+), 28 deletions(-) diff --git a/desmume/src/arm_instructions.cpp b/desmume/src/arm_instructions.cpp index dca41e770..71562944b 100644 --- a/desmume/src/arm_instructions.cpp +++ b/desmume/src/arm_instructions.cpp @@ -21,7 +21,11 @@ // ARM core TODO: // - Check all the LDM/STM opcodes: quirks when Rb included in Rlist; opcodes -// operating on user registers (LDMXX2/STMXX2) +// operating on user registers (LDMXX2/STMXX2) +// - Force User mode memory access for LDRx/STRx opcodes with bit24=0 and bit21=1 +// (has to be done at memory side; once the PU is emulated well enough) +// - Check LDMxx2/STMxx2 (those opcodes that act on User mode registers instead +// of current ones) #include "cp15.h" #include "debug.h" @@ -4104,33 +4108,6 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND(const u32 i) return MMU_aluMemAccessCycles(3,adr); } -//------------------------------------------------------------ -TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND2(const u32 i) -{ - - u32 adr = cpu->R[REG_POS(i,16)]; - u32 val = READ32(cpu->mem_if->data, adr); - u32 old; - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - return MMU_aluMemAccessCycles(5,adr); - } - - old = armcpu_switchMode(cpu, USR); - cpu->R[REG_POS(i,12)] = val; - armcpu_switchMode(cpu, old); - - cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - - return MMU_aluMemAccessCycles(3,adr); -} - //------------------------------------------------------------ TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF_POSTIND(const u32 i)