diff --git a/trunk/desmume/src/arm_instructions.c b/trunk/desmume/src/arm_instructions.c index d6313ff91..4b3fa4452 100644 --- a/trunk/desmume/src/arm_instructions.c +++ b/trunk/desmume/src/arm_instructions.c @@ -225,8 +225,8 @@ extern BOOL execute; static u32 FASTCALL OP_UND(armcpu_t *cpu) { u32 i = cpu->instruction; - LOG("Undefined instruction: 0x%08X", i); - //execute = FALSE; + LOG("Undefined instruction: %08X\n", i); + execute = FALSE; return 1; } @@ -2043,7 +2043,6 @@ static u32 FASTCALL OP_ORR_S_IMM_VAL(armcpu_t *cpu) } //------------------MOV------------------- - #define OP_MOV(a, b) cpu->R[REG_POS(i,12)] = shift_op;\ if(REG_POS(i,12)==15)\ {\ @@ -2053,7 +2052,7 @@ static u32 FASTCALL OP_ORR_S_IMM_VAL(armcpu_t *cpu) return a; #define OP_MOV_S(a, b) cpu->R[REG_POS(i,12)] = shift_op;\ - if(BIT20(i) && REG_POS(i,12)==15)\ + if(REG_POS(i,12)==15)\ {\ Status_Reg SPSR = cpu->SPSR;\ armcpu_switchMode(cpu, SPSR.bits.mode);\ @@ -2065,7 +2064,7 @@ static u32 FASTCALL OP_ORR_S_IMM_VAL(armcpu_t *cpu) cpu->CPSR.bits.C = c;\ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ - return a; + return a;\ static u32 FASTCALL OP_MOV_LSL_IMM(armcpu_t *cpu) { @@ -2742,8 +2741,8 @@ static u32 FASTCALL OP_LDRH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = (u32)MMU_readHWord(cpu->proc_ID, adr); + cpu->R[REG_POS(i,12)] = (u32)MMU_readHWord(cpu->proc_ID, adr); + cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -2752,9 +2751,8 @@ static u32 FASTCALL OP_LDRH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; - cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = (u32)MMU_readHWord(cpu->proc_ID, adr); - + cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -2763,8 +2761,8 @@ static u32 FASTCALL OP_LDRH_PRE_INDE_P_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = (u32)MMU_readHWord(cpu->proc_ID, adr); + cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -2773,8 +2771,8 @@ static u32 FASTCALL OP_LDRH_PRE_INDE_M_REG_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = (u32)MMU_readHWord(cpu->proc_ID, adr); + cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -2861,8 +2859,8 @@ static u32 FASTCALL OP_STRH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; - cpu->R[REG_POS(i,16)] = adr; - MMU_writeHWord(cpu->proc_ID, adr, (u16)cpu->R[REG_POS(i,12)]); + MMU_writeHWord(cpu->proc_ID, adr, (u16)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -3200,7 +3198,7 @@ static u32 FASTCALL OP_MSR_CPSR(armcpu_t *cpu) { if(BIT16(i)) { - armcpu_switchMode(cpu, (u8)(operand & 0x1F)); + armcpu_switchMode(cpu, operand & 0x1F); cpu->CPSR.val = (cpu->CPSR.val & 0xFFFFFF00) | (operand & 0xFF); } if(BIT17(i)) @@ -3245,7 +3243,7 @@ static u32 FASTCALL OP_MSR_CPSR_IMM_VAL(armcpu_t *cpu) { if(BIT16(i)) { - armcpu_switchMode(cpu, (u8)(shift_op & 0x1F)); + armcpu_switchMode(cpu, shift_op & 0x1F); cpu->CPSR.val = (cpu->CPSR.val & 0xFFFFFF00) | (shift_op & 0XFF); } if(BIT17(i)) @@ -3311,35 +3309,29 @@ static u32 FASTCALL OP_BLX_REG(armcpu_t *cpu) static u32 FASTCALL OP_B(armcpu_t *cpu) { - u8 condition = (u8)CONDITION(cpu->instruction); - - u32 off = SIGNEXTEND_24(cpu->instruction); - if(condition==0xF) - { - cpu->R[14] = cpu->next_instruction; - cpu->CPSR.bits.T = 1; - } - cpu->R[15] += (off<<2); - cpu->next_instruction = cpu->R[15]; - - return 3; + u32 off = SIGNEXTEND_24(cpu->instruction); + if(CONDITION(cpu->instruction)==0xF) + { + cpu->R[14] = cpu->next_instruction; + cpu->CPSR.bits.T = 1; + } + cpu->R[15] += (off<<2); + cpu->next_instruction = cpu->R[15]; + return 3; } static u32 FASTCALL OP_BL(armcpu_t *cpu) { - u8 condition = (u8)CONDITION(cpu->instruction); - - u32 off = SIGNEXTEND_24(cpu->instruction); - if(condition==0xF) - { - cpu->CPSR.bits.T = 1; - cpu->R[15] += 2; - } - cpu->R[14] = cpu->next_instruction; - cpu->R[15] += (off<<2); - cpu->next_instruction = cpu->R[15]; - - return 3; + u32 off = SIGNEXTEND_24(cpu->instruction); + if(CONDITION(cpu->instruction)==0xF) + { + cpu->CPSR.bits.T = 1; + cpu->R[15] += 2; + } + cpu->R[14] = cpu->next_instruction; + cpu->R[15] += (off<<2); + cpu->next_instruction = cpu->R[15]; + return 3; } //----------------CLZ------------------------------- @@ -3607,7 +3599,7 @@ static u32 FASTCALL OP_SMLAL_B_B(armcpu_t *cpu) LOG("SMLALBB %08X * %08X + %08X%08X = %08X%08X\r\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + (res + ((tmp<0)*0xFFFFFFFF))), (int)(u32) res); cpu->R[REG_POS(i,12)] = (u32) res; - cpu->R[REG_POS(i,16)] += (u32)(res + ((tmp<0)*0xFFFFFFFF)); + cpu->R[REG_POS(i,16)] += (res + ((tmp<0)*0xFFFFFFFF)); return 2; } @@ -3621,7 +3613,7 @@ static u32 FASTCALL OP_SMLAL_B_T(armcpu_t *cpu) LOG("SMLALBT %08X * %08X + %08X%08X = %08X%08X\r\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(u32) res); cpu->R[REG_POS(i,12)] = (u32) res; - cpu->R[REG_POS(i,16)] += (u32)(res + ((tmp<0)*0xFFFFFFFF)); + cpu->R[REG_POS(i,16)] += res + ((tmp<0)*0xFFFFFFFF); return 2; } @@ -3635,7 +3627,7 @@ static u32 FASTCALL OP_SMLAL_T_B(armcpu_t *cpu) LOG("SMLALTB %08X * %08X + %08X%08X = %08X%08X\r\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(u32) res); cpu->R[REG_POS(i,12)] = (u32) res; - cpu->R[REG_POS(i,16)] += (u32)(res + ((tmp<0)*0xFFFFFFFF)); + cpu->R[REG_POS(i,16)] += res + ((tmp<0)*0xFFFFFFFF); return 2; } @@ -3649,7 +3641,7 @@ static u32 FASTCALL OP_SMLAL_T_T(armcpu_t *cpu) LOG("SMLALTT %08X * %08X + %08X%08X = %08X%08X\r\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(u32) res); cpu->R[REG_POS(i,12)] = (u32) res; - cpu->R[REG_POS(i,16)] += (u32)(res + ((tmp<0)*0xFFFFFFFF)); + cpu->R[REG_POS(i,16)] += res + ((tmp<0)*0xFFFFFFFF); return 2; } @@ -3663,7 +3655,7 @@ static u32 FASTCALL OP_SMULW_B(armcpu_t *cpu) //LOG("SMULWB %08X * %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], ((tmp>>16)&0xFFFFFFFF); - cpu->R[REG_POS(i,16)] = (u32)((tmp>>16)&0xFFFFFFFF); + cpu->R[REG_POS(i,16)] = ((tmp>>16)&0xFFFFFFFF); return 2; } @@ -3675,7 +3667,7 @@ static u32 FASTCALL OP_SMULW_T(armcpu_t *cpu) //LOG("SMULWT %08X * %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], ((tmp>>16)&0xFFFFFFFF)); - cpu->R[REG_POS(i,16)] = (u32)((tmp>>16)&0xFFFFFFFF); + cpu->R[REG_POS(i,16)] = ((tmp>>16)&0xFFFFFFFF); return 2; } @@ -3691,7 +3683,7 @@ static u32 FASTCALL OP_SMLAW_B(armcpu_t *cpu) tmp = (tmp>>16); - cpu->R[REG_POS(i,16)] = (u32)(tmp + a); + cpu->R[REG_POS(i,16)] = tmp + a; if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)])) cpu->CPSR.bits.Q = 1; @@ -3708,7 +3700,7 @@ static u32 FASTCALL OP_SMLAW_T(armcpu_t *cpu) //LOG("SMLAWT %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, ((tmp>>16)&0xFFFFFFFF) + a); tmp = ((tmp>>16)&0xFFFFFFFF); - cpu->R[REG_POS(i,16)] = (u32)(tmp + a); + cpu->R[REG_POS(i,16)] = tmp + a; if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)])) cpu->CPSR.bits.Q = 1; @@ -3964,8 +3956,8 @@ static u32 FASTCALL OP_LDR_P_IMM_OFF_PREIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -3988,9 +3980,8 @@ static u32 FASTCALL OP_LDR_M_IMM_OFF_PREIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - + cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4014,9 +4005,8 @@ static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - + cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4040,9 +4030,8 @@ static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - + cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4066,9 +4055,8 @@ static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - + cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4092,9 +4080,8 @@ static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - + cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4118,9 +4105,8 @@ static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - + cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4144,9 +4130,8 @@ static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - + cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4170,9 +4155,8 @@ static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - + cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4196,8 +4180,8 @@ static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4220,8 +4204,8 @@ static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4247,7 +4231,7 @@ static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND2(armcpu_t *cpu) u32 old = armcpu_switchMode(cpu, USR); cpu->R[REG_POS(i,12)] = val; - armcpu_switchMode(cpu, (u8)old); + armcpu_switchMode(cpu, old); cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; @@ -4274,8 +4258,8 @@ static u32 FASTCALL OP_LDR_M_IMM_OFF_POSTIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4299,8 +4283,8 @@ static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr + shift_op; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4324,8 +4308,8 @@ static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr - shift_op; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4349,8 +4333,8 @@ static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr + shift_op; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4374,8 +4358,8 @@ static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr - shift_op; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4399,8 +4383,8 @@ static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr + shift_op; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4424,8 +4408,8 @@ static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } + cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4449,8 +4433,8 @@ static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr + shift_op; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4474,8 +4458,8 @@ static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr - shift_op; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4596,10 +4580,8 @@ static u32 FASTCALL OP_LDRB_P_IMM_OFF_PREIND(armcpu_t *cpu) u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; u32 val = MMU_readByte(cpu->proc_ID, adr); - - cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - + cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4609,9 +4591,8 @@ static u32 FASTCALL OP_LDRB_M_IMM_OFF_PREIND(armcpu_t *cpu) u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; u32 val = MMU_readByte(cpu->proc_ID, adr); - - cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4622,10 +4603,8 @@ static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu) LSL_IMM; u32 adr = cpu->R[REG_POS(i,16)] + shift_op; u32 val = MMU_readByte(cpu->proc_ID, adr); - - cpu->R[REG_POS(i,16)] = adr; cpu->R[REG_POS(i,12)] = val; - + cpu->R[REG_POS(i,16)] = adr; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4636,9 +4615,8 @@ static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu) LSL_IMM; u32 adr = cpu->R[REG_POS(i,16)] - shift_op; u32 val = MMU_readByte(cpu->proc_ID, adr); - + cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4649,8 +4627,8 @@ static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu) LSR_IMM; u32 adr = cpu->R[REG_POS(i,16)] + shift_op; u32 val = MMU_readByte(cpu->proc_ID, adr); + cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4661,8 +4639,8 @@ static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu) LSR_IMM; u32 adr = cpu->R[REG_POS(i,16)] - shift_op; u32 val = MMU_readByte(cpu->proc_ID, adr); + cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4673,8 +4651,8 @@ static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu) ASR_IMM; u32 adr = cpu->R[REG_POS(i,16)] + shift_op; u32 val = MMU_readByte(cpu->proc_ID, adr); + cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4685,8 +4663,8 @@ static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu) ASR_IMM; u32 adr = cpu->R[REG_POS(i,16)] - shift_op; u32 val = MMU_readByte(cpu->proc_ID, adr); + cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4697,8 +4675,8 @@ static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu) ROR_IMM; u32 adr = cpu->R[REG_POS(i,16)] + shift_op; u32 val = MMU_readByte(cpu->proc_ID, adr); + cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4709,8 +4687,8 @@ static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu) ROR_IMM; u32 adr = cpu->R[REG_POS(i,16)] - shift_op; u32 val = MMU_readByte(cpu->proc_ID, adr); + cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4720,8 +4698,8 @@ static u32 FASTCALL OP_LDRB_P_IMM_OFF_POSTIND(armcpu_t *cpu) u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; u32 val = MMU_readByte(cpu->proc_ID, adr); - cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4731,8 +4709,8 @@ static u32 FASTCALL OP_LDRB_M_IMM_OFF_POSTIND(armcpu_t *cpu) u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)]; u32 val = MMU_readByte(cpu->proc_ID, adr); - cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4743,8 +4721,8 @@ static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) LSL_IMM; u32 adr = cpu->R[REG_POS(i,16)]; u32 val = MMU_readByte(cpu->proc_ID, adr); - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr + shift_op; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4755,8 +4733,8 @@ static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) LSL_IMM; u32 adr = cpu->R[REG_POS(i,16)]; u32 val = MMU_readByte(cpu->proc_ID, adr); - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr - shift_op; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4767,8 +4745,8 @@ static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) LSR_IMM; u32 adr = cpu->R[REG_POS(i,16)]; u32 val = MMU_readByte(cpu->proc_ID, adr); - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr + shift_op; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4779,8 +4757,8 @@ static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) LSR_IMM; u32 adr = cpu->R[REG_POS(i,16)]; u32 val = MMU_readByte(cpu->proc_ID, adr); - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr - shift_op; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4791,8 +4769,8 @@ static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) ASR_IMM; u32 adr = cpu->R[REG_POS(i,16)]; u32 val = MMU_readByte(cpu->proc_ID, adr); - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr + shift_op; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4803,8 +4781,8 @@ static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) ASR_IMM; u32 adr = cpu->R[REG_POS(i,16)]; u32 val = MMU_readByte(cpu->proc_ID, adr); - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr - shift_op; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4815,8 +4793,8 @@ static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) ROR_IMM; u32 adr = cpu->R[REG_POS(i,16)]; u32 val = MMU_readByte(cpu->proc_ID, adr); - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr + shift_op; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4827,8 +4805,8 @@ static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) ROR_IMM; u32 adr = cpu->R[REG_POS(i,16)]; u32 val = MMU_readByte(cpu->proc_ID, adr); - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr - shift_op; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -4840,8 +4818,6 @@ static u32 FASTCALL OP_STR_P_IMM_OFF(armcpu_t *cpu) u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; MMU_writeWord(cpu->proc_ID, adr, cpu->R[REG_POS(i,12)]); - -// execute = false; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5256,7 +5232,7 @@ static u32 FASTCALL OP_STRB_P_IMM_OFF_PREIND(armcpu_t *cpu) { u32 i = cpu->instruction; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - MMU_writeByte(cpu->proc_ID, adr, (u8)cpu->R[REG_POS(i,12)]); + MMU_writeByte(cpu->proc_ID, adr, cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; @@ -5482,7 +5458,7 @@ static u32 FASTCALL OP_LDRBT_P_IMM_OFF_POSTIND(armcpu_t *cpu) cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5501,7 +5477,7 @@ static u32 FASTCALL OP_LDRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu) cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5521,7 +5497,7 @@ static u32 FASTCALL OP_LDRBT_P_REG_OFF_POSTIND(armcpu_t *cpu) cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr + cpu->R[REG_POS(i,0)]; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5541,7 +5517,7 @@ static u32 FASTCALL OP_LDRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr + shift_op; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5562,7 +5538,7 @@ static u32 FASTCALL OP_LDRBT_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr - shift_op; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5583,7 +5559,7 @@ static u32 FASTCALL OP_LDRBT_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr + shift_op; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5604,7 +5580,7 @@ static u32 FASTCALL OP_LDRBT_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr - shift_op; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5625,7 +5601,7 @@ static u32 FASTCALL OP_LDRBT_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr + shift_op; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5646,7 +5622,7 @@ static u32 FASTCALL OP_LDRBT_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr - shift_op; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5667,7 +5643,7 @@ static u32 FASTCALL OP_LDRBT_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr + shift_op; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5688,7 +5664,7 @@ static u32 FASTCALL OP_LDRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) cpu->R[REG_POS(i,12)] = val; cpu->R[REG_POS(i,16)] = adr - shift_op; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5708,7 +5684,7 @@ static u32 FASTCALL OP_STRBT_P_IMM_OFF_POSTIND(armcpu_t *cpu) MMU_writeByte(cpu->proc_ID, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5726,7 +5702,7 @@ static u32 FASTCALL OP_STRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu) MMU_writeByte(cpu->proc_ID, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5744,7 +5720,7 @@ static u32 FASTCALL OP_STRBT_P_REG_OFF_POSTIND(armcpu_t *cpu) MMU_writeByte(cpu->proc_ID, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + cpu->R[REG_POS(i,0)]; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5762,7 +5738,7 @@ static u32 FASTCALL OP_STRBT_M_REG_OFF_POSTIND(armcpu_t *cpu) MMU_writeByte(cpu->proc_ID, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - cpu->R[REG_POS(i,0)]; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5781,7 +5757,7 @@ static u32 FASTCALL OP_STRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) MMU_writeByte(cpu->proc_ID, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5800,7 +5776,7 @@ static u32 FASTCALL OP_STRBT_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu) MMU_writeByte(cpu->proc_ID, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5819,7 +5795,7 @@ static u32 FASTCALL OP_STRBT_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) MMU_writeByte(cpu->proc_ID, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5838,7 +5814,7 @@ static u32 FASTCALL OP_STRBT_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu) MMU_writeByte(cpu->proc_ID, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5857,7 +5833,7 @@ static u32 FASTCALL OP_STRBT_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) MMU_writeByte(cpu->proc_ID, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5876,7 +5852,7 @@ static u32 FASTCALL OP_STRBT_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu) MMU_writeByte(cpu->proc_ID, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5895,7 +5871,7 @@ static u32 FASTCALL OP_STRBT_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) MMU_writeByte(cpu->proc_ID, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr + shift_op; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -5914,7 +5890,7 @@ static u32 FASTCALL OP_STRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu) MMU_writeByte(cpu->proc_ID, adr, (u8)cpu->R[REG_POS(i,12)]); cpu->R[REG_POS(i,16)] = adr - shift_op; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; } @@ -6104,18 +6080,12 @@ static u32 FASTCALL OP_LDMDB(armcpu_t *cpu) static u32 FASTCALL OP_LDMIA_W(armcpu_t *cpu) { - u32 i = cpu->instruction, c = 0, count; + u32 i = cpu->instruction; + u32 c = 0; u32 start = cpu->R[REG_POS(i,16)]; - u32 bitList = i&0xFFFF; u32 * registres = cpu->R; u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID]; - - for (count = 1; count < 65536; count <<= 1) - { - if (count&bitList) - cpu->R[REG_POS(i,16)] += 4; - } OP_L_IA(0, start); OP_L_IA(1, start); @@ -6143,30 +6113,18 @@ static u32 FASTCALL OP_LDMIA_W(armcpu_t *cpu) cpu->next_instruction = registres[15]; } - /* - if (!BIT24(i)) - { - cpu->R[REG_POS(i,16)] = start; - } - */ - + cpu->R[REG_POS(i,16)] = start; return c + 2; } static u32 FASTCALL OP_LDMIB_W(armcpu_t *cpu) { - u32 i = cpu->instruction, c = 0, count; + u32 i = cpu->instruction; + u32 c = 0; u32 start = cpu->R[REG_POS(i,16)]; - u32 bitList = i&0xFFFF; u32 * registres = cpu->R; u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID]; - - for (count = 1; count < 65536; count <<= 1) - { - if (count&bitList) - cpu->R[REG_POS(i,16)] += 4; - } OP_L_IB(0, start); OP_L_IB(1, start); @@ -6194,31 +6152,18 @@ static u32 FASTCALL OP_LDMIB_W(armcpu_t *cpu) cpu->next_instruction = registres[15]; c += 2 + (c==0); } - - /* - if (!BIT24(i)) - { - cpu->R[REG_POS(i,16)] = start; - } - */ - + cpu->R[REG_POS(i,16)] = start; return c + 2; } static u32 FASTCALL OP_LDMDA_W(armcpu_t *cpu) { - u32 i = cpu->instruction, c = 0, count; + u32 i = cpu->instruction; + u32 c = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 * registres = cpu->R; u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID]; - - u32 bitList = i&0xFFFF; - for (count = 1; count < 65536; count <<= 1) - { - if (count&bitList) - cpu->R[REG_POS(i,16)] -= 4; - } if(BIT15(i)) { @@ -6246,24 +6191,18 @@ static u32 FASTCALL OP_LDMDA_W(armcpu_t *cpu) OP_L_DA(1, start); OP_L_DA(0, start); - //cpu->R[REG_POS(i,16)] = start; + cpu->R[REG_POS(i,16)] = start; return c + 2; } static u32 FASTCALL OP_LDMDB_W(armcpu_t *cpu) { - u32 i = cpu->instruction, c = 0, count; + u32 i = cpu->instruction; + u32 c = 0; u32 start = cpu->R[REG_POS(i,16)]; u32 * registres = cpu->R; u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID]; - - u32 bitList = i&0xFFFF; - for (count = 1; count < 65536; count <<= 1) - { - if (count&bitList) - cpu->R[REG_POS(i,16)] -= 4; - } if(BIT15(i)) { @@ -6291,7 +6230,7 @@ static u32 FASTCALL OP_LDMDB_W(armcpu_t *cpu) OP_L_DB(1, start); OP_L_DB(0, start); -// cpu->R[REG_POS(i,16)] = start; + cpu->R[REG_POS(i,16)] = start; return c + 2; } @@ -6342,7 +6281,7 @@ static u32 FASTCALL OP_LDMIA2(armcpu_t *cpu) } else { - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); } return c + 2; } @@ -6394,7 +6333,7 @@ static u32 FASTCALL OP_LDMIB2(armcpu_t *cpu) } else { - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); } return c + 2; } @@ -6446,7 +6385,7 @@ static u32 FASTCALL OP_LDMDA2(armcpu_t *cpu) if(BIT15(i)==0) { - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); } else { @@ -6504,7 +6443,7 @@ static u32 FASTCALL OP_LDMDB2(armcpu_t *cpu) if(BIT15(i)==0) { - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); } else { @@ -6523,7 +6462,7 @@ static u32 FASTCALL OP_LDMIA2_W(armcpu_t *cpu) u32 oldmode; u32 start = cpu->R[REG_POS(i,16)]; -// execute = FALSE; + execute = FALSE; if(BIT15(i)==0) { if(cpu->CPSR.bits.mode==USR) @@ -6553,7 +6492,7 @@ static u32 FASTCALL OP_LDMIA2_W(armcpu_t *cpu) if(BIT15(i)==0) { registres[REG_POS(i,16)] = start; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return c + 2; } @@ -6604,7 +6543,7 @@ static u32 FASTCALL OP_LDMIB2_W(armcpu_t *cpu) if(BIT15(i)==0) { - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); registres[REG_POS(i,16)] = start; return c + 2; @@ -6630,7 +6569,7 @@ static u32 FASTCALL OP_LDMDA2_W(armcpu_t *cpu) u32 oldmode; u32 start = cpu->R[REG_POS(i,16)]; -// execute = FALSE; + execute = FALSE; if(BIT15(i)==0) { if(cpu->CPSR.bits.mode==USR) @@ -6670,7 +6609,7 @@ static u32 FASTCALL OP_LDMDA2_W(armcpu_t *cpu) if(BIT15(i)==0) { - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return c + 2; } @@ -6687,7 +6626,7 @@ static u32 FASTCALL OP_LDMDB2_W(armcpu_t *cpu) u32 oldmode; u32 start = cpu->R[REG_POS(i,16)]; -// execute = FALSE; + execute = FALSE; if(BIT15(i)==0) { if(cpu->CPSR.bits.mode==USR) @@ -6728,7 +6667,7 @@ static u32 FASTCALL OP_LDMDB2_W(armcpu_t *cpu) if(BIT15(i)==0) { - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return c + 2; } @@ -6742,7 +6681,10 @@ static u32 FASTCALL OP_LDMDB2_W(armcpu_t *cpu) static u32 FASTCALL OP_STMIA(armcpu_t *cpu) { - u32 i = cpu->instruction, c = 0, b; + u32 i = cpu->instruction; + u32 c = 0; + u32 b; + u32 start = cpu->R[REG_POS(i,16)]; for(b=0; b<16; ++b) @@ -6759,7 +6701,10 @@ static u32 FASTCALL OP_STMIA(armcpu_t *cpu) static u32 FASTCALL OP_STMIB(armcpu_t *cpu) { - u32 i = cpu->instruction, c = 0, b; + u32 i = cpu->instruction; + u32 c = 0; + u32 b; + u32 start = cpu->R[REG_POS(i,16)]; for(b=0; b<16; ++b) @@ -6776,7 +6721,10 @@ static u32 FASTCALL OP_STMIB(armcpu_t *cpu) static u32 FASTCALL OP_STMDA(armcpu_t *cpu) { - u32 i = cpu->instruction, c = 0, b; + u32 i = cpu->instruction; + u32 c = 0; + u32 b; + u32 start = cpu->R[REG_POS(i,16)]; for(b=0; b<16; ++b) @@ -6793,7 +6741,10 @@ static u32 FASTCALL OP_STMDA(armcpu_t *cpu) static u32 FASTCALL OP_STMDB(armcpu_t *cpu) { - u32 i = cpu->instruction, c = 0, b; + u32 i = cpu->instruction; + u32 c = 0; + u32 b; + u32 start = cpu->R[REG_POS(i,16)]; for(b=0; b<16; ++b) @@ -6810,7 +6761,10 @@ static u32 FASTCALL OP_STMDB(armcpu_t *cpu) static u32 FASTCALL OP_STMIA_W(armcpu_t *cpu) { - u32 i = cpu->instruction, c = 0, b; + u32 i = cpu->instruction; + u32 c = 0; + u32 b; + u32 start = cpu->R[REG_POS(i,16)]; for(b=0; b<16; ++b) @@ -6829,7 +6783,10 @@ static u32 FASTCALL OP_STMIA_W(armcpu_t *cpu) static u32 FASTCALL OP_STMIB_W(armcpu_t *cpu) { - u32 i = cpu->instruction, c = 0, b; + u32 i = cpu->instruction; + u32 c = 0; + u32 b; + u32 start = cpu->R[REG_POS(i,16)]; for(b=0; b<16; ++b) @@ -6847,7 +6804,10 @@ static u32 FASTCALL OP_STMIB_W(armcpu_t *cpu) static u32 FASTCALL OP_STMDA_W(armcpu_t *cpu) { - u32 i = cpu->instruction, c = 0, b; + u32 i = cpu->instruction; + u32 c = 0; + u32 b; + u32 start = cpu->R[REG_POS(i,16)]; for(b=0; b<16; ++b) @@ -6866,7 +6826,9 @@ static u32 FASTCALL OP_STMDA_W(armcpu_t *cpu) static u32 FASTCALL OP_STMDB_W(armcpu_t *cpu) { - u32 i = cpu->instruction, c = 0, b; + u32 i = cpu->instruction; + u32 c = 0; + u32 b; u32 start = cpu->R[REG_POS(i,16)]; for(b=0; b<16; ++b) @@ -6884,16 +6846,19 @@ static u32 FASTCALL OP_STMDB_W(armcpu_t *cpu) } static u32 FASTCALL OP_STMIA2(armcpu_t *cpu) -{ +{ if(cpu->CPSR.bits.mode==USR) return 2; - u32 i = cpu->instruction, c = 0, b; + u32 i = cpu->instruction; u32 start = cpu->R[REG_POS(i,16)]; u32 oldmode = armcpu_switchMode(cpu, SYS); - - execute = FALSE; - + u32 b; + + execute = FALSE; + u32 c = 0; + + for(b=0; b<16; ++b) { if(BIT_N(i, b)) @@ -6904,7 +6869,7 @@ static u32 FASTCALL OP_STMIA2(armcpu_t *cpu) } } - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return c + 1; } @@ -6913,11 +6878,14 @@ static u32 FASTCALL OP_STMIB2(armcpu_t *cpu) if(cpu->CPSR.bits.mode==USR) return 2; - u32 i = cpu->instruction, c = 0, b; + u32 i = cpu->instruction; + u32 start = cpu->R[REG_POS(i,16)]; u32 oldmode = armcpu_switchMode(cpu, SYS); + u32 b; - execute = FALSE; + execute = FALSE; + u32 c = 0; for(b=0; b<16; ++b) { @@ -6929,7 +6897,7 @@ static u32 FASTCALL OP_STMIB2(armcpu_t *cpu) } } - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return c + 1; } @@ -6937,12 +6905,15 @@ static u32 FASTCALL OP_STMDA2(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; - - u32 i = cpu->instruction, c = 0, b; + u32 c = 0; + + u32 i = cpu->instruction; + u32 start = cpu->R[REG_POS(i,16)]; - u32 oldmode = armcpu_switchMode(cpu, SYS); + u32 b; execute = FALSE; + u32 oldmode = armcpu_switchMode(cpu, SYS); for(b=0; b<16; ++b) { @@ -6954,7 +6925,7 @@ static u32 FASTCALL OP_STMDA2(armcpu_t *cpu) } } - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return c + 1; } @@ -6962,7 +6933,11 @@ static u32 FASTCALL OP_STMDB2(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; - u32 i = cpu->instruction, c=0, b; + u32 c = 0; + u32 b; + + u32 i = cpu->instruction; + u32 start = cpu->R[REG_POS(i,16)]; u32 oldmode = armcpu_switchMode(cpu, SYS); @@ -6976,7 +6951,7 @@ static u32 FASTCALL OP_STMDB2(armcpu_t *cpu) } } - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return c + 1; } @@ -6984,11 +6959,13 @@ static u32 FASTCALL OP_STMIA2_W(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; + u32 c = 0; + u32 b; + + u32 i = cpu->instruction; - u32 i = cpu->instruction, c=0, b; u32 start = cpu->R[REG_POS(i,16)]; u32 oldmode = armcpu_switchMode(cpu, SYS); - execute = FALSE; for(b=0; b<16; ++b) @@ -7003,7 +6980,7 @@ static u32 FASTCALL OP_STMIA2_W(armcpu_t *cpu) cpu->R[REG_POS(i,16)] = start; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return c + 1; } @@ -7011,7 +6988,11 @@ static u32 FASTCALL OP_STMIB2_W(armcpu_t *cpu) { if(cpu->CPSR.bits.mode==USR) return 2; - u32 i = cpu->instruction, c=0, b; + u32 c = 0; + u32 b; + + u32 i = cpu->instruction; + u32 start = cpu->R[REG_POS(i,16)]; u32 oldmode = armcpu_switchMode(cpu, SYS); @@ -7024,7 +7005,7 @@ static u32 FASTCALL OP_STMIB2_W(armcpu_t *cpu) c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; } } - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); cpu->R[REG_POS(i,16)] = start; return c + 1; @@ -7035,11 +7016,15 @@ static u32 FASTCALL OP_STMDA2_W(armcpu_t *cpu) if(cpu->CPSR.bits.mode==USR) return 2; - u32 i = cpu->instruction, c = 0, b; + u32 i = cpu->instruction; + u32 start = cpu->R[REG_POS(i,16)]; u32 oldmode = armcpu_switchMode(cpu, SYS); execute = FALSE; + u32 c = 0; + u32 b; + for(b=0; b<16; ++b) { if(BIT_N(i, 15-b)) @@ -7052,7 +7037,7 @@ static u32 FASTCALL OP_STMDA2_W(armcpu_t *cpu) cpu->R[REG_POS(i,16)] = start; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return c + 1; } @@ -7061,11 +7046,14 @@ static u32 FASTCALL OP_STMDB2_W(armcpu_t *cpu) if(cpu->CPSR.bits.mode==USR) return 2; - u32 i = cpu->instruction, c = 0, b; + u32 i = cpu->instruction; u32 start = cpu->R[REG_POS(i,16)]; u32 oldmode = armcpu_switchMode(cpu, SYS); execute = FALSE; + + u32 c = 0; + u32 b; for(b=0; b<16; ++b) { @@ -7079,7 +7067,7 @@ static u32 FASTCALL OP_STMDB2_W(armcpu_t *cpu) cpu->R[REG_POS(i,16)] = start; - armcpu_switchMode(cpu, (u8)oldmode); + armcpu_switchMode(cpu, oldmode); return c + 1; } @@ -7212,7 +7200,7 @@ static u32 FASTCALL OP_MCR(armcpu_t *cpu) return 2; } - armcp15_moveARM2CP((armcp15_t*)cpu->coproc[cpnum], cpu->R[REG_POS(i, 12)], (u8)REG_POS(i, 16), (u8)REG_POS(i, 0), (u8)((i>>21)&7), (u8)((i>>5)&7)); + armcp15_moveARM2CP((armcp15_t*)cpu->coproc[cpnum], cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7); //cpu->coproc[cpnum]->moveARM2CP(cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7); return 2; } @@ -7230,7 +7218,7 @@ static u32 FASTCALL OP_MRC(armcpu_t *cpu) return 2; } - armcp15_moveCP2ARM((armcp15_t*)cpu->coproc[cpnum], &cpu->R[REG_POS(i, 12)], (u8)REG_POS(i, 16), (u8)REG_POS(i, 0), (u8)((i>>21)&7), (u8)((i>>5)&7)); + armcp15_moveCP2ARM((armcp15_t*)cpu->coproc[cpnum], &cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7); //cpu->coproc[cpnum]->moveCP2ARM(&cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7); return 4; } @@ -7257,17 +7245,30 @@ static u32 FASTCALL OP_CDP(armcpu_t *cpu) return 4; } -static u32 FASTCALL OP_LDRD(armcpu_t *cpu) -{ - u32 i = cpu->instruction; - LOG("Undefined instruction: %08X\n", i); - execute = FALSE; - return 1; -} - #define TYPE_RETOUR u32 #define PARAMETRES armcpu_t *cpu #define CALLTYPE FASTCALL #define NOM_TAB arm_instructions_set #include "instruction_tabdef.inc" + + + + + + + + + + + + + + + + + + + + +