diff --git a/desmume/AUTHORS b/AUTHORS similarity index 100% rename from desmume/AUTHORS rename to AUTHORS diff --git a/desmume/COPYING b/COPYING similarity index 100% rename from desmume/COPYING rename to COPYING diff --git a/desmume/ChangeLog b/ChangeLog similarity index 95% rename from desmume/ChangeLog rename to ChangeLog index 820cb9e6a..e800bc673 100644 --- a/desmume/ChangeLog +++ b/ChangeLog @@ -1,9 +1,3 @@ -0.9+ -Graphics: - bug: Fix some errors in rendering 512 tall BG [zeromus,CrazyMax] (still not fully resolved) - bug: 3d compositing integrated into GPU engine (more precision and speed in cases where no compositing needed) [luigi__] - bug: Add optional fragment shading pipeline (more precision) [luigi__] - 0.8 -> 0.9 There have been so many changes that this list can hardly be considered complete. For this release, we have formatted the list into a high level overview of big changes and bad bugs relative to the previous release. Hopefully what you're interested in. @@ -44,7 +38,6 @@ Graphics: . Move entire GE to core emu. . Move OpenGL renderer to emu core for optional use by platforms, removing ogl_collector. Now every platform shares the same 3d code. . Reorganize 3d code to defer rendering to after 3d vblank. Eliminates tearing, and texturing artifacts. [zeromus] - . Add optional fragment shading pipeline (more precision) [luigi__] . Move lighting model to software instead of using opengl's fixed function model [zeromus] . Render shadow volumes; toon shading and highlight table [zeromus, luigi__] . Added texture caching! big speed up. [CrazyMax] @@ -61,7 +54,6 @@ Graphics: bug: Add 3d layer h-scrolling [zeromus] bug: Added transparency and fixed material alpha support and alpha testing on the 3D core [shash] bug: Rewrite VRAM mapping control and rendering (more accurate) [CrazyMax,luigi__] - bug: convert colors to opengl better to prevent alpha=31 polys from being ever so slightly transparent [zeromus] enh: Add MMU->GPU signal for when vram mappings change to function as a texture cache invalidate signal [zeromus] enh: Make matrix 4x4 multiply routines use W-coordinate; carry w coord through pipeline [zeromus] diff --git a/desmume/INSTALL b/INSTALL similarity index 100% rename from desmume/INSTALL rename to INSTALL diff --git a/desmume/Makefile.am b/Makefile.am similarity index 100% rename from desmume/Makefile.am rename to Makefile.am diff --git a/desmume/NEWS b/NEWS similarity index 100% rename from desmume/NEWS rename to NEWS diff --git a/desmume/README b/README similarity index 100% rename from desmume/README rename to README diff --git a/desmume/README.LIN b/README.LIN similarity index 100% rename from desmume/README.LIN rename to README.LIN diff --git a/desmume/README.MAC b/README.MAC similarity index 100% rename from desmume/README.MAC rename to README.MAC diff --git a/desmume/README.TRANSLATION b/README.TRANSLATION similarity index 100% rename from desmume/README.TRANSLATION rename to README.TRANSLATION diff --git a/desmume/README.WIN b/README.WIN similarity index 100% rename from desmume/README.WIN rename to README.WIN diff --git a/desmume/TODO b/TODO similarity index 100% rename from desmume/TODO rename to TODO diff --git a/desmume/autogen.sh b/autogen.sh similarity index 100% rename from desmume/autogen.sh rename to autogen.sh diff --git a/desmume/autopackage/default.apspec.in b/autopackage/default.apspec.in similarity index 100% rename from desmume/autopackage/default.apspec.in rename to autopackage/default.apspec.in diff --git a/desmume/compile b/compile similarity index 100% rename from desmume/compile rename to compile diff --git a/desmume/configure.ac b/configure.ac similarity index 99% rename from desmume/configure.ac rename to configure.ac index 478eb78aa..54e27f538 100644 --- a/desmume/configure.ac +++ b/configure.ac @@ -1,7 +1,7 @@ dnl --- Package name is first argument to AC_INIT dnl --- Release version is second argument to AC_INIT -AC_INIT(desmume, [0.8]) +AC_INIT(desmume, [0.9]) dnl -- find target architecture for some os specific libraries AC_CANONICAL_TARGET diff --git a/desmume/po/ChangeLog b/po/ChangeLog similarity index 100% rename from desmume/po/ChangeLog rename to po/ChangeLog diff --git a/desmume/po/LINGUAS b/po/LINGUAS similarity index 100% rename from desmume/po/LINGUAS rename to po/LINGUAS diff --git a/desmume/po/PACKAGE b/po/PACKAGE similarity index 100% rename from desmume/po/PACKAGE rename to po/PACKAGE diff --git a/desmume/po/POTFILES.in b/po/POTFILES.in similarity index 100% rename from desmume/po/POTFILES.in rename to po/POTFILES.in diff --git a/desmume/po/desmume.pot b/po/desmume.pot similarity index 100% rename from desmume/po/desmume.pot rename to po/desmume.pot diff --git a/desmume/po/fr.po b/po/fr.po similarity index 100% rename from desmume/po/fr.po rename to po/fr.po diff --git a/desmume/po/pt_BR.po b/po/pt_BR.po similarity index 100% rename from desmume/po/pt_BR.po rename to po/pt_BR.po diff --git a/desmume/po/sv.po b/po/sv.po similarity index 100% rename from desmume/po/sv.po rename to po/sv.po diff --git a/desmume/src/ARM9.h b/src/ARM9.h similarity index 100% rename from desmume/src/ARM9.h rename to src/ARM9.h diff --git a/desmume/src/Disassembler.cpp b/src/Disassembler.cpp similarity index 100% rename from desmume/src/Disassembler.cpp rename to src/Disassembler.cpp diff --git a/desmume/src/Disassembler.h b/src/Disassembler.h similarity index 100% rename from desmume/src/Disassembler.h rename to src/Disassembler.h diff --git a/desmume/src/FIFO.cpp b/src/FIFO.cpp similarity index 100% rename from desmume/src/FIFO.cpp rename to src/FIFO.cpp diff --git a/desmume/src/FIFO.h b/src/FIFO.h similarity index 100% rename from desmume/src/FIFO.h rename to src/FIFO.h diff --git a/desmume/src/GPU.cpp b/src/GPU.cpp similarity index 81% rename from desmume/src/GPU.cpp rename to src/GPU.cpp index ac79cb092..29a514d10 100644 --- a/desmume/src/GPU.cpp +++ b/src/GPU.cpp @@ -139,51 +139,31 @@ NULL }; //static BOOL setFinalColorDirect (const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); -static BOOL setFinalBGColorSpecialNone (GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); -static BOOL setFinalBGColorSpecialBlend (GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); -static BOOL setFinalBGColorSpecialIncrease (GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); -static BOOL setFinalBGColorSpecialDecrease (GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); +static BOOL setFinalColorSpecialNone (const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); +static BOOL setFinalColorSpecialBlend (const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); +static BOOL setFinalColorSpecialIncrease (const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); +static BOOL setFinalColorSpecialDecrease (const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); //static BOOL setFinalColorDirectWnd (const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); -static BOOL setFinalBGColorSpecialNoneWnd (GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); -static BOOL setFinalBGColorSpecialBlendWnd (GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); -static BOOL setFinalBGColorSpecialIncreaseWnd (GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); -static BOOL setFinalBGColorSpecialDecreaseWnd (GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); - -static BOOL setFinal3DColorSpecialNone (GPU *gpu, u32 passing, u8 *dst, u16 color, u8 alpha, u16 x, u16 y); -static BOOL setFinal3DColorSpecialBlend (GPU *gpu, u32 passing, u8 *dst, u16 color, u8 alpha, u16 x, u16 y); -static BOOL setFinal3DColorSpecialIncrease (GPU *gpu, u32 passing, u8 *dst, u16 color, u8 alpha, u16 x, u16 y); -static BOOL setFinal3DColorSpecialDecrease (GPU *gpu, u32 passing, u8 *dst, u16 color, u8 alpha, u16 x, u16 y); -static BOOL setFinal3DColorSpecialNoneWnd (GPU *gpu, u32 passing, u8 *dst, u16 color, u8 alpha, u16 x, u16 y); -static BOOL setFinal3DColorSpecialBlendWnd (GPU *gpu, u32 passing, u8 *dst, u16 color, u8 alpha, u16 x, u16 y); -static BOOL setFinal3DColorSpecialIncreaseWnd (GPU *gpu, u32 passing, u8 *dst, u16 color, u8 alpha, u16 x, u16 y); -static BOOL setFinal3DColorSpecialDecreaseWnd (GPU *gpu, u32 passing, u8 *dst, u16 color, u8 alpha, u16 x, u16 y); +static BOOL setFinalColorSpecialNoneWnd (const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); +static BOOL setFinalColorSpecialBlendWnd (const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); +static BOOL setFinalColorSpecialIncreaseWnd (const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); +static BOOL setFinalColorSpecialDecreaseWnd (const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); -typedef BOOL (*FinalBGColFunct)(GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); -typedef BOOL (*Final3DColFunct)(GPU *gpu, u32 passing, u8 *dst, u16 color, u8 alpha, u16 x, u16 y); +typedef BOOL (*FinalColFunct)(const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); -FinalBGColFunct pixelBlittersBG[8] = { //setFinalColorDirect, - setFinalBGColorSpecialNone, - setFinalBGColorSpecialBlend, - setFinalBGColorSpecialIncrease, - setFinalBGColorSpecialDecrease, +FinalColFunct pixelBlitters[8] = { //setFinalColorDirect, + setFinalColorSpecialNone, + setFinalColorSpecialBlend, + setFinalColorSpecialIncrease, + setFinalColorSpecialDecrease, //setFinalColorDirectWnd, - setFinalBGColorSpecialNoneWnd, - setFinalBGColorSpecialBlendWnd, - setFinalBGColorSpecialIncreaseWnd, - setFinalBGColorSpecialDecreaseWnd}; - -Final3DColFunct pixelBlitters3D[8] = { - setFinal3DColorSpecialNone, - setFinal3DColorSpecialBlend, - setFinal3DColorSpecialIncrease, - setFinal3DColorSpecialDecrease, - setFinal3DColorSpecialNoneWnd, - setFinal3DColorSpecialBlendWnd, - setFinal3DColorSpecialIncreaseWnd, - setFinal3DColorSpecialDecreaseWnd}; + setFinalColorSpecialNoneWnd, + setFinalColorSpecialBlendWnd, + setFinalColorSpecialIncreaseWnd, + setFinalColorSpecialDecreaseWnd}; u16 fadeInColors[17][0x8000]; u16 fadeOutColors[17][0x8000]; @@ -192,73 +172,49 @@ u16 fadeOutColors[17][0x8000]; // INITIALIZATION /*****************************************************************************/ -static void GPU_InitFadeColors() -{ - /* - NOTE: gbatek (in the reference above) seems to expect 6bit values - per component, but as desmume works with 5bit per component, - we use 31 as top, instead of 63. Testing it on a few games, - using 63 seems to give severe color wraping, and 31 works - nicely, so for now we'll just that, until proven wrong. - - i have seen pics of pokemon ranger getting white with 31, with 63 it is nice. - it could be pb of alpha or blending or... - - MightyMax> created a test NDS to check how the brightness values work, - and 31 seems to be correct. FactorEx is a override for max brighten/darken - See: http://mightymax.org/gfx_test_brightness.nds - The Pokemon Problem could be a problem with 8/32 bit writes not recognized yet, - i'll add that so you can check back. - - */ - - for(int i = 0; i <= 16; i++) - { - for(int j = 0x8000; j < 0x10000; j++) - { - COLOR cur; - - cur.val = j; - cur.bits.red = (cur.bits.red + ((31 - cur.bits.red) * i / 16)); - cur.bits.green = (cur.bits.green + ((31 - cur.bits.green) * i / 16)); - cur.bits.blue = (cur.bits.blue + ((31 - cur.bits.blue) * i / 16)); - fadeInColors[i][j & 0x7FFF] = cur.val; - - cur.val = j; - cur.bits.red = (cur.bits.red - (cur.bits.red * i / 16)); - cur.bits.green = (cur.bits.green - (cur.bits.green * i / 16)); - cur.bits.blue = (cur.bits.blue - (cur.bits.blue * i / 16)); - fadeOutColors[i][j & 0x7FFF] = cur.val; - } - } -} - - - GPU * GPU_Init(u8 l) { - GPU * g; + int i, j; - if ((g = (GPU *) malloc(sizeof(GPU))) == NULL) - return NULL; + GPU * g; - GPU_Reset(g, l); - GPU_InitFadeColors(); + if ((g = (GPU *) malloc(sizeof(GPU))) == NULL) + return NULL; - g->setFinalColorBck = setFinalBGColorSpecialNone; - g->setFinalColorSpr = setFinalBGColorSpecialNone; - g->setFinalColor3D = setFinal3DColorSpecialNone; + GPU_Reset(g, l); - return g; + for(i = 0; i <= 16; i++) + { + for(j = 0x8000; j < 0x10000; j++) + { + COLOR cur; + + cur.val = j; + cur.bits.red = (cur.bits.red + ((31 - cur.bits.red) * i / 16)); + cur.bits.green = (cur.bits.green + ((31 - cur.bits.green) * i / 16)); + cur.bits.blue = (cur.bits.blue + ((31 - cur.bits.blue) * i / 16)); + fadeInColors[i][j & 0x7FFF] = cur.val; + + cur.val = j; + cur.bits.red = (cur.bits.red - (cur.bits.red * i / 16)); + cur.bits.green = (cur.bits.green - (cur.bits.green * i / 16)); + cur.bits.blue = (cur.bits.blue - (cur.bits.blue * i / 16)); + fadeOutColors[i][j & 0x7FFF] = cur.val; + } + } + + g->setFinalColorBck = setFinalColorSpecialNone; + g->setFinalColorSpr = setFinalColorSpecialNone; + + return g; } void GPU_Reset(GPU *g, u8 l) { memset(g, 0, sizeof(GPU)); - g->setFinalColorBck = setFinalBGColorSpecialNone; - g->setFinalColorSpr = setFinalBGColorSpecialNone; - g->setFinalColor3D = setFinal3DColorSpecialNone; + g->setFinalColorBck = setFinalColorSpecialNone; + g->setFinalColorSpr = setFinalColorSpecialNone; g->core = l; g->BGSize[0][0] = g->BGSize[1][0] = g->BGSize[2][0] = g->BGSize[3][0] = 256; g->BGSize[0][1] = g->BGSize[1][1] = g->BGSize[2][1] = g->BGSize[3][1] = 256; @@ -363,9 +319,8 @@ void SetupFinalPixelBlitter (GPU *gpu) u8 windowUsed = (gpu->WIN0_ENABLED | gpu->WIN1_ENABLED | gpu->WINOBJ_ENABLED); u8 blendMode = (gpu->BLDCNT >> 6)&3; - gpu->setFinalColorSpr = pixelBlittersBG[windowUsed*4 + blendMode]; - gpu->setFinalColorBck = pixelBlittersBG[windowUsed*4 + blendMode]; - gpu->setFinalColor3D = pixelBlitters3D[windowUsed*4 + blendMode]; + gpu->setFinalColorSpr = pixelBlitters[windowUsed*4 + blendMode]; + gpu->setFinalColorBck = pixelBlitters[windowUsed*4 + blendMode]; } /* Sets up LCD control variables for Display Engines A and B for quick reading */ @@ -580,10 +535,10 @@ static INLINE void renderline_checkWindows(const GPU *gpu, u8 bgnum, u16 x, u16 } /*****************************************************************************/ -// PIXEL RENDERING - BGS +// PIXEL RENDERING /*****************************************************************************/ -static BOOL setFinalBGColorSpecialNone (GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y) +static BOOL setFinalColorSpecialNone (const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y) { //sprwin test hack - use this code //BOOL windowDraw = TRUE, windowEffect = TRUE; @@ -592,11 +547,10 @@ static BOOL setFinalBGColorSpecialNone (GPU *gpu, u32 passing, u8 bgnum, u8 *dst //return 1; T2WriteWord(dst, passing, color); - gpu->bgPixels[x] = bgnum; return 1; } -static BOOL setFinalBGColorSpecialBlend (GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y) +static BOOL setFinalColorSpecialBlend (const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y) { if ((gpu->BLDCNT >> bgnum)&1 && gpu->BLDALPHA_EVA) { @@ -627,18 +581,16 @@ static BOOL setFinalBGColorSpecialBlend (GPU *gpu, u32 passing, u8 bgnum, u8 *ds color = (sourceR & 0x1F) | ((sourceG & 0x1F) << 5) | ((sourceB & 0x1F) << 10) | 0x8000 ; T2WriteWord(dst, passing, color); - gpu->bgPixels[x] = bgnum; } else { T2WriteWord(dst, passing, color); - gpu->bgPixels[x] = bgnum; } return 1; } -static BOOL setFinalBGColorSpecialIncrease (GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y) +static BOOL setFinalColorSpecialIncrease (const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y) { if ((gpu->BLDCNT >> bgnum)&1) // the bg to draw has a special color effect { @@ -658,18 +610,16 @@ static BOOL setFinalBGColorSpecialIncrease (GPU *gpu, u32 passing, u8 bgnum, u8 } T2WriteWord(dst, passing, color) ; - gpu->bgPixels[x] = bgnum; } else { T2WriteWord(dst, passing, color); - gpu->bgPixels[x] = bgnum; } return 1; } -static BOOL setFinalBGColorSpecialDecrease (GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y) +static BOOL setFinalColorSpecialDecrease (const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y) { if ((gpu->BLDCNT >> bgnum)&1) // the bg to draw has a special color effect { @@ -688,18 +638,16 @@ static BOOL setFinalBGColorSpecialDecrease (GPU *gpu, u32 passing, u8 bgnum, u8 color = (fadeOutColors[gpu->BLDY_EVY][color&0x7FFF] | 0x8000); } T2WriteWord(dst, passing, color) ; - gpu->bgPixels[x] = bgnum; } else { T2WriteWord(dst, passing, color); - gpu->bgPixels[x] = bgnum; } return 1; } -static BOOL setFinalBGColorSpecialNoneWnd (GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y) +static BOOL setFinalColorSpecialNoneWnd (const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y) { BOOL windowDraw = TRUE, windowEffect = TRUE; @@ -708,21 +656,17 @@ static BOOL setFinalBGColorSpecialNoneWnd (GPU *gpu, u32 passing, u8 bgnum, u8 * if (((gpu->BLDCNT >> bgnum)&1) && windowEffect) // the bg to draw has a special color effect { T2WriteWord(dst, passing, color); - gpu->bgPixels[x] = bgnum; } else { if ((windowEffect && (gpu->BLDCNT & (0x100 << bgnum))) || windowDraw) - { T2WriteWord(dst, passing, color); - gpu->bgPixels[x] = bgnum; - } } return windowDraw; } -static BOOL setFinalBGColorSpecialBlendWnd (GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y) +static BOOL setFinalColorSpecialBlendWnd (const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y) { BOOL windowDraw = TRUE, windowEffect = TRUE; @@ -758,21 +702,17 @@ static BOOL setFinalBGColorSpecialBlendWnd (GPU *gpu, u32 passing, u8 bgnum, u8 color = (sourceR & 0x1F) | ((sourceG & 0x1F) << 5) | ((sourceB & 0x1F) << 10) | 0x8000 ; T2WriteWord(dst, passing, color); - gpu->bgPixels[x] = bgnum; } else { if ((windowEffect && (gpu->BLDCNT & (0x100 << bgnum))) || windowDraw) - { T2WriteWord(dst, passing, color); - gpu->bgPixels[x] = bgnum; - } } return windowDraw; } -static BOOL setFinalBGColorSpecialIncreaseWnd (GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y) +static BOOL setFinalColorSpecialIncreaseWnd (const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y) { BOOL windowDraw = TRUE, windowEffect = TRUE; @@ -796,21 +736,17 @@ static BOOL setFinalBGColorSpecialIncreaseWnd (GPU *gpu, u32 passing, u8 bgnum, } T2WriteWord(dst, passing, color) ; - gpu->bgPixels[x] = bgnum; } else { if ((windowEffect && (gpu->BLDCNT & (0x100 << bgnum))) || windowDraw) - { T2WriteWord(dst, passing, color); - gpu->bgPixels[x] = bgnum; - } } return windowDraw; } -static BOOL setFinalBGColorSpecialDecreaseWnd (GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y) +static BOOL setFinalColorSpecialDecreaseWnd (const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y) { BOOL windowDraw = TRUE, windowEffect = TRUE; @@ -833,241 +769,11 @@ static BOOL setFinalBGColorSpecialDecreaseWnd (GPU *gpu, u32 passing, u8 bgnum, color = (fadeOutColors[gpu->BLDY_EVY][color&0x7FFF] | 0x8000); } T2WriteWord(dst, passing, color) ; - gpu->bgPixels[x] = bgnum; } else { if ((windowEffect && (gpu->BLDCNT & (0x100 << bgnum))) || windowDraw) - { T2WriteWord(dst, passing, color); - gpu->bgPixels[x] = bgnum; - } - } - - return windowDraw; -} - -/*****************************************************************************/ -// PIXEL RENDERING - 3D -/*****************************************************************************/ - -static BOOL setFinal3DColorSpecialNone(GPU *gpu, u32 passing, u8 *dst, u16 color, u8 alpha, u16 x, u16 y) -{ - T2WriteWord(dst, passing, (color | 0x8000)); - return 1; -} - -static BOOL setFinal3DColorSpecialBlend(GPU *gpu, u32 passing, u8 *dst, u16 color, u8 alpha, u16 x, u16 y) -{ - /* We can blend if the 3D layer is selected as 1st target, */ - /* but also if the 3D layer has the highest prio. */ - if((gpu->BLDCNT & 0x1) || (gpu->dispx_st->dispx_BGxCNT[0].bits.Priority == 0)) - { - int bg_under = gpu->bgPixels[x]; - u16 final = color; - - /* If the layer we are drawing on is selected as 2nd source, we can blend */ - if(gpu->BLDCNT & (1 << (8 + bg_under))) - { - /* Test for easy cases like alpha = min or max */ - if(alpha == 16) - { - final = color; - } - else if(alpha == 0) - { - final = T2ReadWord(dst, passing); - } - else - { - COLOR c1, c2, cfinal; - - c1.val = color; - c2.val = T2ReadWord(dst, passing); - - cfinal.bits.red = ((c1.bits.red * alpha / 16) + (c2.bits.red * (16 - alpha) / 16)); - cfinal.bits.green = ((c1.bits.green * alpha / 16) + (c2.bits.green * (16 - alpha) / 16)); - cfinal.bits.blue = ((c1.bits.blue * alpha / 16) + (c2.bits.blue * (16 - alpha) / 16)); - - final = cfinal.val; - } - } - - T2WriteWord(dst, passing, (final | 0x8000)); - gpu->bgPixels[x] = 0; - } - else - { - T2WriteWord(dst, passing, (color | 0x8000)); - gpu->bgPixels[x] = 0; - } - - return 1; -} - -static BOOL setFinal3DColorSpecialIncrease(GPU *gpu, u32 passing, u8 *dst, u16 color, u8 alpha, u16 x, u16 y) -{ - if(gpu->BLDCNT & 0x1) - { - if (gpu->BLDY_EVY != 0x0) - { - color = fadeInColors[gpu->BLDY_EVY][color&0x7FFF]; - } - - T2WriteWord(dst, passing, (color | 0x8000)); - gpu->bgPixels[x] = 0; - } - else - { - T2WriteWord(dst, passing, (color | 0x8000)); - gpu->bgPixels[x] = 0; - } - - return 1; -} - -static BOOL setFinal3DColorSpecialDecrease(GPU *gpu, u32 passing, u8 *dst, u16 color, u8 alpha, u16 x, u16 y) -{ - if(gpu->BLDCNT & 0x1) - { - if (gpu->BLDY_EVY != 0x0) - { - color = fadeOutColors[gpu->BLDY_EVY][color&0x7FFF]; - } - - T2WriteWord(dst, passing, (color | 0x8000)); - gpu->bgPixels[x] = 0; - } - else - { - T2WriteWord(dst, passing, (color | 0x8000)); - gpu->bgPixels[x] = 0; - } - - return 1; -} - -static BOOL setFinal3DColorSpecialNoneWnd(GPU *gpu, u32 passing, u8 *dst, u16 color, u8 alpha, u16 x, u16 y) -{ - BOOL windowDraw = TRUE, windowEffect = TRUE; - - renderline_checkWindows(gpu, 0, x, y, &windowDraw, &windowEffect); - - if(windowDraw) - { - T2WriteWord(dst, passing, (color | 0x8000)); - gpu->bgPixels[x] = 0; - } - - return windowDraw; -} - -static BOOL setFinal3DColorSpecialBlendWnd(GPU *gpu, u32 passing, u8 *dst, u16 color, u8 alpha, u16 x, u16 y) -{ - BOOL windowDraw = TRUE, windowEffect = TRUE; - - renderline_checkWindows(gpu, 0, x, y, &windowDraw, &windowEffect); - - if(windowDraw) - { - /* We can blend if the 3D layer is selected as 1st target, */ - /* but also if the 3D layer has the highest prio. */ - if(((gpu->BLDCNT & 0x1) && windowEffect) || (gpu->dispx_st->dispx_BGxCNT[0].bits.Priority == 0)) - { - int bg_under = gpu->bgPixels[x]; - u16 final = color; - - /* If the layer we are drawing on is selected as 2nd source, we can blend */ - if(gpu->BLDCNT & (1 << (8 + bg_under))) - { - /* Test for easy cases like alpha = min or max */ - if(alpha == 16) - { - final = color; - } - else if(alpha == 0) - { - final = T2ReadWord(dst, passing); - } - else - { - COLOR c1, c2, cfinal; - - c1.val = color; - c2.val = T2ReadWord(dst, passing); - - cfinal.bits.red = ((c1.bits.red * alpha / 16) + (c2.bits.red * (16 - alpha) / 16)); - cfinal.bits.green = ((c1.bits.green * alpha / 16) + (c2.bits.green * (16 - alpha) / 16)); - cfinal.bits.blue = ((c1.bits.blue * alpha / 16) + (c2.bits.blue * (16 - alpha) / 16)); - - final = cfinal.val; - } - } - - T2WriteWord(dst, passing, (final | 0x8000)); - gpu->bgPixels[x] = 0; - } - else - { - T2WriteWord(dst, passing, (color | 0x8000)); - gpu->bgPixels[x] = 0; - } - } - - return windowDraw; -} - -static BOOL setFinal3DColorSpecialIncreaseWnd(GPU *gpu, u32 passing, u8 *dst, u16 color, u8 alpha, u16 x, u16 y) -{ - BOOL windowDraw = TRUE, windowEffect = TRUE; - - renderline_checkWindows(gpu, 0, x, y, &windowDraw, &windowEffect); - - if(windowDraw) - { - if((gpu->BLDCNT & 0x1) && windowEffect) - { - if (gpu->BLDY_EVY != 0x0) - { - color = fadeInColors[gpu->BLDY_EVY][color&0x7FFF]; - } - - T2WriteWord(dst, passing, (color | 0x8000)); - gpu->bgPixels[x] = 0; - } - else - { - T2WriteWord(dst, passing, (color | 0x8000)); - gpu->bgPixels[x] = 0; - } - } - - return windowDraw; -} - -static BOOL setFinal3DColorSpecialDecreaseWnd(GPU *gpu, u32 passing, u8 *dst, u16 color, u8 alpha, u16 x, u16 y) -{ - BOOL windowDraw = TRUE, windowEffect = TRUE; - - renderline_checkWindows(gpu, 0, x, y, &windowDraw, &windowEffect); - - if(windowDraw) - { - if((gpu->BLDCNT & 0x1) && windowEffect) - { - if (gpu->BLDY_EVY != 0x0) - { - color = fadeOutColors[gpu->BLDY_EVY][color&0x7FFF]; - } - - T2WriteWord(dst, passing, (color | 0x8000)); - gpu->bgPixels[x] = 0; - } - else - { - T2WriteWord(dst, passing, (color | 0x8000)); - gpu->bgPixels[x] = 0; - } } return windowDraw; @@ -1077,7 +783,7 @@ static BOOL setFinal3DColorSpecialDecreaseWnd(GPU *gpu, u32 passing, u8 *dst, u1 // BACKGROUND RENDERING -TEXT- /*****************************************************************************/ // render a text background to the combined pixelbuffer -INLINE void renderline_textBG(GPU * gpu, u8 num, u8 * dst, u32 Y, u16 XBG, u16 YBG, u16 LG) +INLINE void renderline_textBG(const GPU * gpu, u8 num, u8 * dst, u32 Y, u16 XBG, u16 YBG, u16 LG) { struct _BGxCNT * bgCnt = &(gpu->dispx_st)->dispx_BGxCNT[num].bits; struct _DISPCNT * dispCnt = &(gpu->dispx_st)->dispx_DISPCNT.bits; @@ -1100,18 +806,12 @@ INLINE void renderline_textBG(GPU * gpu, u8 num, u8 * dst, u32 Y, u16 XBG, u16 Y TILEENTRY tileentry; - //zero 30-dec-2008 - if you mask by 31 here, you lose the ability to correctly map the bottom half of 512-tall BG. - //the masking to keep it to a reasonable value was already done when tmp was calculated - // this is broke some games - //map = (u8 *)MMU_RenderMapToLCD(gpu->BG_map_ram[num] + (tmp) * 64); - - u32 tmp_map = gpu->BG_map_ram[num] + (tmp&31) * 64; - if(tmp>31) - tmp_map+= ADDRESS_STEP_512B << bgCnt->ScreenSize ; - - map = (u8 *)MMU_RenderMapToLCD(tmp_map); - if(!map) return; // no map + map = (u8 *)MMU_RenderMapToLCD(gpu->BG_map_ram[num] + (tmp&31) * 64); + if (!map) return; + if(tmp>31) + map+= ADDRESS_STEP_512B << bgCnt->ScreenSize ; + tile = (u8*) MMU_RenderMapToLCD(gpu->BG_tile_ram[num]); if(!tile) return; // no tiles @@ -1257,7 +957,6 @@ INLINE void renderline_textBG(GPU * gpu, u8 num, u8 * dst, u32 Y, u16 XBG, u16 Y } yoff = ((YBG&7)<<3); - xfin = 8 - (xoff&7); for(x = 0; x < LG; xfin = std::min(x+8, LG)) { @@ -1489,7 +1188,7 @@ void lineExtRot(GPU * gpu, u8 num, u16 l, u8 * DST) 256); } -void textBG(GPU * gpu, u8 num, u8 * DST) +void textBG(const GPU * gpu, u8 num, u8 * DST) { u32 i; for(i = 0; i < gpu->BGSize[num][1]; ++i) @@ -2416,10 +2115,52 @@ void GPU_set_DISPCAPCNT(u32 val) gpu->dispCapCnt.capSrc, gpu->dispCapCnt.dst - ARM9Mem.ARM9_LCD, gpu->dispCapCnt.src - ARM9Mem.ARM9_LCD, gpu->dispCapCnt.srcA, gpu->dispCapCnt.srcB);*/ } + +// trade off for speed is 1MB +u16 bright_more_colors[16][0x8000]; +u16 bright_less_colors[16][0x8000]; +BOOL bright_init=FALSE; + +// comment this if want to use formulas instead // #define BRIGHT_TABLES +#ifdef BRIGHT_TABLES +static void calc_bright_colors() { + int base = 31 ; + int factor; + u16 red, green, blue; + COLOR color_more, color_less, color_ref; -static void GPU_ligne_layer(NDS_Screen * screen, u16 l) +#define FORMULA_MORE(x) x + ((base-x)*factor)/16 +#define FORMULA_LESS(x) x - (x*factor)/16 + + if (bright_init) return; + for (factor=0; factor<16; factor++) + for (red =0; red <32; red++) { + color_ref.bits.red = red; + color_more.bits.red = FORMULA_MORE(red); + color_less.bits.red = FORMULA_LESS(red); + for (green=0; green<32; green++) { + color_ref.bits.green = green; + color_more.bits.green = FORMULA_MORE(green); + color_less.bits.green = FORMULA_LESS(green); + for (blue =0; blue <32; blue++) { + color_ref.bits.blue = blue; + color_more.bits.blue = FORMULA_MORE(blue); + color_less.bits.blue = FORMULA_LESS(blue); + bright_more_colors[factor][color_ref.bitx.bgr] = color_more.val; + bright_less_colors[factor][color_ref.bitx.bgr] = color_less.val; + } + } + } + bright_init=TRUE; + +#undef FORMULA_MORE +#undef FORMULA_LESS +} +#endif + +static INLINE void GPU_ligne_layer(NDS_Screen * screen, u16 l) { GPU * gpu = screen->gpu; struct _DISPCNT * dispCnt = &(gpu->dispx_st)->dispx_DISPCNT.bits; @@ -2451,9 +2192,6 @@ static void GPU_ligne_layer(NDS_Screen * screen, u16 l) for(int i = 0; i< 256; ++i) T2WriteWord(dst, i << 1, c); - /* reset them to backdrop */ - memset(gpu->bgPixels, 5, 256); - if (!gpu->LayersEnable[0] && !gpu->LayersEnable[1] && !gpu->LayersEnable[2] && !gpu->LayersEnable[3] && !gpu->LayersEnable[4]) return; @@ -2507,11 +2245,6 @@ static void GPU_ligne_layer(NDS_Screen * screen, u16 l) { if (i16 == 0 && dispCnt->BG0_3D) { - u16 line3Dcolor[256]; - u8 line3Dalpha[256]; - - memset(line3Dcolor, 0, sizeof(line3Dcolor)); - memset(line3Dalpha, 0, sizeof(line3Dalpha)); //determine the 3d range to grab BGxOFS * bgofs = &gpu->dispx_st->dispx_BGxOFS[i16]; s16 hofs = (s16)T1ReadWord((u8 *)&bgofs->BGxHOFS, 0); @@ -2520,13 +2253,7 @@ static void GPU_ligne_layer(NDS_Screen * screen, u16 l) else if(hofs<0) { start = -hofs; end=255; ofs=0; } else { start = 0; end=255-hofs; ofs=hofs; } - //gpu3D->NDS_3D_GetLine (l, start, end, (u16*)dst+ofs); - gpu3D->NDS_3D_GetLine(l, start, end, line3Dcolor + ofs, line3Dalpha + ofs); - - for(int k = start; k <= end; k++) - if(line3Dcolor[k] & 0x8000) - gpu->setFinalColor3D(gpu, (k << 1), dst, line3Dcolor[k], line3Dalpha[k], k, l); - + gpu3D->NDS_3D_GetLine (l, start, end, (u16*)dst+ofs); continue; } } @@ -2547,9 +2274,10 @@ static void GPU_ligne_layer(NDS_Screen * screen, u16 l) } // TODO: capture emulated not fully -static void GPU_ligne_DispCapture(u16 l) +static INLINE void GPU_ligne_DispCapture(u16 l) { GPU * gpu = MainScreen.gpu; + struct _DISPCNT * dispCnt = &(gpu->dispx_st)->dispx_DISPCNT.bits; if (l == 0) { @@ -2685,11 +2413,15 @@ static void GPU_ligne_DispCapture(u16 l) static INLINE void GPU_ligne_MasterBrightness(NDS_Screen * screen, u16 l) { GPU * gpu = screen->gpu; - u8 * dst = GPU_screen + (screen->offset + l) * 512; u16 i16; - if (!gpu->MasterBrightFactor) return; +#ifndef HAVE_LIBGDKGLEXT_X11_1_0 +// damdoum : +// brightness done with opengl +// test are ok (gfx_test_brightness) +// now, if we are going to support 3D, this becomes dead code +// because it is obvious we'll use openGL / mesa3D #ifdef BRIGHT_TABLES calc_bright_colors(); @@ -2709,11 +2441,36 @@ static INLINE void GPU_ligne_MasterBrightness(NDS_Screen * screen, u16 l) // Bright up case 1: { - // when we wont do anything, we dont need to loop +#if 0 + COLOR dstColor; + unsigned int masterBrightFactor = gpu->MasterBrightFactor; + u16 * colors = bright_more_colors[masterBrightFactor]; +#endif + + /* when we wont do anything, we dont need to loop */ if (!(gpu->MasterBrightFactor)) break ; for(i16 = 0; i16 < 256; ++i16) { +#if 0 +#ifndef BRIGHT_TABLES + u8 base ; + u8 r,g,b; // get components, 5bit each + dstColor.val = *((u16 *) (dst + (i16 << 1))); + r = dstColor.bits.red; + g = dstColor.bits.green; + b = dstColor.bits.blue; + // Bright up and clamp to 5bit <-- automatic + base = 31 ; + dstColor.bits.red = r + ((base-r)*masterBrightFactor)/16; + dstColor.bits.green = g + ((base-g)*masterBrightFactor)/16; + dstColor.bits.blue = b + ((base-b)*masterBrightFactor)/16; +#else + dstColor.val = T1ReadWord(dst, i16 << 1); + dstColor.bitx.bgr = colors[dstColor.bitx.bgr]; +#endif + *((u16 *) (dst + (i16 << 1))) = dstColor.val; +#endif ((u16*)dst)[i16] = fadeInColors[gpu->MasterBrightFactor][((u16*)dst)[i16]&0x7FFF]; } break; @@ -2722,11 +2479,51 @@ static INLINE void GPU_ligne_MasterBrightness(NDS_Screen * screen, u16 l) // Bright down case 2: { - // when we wont do anything, we dont need to loop +/* + NOTE: gbatek (in the reference above) seems to expect 6bit values + per component, but as desmume works with 5bit per component, + we use 31 as top, instead of 63. Testing it on a few games, + using 63 seems to give severe color wraping, and 31 works + nicely, so for now we'll just that, until proven wrong. + + i have seen pics of pokemon ranger getting white with 31, with 63 it is nice. + it could be pb of alpha or blending or... + + MightyMax> created a test NDS to check how the brightness values work, + and 31 seems to be correct. FactorEx is a override for max brighten/darken + See: http://mightymax.org/gfx_test_brightness.nds + The Pokemon Problem could be a problem with 8/32 bit writes not recognized yet, + i'll add that so you can check back. + +*/ +#if 0 + COLOR dstColor; + unsigned int masterBrightFactor = gpu->MasterBrightFactor; + u16 * colors = bright_less_colors[masterBrightFactor]; +#endif + + /* when we wont do anything, we dont need to loop */ if (!gpu->MasterBrightFactor) break; for(i16 = 0; i16 < 256; ++i16) { +#if 0 +#ifndef BRIGHT_TABLES + u8 r,g,b; + dstColor.val = *((u16 *) (dst + (i16 << 1))); + r = dstColor.bits.red; + g = dstColor.bits.green; + b = dstColor.bits.blue; + // Bright up and clamp to 5bit <- automatic + dstColor.bits.red = r - (r*masterBrightFactor)/16; + dstColor.bits.green = g - (g*masterBrightFactor)/16; + dstColor.bits.blue = b - (b*masterBrightFactor)/16; +#else + dstColor.val = T1ReadWord(dst, i16 << 1); + dstColor.bitx.bgr = colors[dstColor.bitx.bgr]; +#endif + *((u16 *) (dst + (i16 << 1))) = dstColor.val; +#endif ((u16*)dst)[i16] = fadeOutColors[gpu->MasterBrightFactor][((u16*)dst)[i16]&0x7FFF]; } break; @@ -2736,7 +2533,7 @@ static INLINE void GPU_ligne_MasterBrightness(NDS_Screen * screen, u16 l) case 3: break; } - +#endif } void GPU_ligne(NDS_Screen * screen, u16 l) diff --git a/desmume/src/GPU.h b/src/GPU.h similarity index 95% rename from desmume/src/GPU.h rename to src/GPU.h index dac7c2aa2..c6f25050b 100644 --- a/desmume/src/GPU.h +++ b/src/GPU.h @@ -661,11 +661,8 @@ struct _GPU u8 MasterBrightMode; u32 MasterBrightFactor; - u8 bgPixels[256]; - - BOOL (*setFinalColorSpr)(GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); - BOOL (*setFinalColorBck)(GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); - BOOL (*setFinalColor3D) (GPU *gpu, u32 passing, u8 *dst, u16 color, u8 alpha, u16 x, u16 y); + BOOL (*setFinalColorSpr)(const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); + BOOL (*setFinalColorBck)(const GPU *gpu, u32 passing, u8 bgnum, u8 *dst, u16 color, u16 x, u16 y); void (*spriteRender) (GPU * gpu, u16 l, u8 * dst, u8 * prioTab); }; /* @@ -695,7 +692,7 @@ GPU * GPU_Init(u8 l); void GPU_Reset(GPU *g, u8 l); void GPU_DeInit(GPU *); -void textBG(GPU * gpu, u8 num, u8 * DST); //Draw text based background +void textBG(const GPU * gpu, u8 num, u8 * DST); //Draw text based background void rotBG(GPU * gpu, u8 num, u8 * DST); void extRotBG(GPU * gpu, u8 num, u8 * DST); void sprite1D(GPU * gpu, u16 l, u8 * dst, u8 * prioTab); diff --git a/desmume/src/GPU_osd.cpp b/src/GPU_osd.cpp similarity index 100% rename from desmume/src/GPU_osd.cpp rename to src/GPU_osd.cpp diff --git a/desmume/src/GPU_osd.h b/src/GPU_osd.h similarity index 100% rename from desmume/src/GPU_osd.h rename to src/GPU_osd.h diff --git a/desmume/src/MMU.cpp b/src/MMU.cpp similarity index 95% rename from desmume/src/MMU.cpp rename to src/MMU.cpp index 2d3ecac40..9c499f8d1 100644 --- a/desmume/src/MMU.cpp +++ b/src/MMU.cpp @@ -761,13 +761,18 @@ char txt[80]; static void execsqrt() { u32 ret; u16 cnt = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B0); - - if (cnt&1) { - u64 v = T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8); - ret = isqrt(v); - } else { + switch(cnt&1) + { + case 0: { u32 v = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8); ret = isqrt(v); + break; + } + case 1: { + u64 v = T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8); + ret = isqrt(v); + break; + } } T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B4, 0); T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B0, cnt | 0x8000); @@ -782,22 +787,20 @@ static void execdiv() { u16 cnt = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x280); s64 num,den; s64 res,mod; - switch(cnt&3) { case 0: num = (s64) (s32) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290); den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298); MMU.divCycles = (nds.cycles + 36); - break; - case 1: + break; case 3: //gbatek says this is same as mode 1 + case 1: num = (s64) T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290); den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298); MMU.divCycles = (nds.cycles + 68); - break; + break; case 2: - default: num = (s64) T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290); den = (s64) T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298); MMU.divCycles = (nds.cycles + 68); @@ -2228,67 +2231,35 @@ static void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val) if((adr>>24)==4) { - - // MightyMax: no need to do several ifs, when only one can happen - // switch/case instead - // both comparison >=,< per if can be replaced by one bit comparison since - // they are 2^4 aligned and 2^4n wide - // this looks ugly but should reduce load on register writes, they are done as - // lookups by the compiler - switch (adr >> 4) + if( (adr >= 0x04000330) && (adr < 0x04000340) ) //edge color table { - case 0x400033: //edge color table - ((u32 *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[(adr & 0xFFF) >> 2] = val; - return; - case 0x400036: //fog table - case 0x400037: - ((u32 *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[(adr & 0xFFF) >> 2] = val; - return; - case 0x400038: - case 0x400039: - case 0x40003A: - case 0x40003B: //toon table - ((u32 *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[(adr & 0xFFF) >> 2] = val; - gfx3d_UpdateToonTable(&((MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[(0x380)]); - return; - case 0x400040: - case 0x400041: - case 0x400042: - case 0x400043: // FIFO Commands - gfx3d_sendCommandToFIFO(val); - return; - case 0x400044: - case 0x400045: - case 0x400046: - case 0x400047: - case 0x400048: - case 0x400049: - case 0x40004A: - case 0x40004B: - case 0x40004C: - case 0x40004D: - case 0x40004E: - case 0x40004F: - case 0x400050: - case 0x400051: - case 0x400052: - case 0x400053: - case 0x400054: - case 0x400055: - case 0x400056: - case 0x400057: - case 0x400058: - case 0x400059: - case 0x40005A: - case 0x40005B: - case 0x40005C: - case 0x40005D: - case 0x40005E: - case 0x40005F: // Individual Commands - gfx3d_sendCommand(adr, val); - return; - default: - break; + ((u32 *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[(adr & 0xFFF) >> 2] = val; + return; + } + + if( (adr >= 0x04000360) && (adr < 0x04000380) ) //fog table + { + ((u32 *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[(adr & 0xFFF) >> 2] = val; + return; + } + + if( (adr >= 0x04000380) && (adr <= 0x40003BC) ) //toon table + { + ((u32 *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[(adr & 0xFFF) >> 2] = val; + gfx3d_UpdateToonTable(&((MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[(0x380)]); + return; + } + + if ( (adr >= 0x04000400) && (adr < 0x04000440) ) + { + gfx3d_sendCommandToFIFO(val); + return; + } + + if ( (adr >= 0x04000440) && (adr < 0x04000600) ) + { + gfx3d_sendCommand(adr, val); + return; } switch(adr) diff --git a/desmume/src/MMU.h b/src/MMU.h similarity index 100% rename from desmume/src/MMU.h rename to src/MMU.h diff --git a/desmume/src/Makefile.am b/src/Makefile.am similarity index 100% rename from desmume/src/Makefile.am rename to src/Makefile.am diff --git a/desmume/src/NDSSystem.cpp b/src/NDSSystem.cpp similarity index 100% rename from desmume/src/NDSSystem.cpp rename to src/NDSSystem.cpp diff --git a/desmume/src/NDSSystem.h b/src/NDSSystem.h similarity index 100% rename from desmume/src/NDSSystem.h rename to src/NDSSystem.h diff --git a/desmume/src/OGLRender.cpp b/src/OGLRender.cpp similarity index 74% rename from desmume/src/OGLRender.cpp rename to src/OGLRender.cpp index c19395f5a..c982b8484 100644 --- a/desmume/src/OGLRender.cpp +++ b/src/OGLRender.cpp @@ -74,7 +74,7 @@ static void ENDGL() { #endif static ALIGN(16) unsigned char GPU_screen3D [256*256*4]; -//static ALIGN(16) unsigned char GPU_screenStencil[256*256]; +static ALIGN(16) unsigned char GPU_screenStencil[256*256]; static const unsigned short map3d_cull[4] = {GL_FRONT_AND_BACK, GL_FRONT, GL_BACK, 0}; static const int texEnv[4] = { GL_MODULATE, GL_DECAL, GL_MODULATE, GL_MODULATE }; @@ -217,12 +217,12 @@ static void _xglDisable(GLenum cap) { //================================================= Textures #define MAX_TEXTURE 500 -#ifdef SSE2 -struct ALIGN(16) TextureCache -#else -struct ALIGN(8) TextureCache -#endif +struct TextureCache { + TextureCache() + : suspectedInvalid(true) + {} + GLenum id; unsigned int frm; unsigned int mode; @@ -233,14 +233,16 @@ struct ALIGN(8) TextureCache int coord; float invSizeX; float invSizeY; +#ifdef SSE2 + ALIGN(16) unsigned char texture[128*1024]; // 128Kb texture slot +#else unsigned char texture[128*1024]; // 128Kb texture slot - u8 palette[256*2]; - u16 palSize; +#endif //set if this texture is suspected be invalid due to a vram reconfigure bool suspectedInvalid; -}; +} ; TextureCache texcache[MAX_TEXTURE+1]; u32 texcache_count; @@ -364,13 +366,9 @@ static void OGLReset() texcache_start=0; texcache_stop=MAX_TEXTURE<<1; - for(i=0;i>14)&0x03; adr=(unsigned char *)(ARM9Mem.textureSlotAddr[txt_slot_current]+((format&0x3FFF)<<3)); - - switch (textureMode) - { - case 1: //a3i5 - pal = (unsigned short *)(ARM9Mem.texPalSlot[0] + (texturePalette<<4)); - break; - case 2: //i2 - pal = (unsigned short *)(ARM9Mem.texPalSlot[0] + (texturePalette<<3)); - break; - case 3: //i4 - pal = (unsigned short *)(ARM9Mem.texPalSlot[0] + (texturePalette<<4)); - break; - case 4: //i8 - pal = (unsigned short *)(ARM9Mem.texPalSlot[0] + (texturePalette<<4)); - break; - case 5: //4x4 - pal = (unsigned short *)(ARM9Mem.texPalSlot[0] + (texturePalette<<4)); - break; - case 6: //a5i3 - pal = (unsigned short *)(ARM9Mem.texPalSlot[0] + (texturePalette<<4)); - break; - case 7: //16bpp - pal = (unsigned short *)(ARM9Mem.texPalSlot[0] + (texturePalette<<4)); - break; - } i=texcache_start; @@ -607,31 +582,11 @@ static void setTexture(unsigned int format, unsigned int texpal) { if (texcache_stop==i) break; if (texcache[i].frm==0) break; - if ( (texcache[i].frm == format) && (texcache[i].pal == texpal) ) + if ((texcache[i].frm==format)&&(texcache[i].pal==texpal)) { - - if ((texcache[i].mode == 5) || - (texcache[i].mode == 7) || - !memcmp(texcache[i].palette, pal, texcache[i].palSize) ) - { - //TODO - this doesnt correctly span bank boundaries. in fact, it seems quite dangerous. - if (!memcmp(adr, texcache[i].texture, std::min((size_t)imageSize,sizeof(texcache[i].texture))) ) - { - texcache[i].suspectedInvalid = false; - texcache_count=i; - if(lastTexture == -1 || (int)i != lastTexture) - { - lastTexture = i; - glBindTexture(GL_TEXTURE_2D,texcache[i].id); - glMatrixMode (GL_TEXTURE); - glLoadIdentity (); - glScaled (texcache[i].invSizeX, texcache[i].invSizeY, 1.0f); - } - return; - } - } -#if 0 - if (!texcache[i].suspectedInvalid) + //TODO - we need to compare the palette also. + //TODO - this doesnt correctly span bank boundaries. in fact, it seems quite dangerous. + if (!texcache[i].suspectedInvalid || !memcmp(adr,texcache[i].texture,std::min((size_t)imageSize,sizeof(texcache[i].texture)))) { texcache[i].suspectedInvalid = false; texcache_count=i; @@ -645,7 +600,6 @@ static void setTexture(unsigned int format, unsigned int texpal) } return; } -#endif } i++; if (i>MAX_TEXTURE) @@ -673,14 +627,7 @@ static void setTexture(unsigned int format, unsigned int texpal) texcache[i].coord=(format>>30); texcache[i].invSizeX=1.0f/((float)(sizeX*(1<<4))); texcache[i].invSizeY=1.0f/((float)(sizeY*(1<<4))); - memcpy(texcache[i].texture,adr,std::min((size_t)imageSize,sizeof(texcache[i].texture))); - texcache[i].palSize = 0; - if ( (textureMode != 5) || (textureMode != 7) ) - { - texcache[i].palSize = 256*2; - memcpy(texcache[i].palette, pal, texcache[i].palSize); - } - + memcpy (texcache[i].texture,adr,std::min((size_t)imageSize,sizeof(texcache[i].texture))); texcache[i].numcolors=palSize[texcache[i].mode]; texcache[i].frm=format; @@ -696,223 +643,229 @@ static void setTexture(unsigned int format, unsigned int texpal) palZeroTransparent = (1-((format>>29)&1))*255; // shash: CONVERT THIS TO A TABLE :) txt_slot_size=(txt_slot_current_size=0x020000-((format & 0x3FFF)<<3)); - switch (texcache[i].mode) - { - case 1: //a3i5 + switch (texcache[i].mode) { - for(x = 0; x < imageSize; x++, dst += 4) + case 1: //a3i5 { - u16 c = pal[adr[x]&31]; - u8 alpha = adr[x]>>5; - *dwdst++ = RGB15TO32(c,material_3bit_to_8bit[alpha]); - CHECKSLOT; - } - break; - } - case 2: //i2 - { - for(x = 0; x < imageSize>>2; ++x) - { - unsigned short c = pal[(adr[x])&0x3]; - dst[0] = ((c & 0x1F)<<3); - dst[1] = ((c & 0x3E0)>>2); - dst[2] = ((c & 0x7C00)>>7); - dst[3] = ((adr[x]&3) == 0) ? palZeroTransparent : 255;//(c>>15)*255; - dst += 4; - - c = pal[((adr[x])>>2)&0x3]; - dst[0] = ((c & 0x1F)<<3); - dst[1] = ((c & 0x3E0)>>2); - dst[2] = ((c & 0x7C00)>>7); - dst[3] = (((adr[x]>>2)&3) == 0) ? palZeroTransparent : 255;//(c>>15)*255; - dst += 4; - - c = pal[((adr[x])>>4)&0x3]; - dst[0] = ((c & 0x1F)<<3); - dst[1] = ((c & 0x3E0)>>2); - dst[2] = ((c & 0x7C00)>>7); - dst[3] = (((adr[x]>>4)&3) == 0) ? palZeroTransparent : 255;//(c>>15)*255; - dst += 4; - - c = pal[(adr[x])>>6]; - dst[0] = ((c & 0x1F)<<3); - dst[1] = ((c & 0x3E0)>>2); - dst[2] = ((c & 0x7C00)>>7); - dst[3] = (((adr[x]>>6)&3) == 0) ? palZeroTransparent : 255;//(c>>15)*255; - dst += 4; - CHECKSLOT; - } - break; - } - case 3: //i4 - { - for(x = 0; x < (imageSize>>1); x++) + pal = (unsigned short *)(ARM9Mem.texPalSlot[0] + (texturePalette<<4)); + for(x = 0; x < imageSize; x++, dst += 4) { - unsigned short c = pal[adr[x]&0xF]; + u16 c = pal[adr[x]&31]; + u8 alpha = adr[x]>>5; + *dwdst++ = RGB15TO32(c,material_3bit_to_8bit[alpha]); + CHECKSLOT; + } + break; + } + case 2: //i2 + { + pal = (unsigned short *)(ARM9Mem.texPalSlot[0] + (texturePalette<<3)); + for(x = 0; x < imageSize>>2; ++x) + { + unsigned short c = pal[(adr[x])&0x3]; dst[0] = ((c & 0x1F)<<3); dst[1] = ((c & 0x3E0)>>2); dst[2] = ((c & 0x7C00)>>7); - dst[3] = (((adr[x])&0xF) == 0) ? palZeroTransparent : 255;//(c>>15)*255; + dst[3] = ((adr[x]&3) == 0) ? palZeroTransparent : 255;//(c>>15)*255; dst += 4; - c = pal[((adr[x])>>4)]; + c = pal[((adr[x])>>2)&0x3]; dst[0] = ((c & 0x1F)<<3); dst[1] = ((c & 0x3E0)>>2); dst[2] = ((c & 0x7C00)>>7); - dst[3] = (((adr[x]>>4)&0xF) == 0) ? palZeroTransparent : 255;//(c>>15)*255; + dst[3] = (((adr[x]>>2)&3) == 0) ? palZeroTransparent : 255;//(c>>15)*255; + dst += 4; + + c = pal[((adr[x])>>4)&0x3]; + dst[0] = ((c & 0x1F)<<3); + dst[1] = ((c & 0x3E0)>>2); + dst[2] = ((c & 0x7C00)>>7); + dst[3] = (((adr[x]>>4)&3) == 0) ? palZeroTransparent : 255;//(c>>15)*255; + dst += 4; + + c = pal[(adr[x])>>6]; + dst[0] = ((c & 0x1F)<<3); + dst[1] = ((c & 0x3E0)>>2); + dst[2] = ((c & 0x7C00)>>7); + dst[3] = (((adr[x]>>6)&3) == 0) ? palZeroTransparent : 255;//(c>>15)*255; dst += 4; CHECKSLOT; } break; } - case 4: //i8 - { - for(x = 0; x < imageSize; ++x) + case 3: //i4 { - u16 c = pal[adr[x]]; - *dwdst++ = RGB15TO32(c,(adr[x] == 0) ? palZeroTransparent : 255); - CHECKSLOT; + pal = (unsigned short *)(ARM9Mem.texPalSlot[0] + (texturePalette<<4)); + for(x = 0; x < (imageSize>>1); x++) + { + unsigned short c = pal[adr[x]&0xF]; + dst[0] = ((c & 0x1F)<<3); + dst[1] = ((c & 0x3E0)>>2); + dst[2] = ((c & 0x7C00)>>7); + dst[3] = (((adr[x])&0xF) == 0) ? palZeroTransparent : 255;//(c>>15)*255; + dst += 4; + + c = pal[((adr[x])>>4)]; + dst[0] = ((c & 0x1F)<<3); + dst[1] = ((c & 0x3E0)>>2); + dst[2] = ((c & 0x7C00)>>7); + dst[3] = (((adr[x]>>4)&0xF) == 0) ? palZeroTransparent : 255;//(c>>15)*255; + dst += 4; + CHECKSLOT; + } + break; } - } - break; - case 5: //4x4 - { - unsigned short * slot1; - unsigned int * map = (unsigned int *)adr; - unsigned int d = 0; - if ( (texcache[i].frm & 0xc000) == 0x8000) - // texel are in slot 2 - slot1=(unsigned short*)&ARM9Mem.textureSlotAddr[1][((texcache[i].frm&0x3FFF)<<2)+0x010000]; - else - slot1=(unsigned short*)&ARM9Mem.textureSlotAddr[1][(texcache[i].frm&0x3FFF)<<2]; - - bool dead = false; - u16 yTmpSize = (texcache[i].sizeY>>2); - u16 xTmpSize = (texcache[i].sizeX>>2); - - for (y = 0; y < yTmpSize; y ++) + case 4: //i8 + { + pal = (unsigned short *)(ARM9Mem.texPalSlot[0] + (texturePalette<<4)); + for(x = 0; x < imageSize; ++x) + { + u16 c = pal[adr[x]]; + *dwdst++ = RGB15TO32(c,(adr[x] == 0) ? palZeroTransparent : 255); + CHECKSLOT; + } + } + break; + case 5: //4x4 { - u32 tmpPos[4]={(y<<2)*texcache[i].sizeX,((y<<2)+1)*texcache[i].sizeX, - ((y<<2)+2)*texcache[i].sizeX,((y<<2)+3)*texcache[i].sizeX}; - for (x = 0; x < xTmpSize; x ++, d++) - { - u32 currBlock = map[d], sy; - u16 pal1 = slot1[d]; - u16 pal1offset = (pal1 & 0x3FFF)<<1; - u8 mode = pal1>>14; - u32 tmp_col[4]; + pal = (unsigned short *)(ARM9Mem.texPalSlot[0] + (texturePalette<<4)); + unsigned short * slot1; + unsigned int * map = (unsigned int *)adr; + unsigned int d = 0; + if ( (texcache[i].frm & 0xc000) == 0x8000) + // texel are in slot 2 + slot1=(unsigned short*)&ARM9Mem.textureSlotAddr[1][((texcache[i].frm&0x3FFF)<<2)+0x010000]; + else + slot1=(unsigned short*)&ARM9Mem.textureSlotAddr[1][(texcache[i].frm&0x3FFF)<<2]; - tmp_col[0]=RGB16TO32(pal[pal1offset],255); - tmp_col[1]=RGB16TO32(pal[pal1offset+1],255); + bool dead = false; - switch (mode) - { - case 0: - tmp_col[2]=RGB16TO32(pal[pal1offset+2],255); - tmp_col[3]=RGB16TO32(0x7FFF,0); - break; - case 1: - tmp_col[2]=(((tmp_col[0]&0xFF)+(tmp_col[1]&0xff))>>1)| - (((tmp_col[0]&(0xFF<<8))+(tmp_col[1]&(0xFF<<8)))>>1)| - (((tmp_col[0]&(0xFF<<16))+(tmp_col[1]&(0xFF<<16)))>>1)| - (0xff<<24); - tmp_col[3]=RGB16TO32(0x7FFF,0); - break; - case 2: - tmp_col[2]=RGB16TO32(pal[pal1offset+2],255); - tmp_col[3]=RGB16TO32(pal[pal1offset+3],255); - break; - case 3: + for (y = 0; y < (texcache[i].sizeY>>2); y ++) + { + u32 tmpPos[4]={(y<<2)*texcache[i].sizeX,((y<<2)+1)*texcache[i].sizeX, + ((y<<2)+2)*texcache[i].sizeX,((y<<2)+3)*texcache[i].sizeX}; + for (x = 0; x < (texcache[i].sizeX>>2); x ++, d++) { - u32 red1, red2; - u32 green1, green2; - u32 blue1, blue2; - u16 tmp1, tmp2; + u32 currBlock = map[d], sy; + u16 pal1 = slot1[d]; + u16 pal1offset = (pal1 & 0x3FFF)<<1; + u8 mode = pal1>>14; + u32 tmp_col[4]; - red1=tmp_col[0]&0xff; - green1=(tmp_col[0]>>8)&0xff; - blue1=(tmp_col[0]>>16)&0xff; - red2=tmp_col[1]&0xff; - green2=(tmp_col[1]>>8)&0xff; - blue2=(tmp_col[1]>>16)&0xff; + tmp_col[0]=RGB16TO32(pal[pal1offset],255); + tmp_col[1]=RGB16TO32(pal[pal1offset+1],255); - tmp1=((red1*5+red2*3)>>6)| - (((green1*5+green2*3)>>6)<<5)| - (((blue1*5+blue2*3)>>6)<<10); - tmp2=((red2*5+red1*3)>>6)| - (((green2*5+green1*3)>>6)<<5)| - (((blue2*5+blue1*3)>>6)<<10); - - tmp_col[2]=RGB16TO32(tmp1,255); - tmp_col[3]=RGB16TO32(tmp2,255); - break; - } - } - for (sy = 0; sy < 4; sy++) + switch (mode) { - // Texture offset - u32 currentPos = (x<<2) + tmpPos[sy]; - u8 currRow = (u8)((currBlock>>(sy<<3))&0xFF); - - dwdst[currentPos] = tmp_col[currRow&3]; - dwdst[currentPos+1] = tmp_col[(currRow>>2)&3]; - dwdst[currentPos+2] = tmp_col[(currRow>>4)&3]; - dwdst[currentPos+3] = tmp_col[(currRow>>6)&3]; - - if(dead) { - memset(dwdst, 0, sizeof(dwdst[0]) * 4); - } - - txt_slot_current_size-=4;; - if (txt_slot_current_size<=0) + case 0: + tmp_col[2]=RGB16TO32(pal[pal1offset+2],255); + tmp_col[3]=RGB16TO32(0x7FFF,0); + break; + case 1: + tmp_col[2]=(((tmp_col[0]&0xFF)+(tmp_col[1]&0xff))>>1)| + (((tmp_col[0]&(0xFF<<8))+(tmp_col[1]&(0xFF<<8)))>>1)| + (((tmp_col[0]&(0xFF<<16))+(tmp_col[1]&(0xFF<<16)))>>1)| + (0xff<<24); + tmp_col[3]=RGB16TO32(0x7FFF,0); + break; + case 2: + tmp_col[2]=RGB16TO32(pal[pal1offset+2],255); + tmp_col[3]=RGB16TO32(pal[pal1offset+3],255); + break; + case 3: { - //dead = true; - txt_slot_current++; - map=(unsigned int*)ARM9Mem.textureSlotAddr[txt_slot_current]; - map-=txt_slot_size>>2; //this is weird, but necessary since we use map[d] above - txt_slot_size=txt_slot_current_size=0x020000; + u32 red1, red2; + u32 green1, green2; + u32 blue1, blue2; + u16 tmp1, tmp2; + + red1=tmp_col[0]&0xff; + green1=(tmp_col[0]>>8)&0xff; + blue1=(tmp_col[0]>>16)&0xff; + red2=tmp_col[1]&0xff; + green2=(tmp_col[1]>>8)&0xff; + blue2=(tmp_col[1]>>16)&0xff; + + tmp1=((red1*5+red2*3)>>6)| + (((green1*5+green2*3)>>6)<<5)| + (((blue1*5+blue2*3)>>6)<<10); + tmp2=((red2*5+red1*3)>>6)| + (((green2*5+green1*3)>>6)<<5)| + (((blue2*5+blue1*3)>>6)<<10); + + tmp_col[2]=RGB16TO32(tmp1,255); + tmp_col[3]=RGB16TO32(tmp2,255); + break; + } + } + for (sy = 0; sy < 4; sy++) + { + // Texture offset + u32 currentPos = (x<<2) + tmpPos[sy]; + u8 currRow = (u8)((currBlock>>(sy<<3))&0xFF); + + dwdst[currentPos] = tmp_col[currRow&3]; + dwdst[currentPos+1] = tmp_col[(currRow>>2)&3]; + dwdst[currentPos+2] = tmp_col[(currRow>>4)&3]; + dwdst[currentPos+3] = tmp_col[(currRow>>6)&3]; + + if(dead) { + memset(dwdst, 0, sizeof(dwdst[0]) * 4); + } + + txt_slot_current_size-=4;; + if (txt_slot_current_size<=0) + { + //dead = true; + txt_slot_current++; + map=(unsigned int*)ARM9Mem.textureSlotAddr[txt_slot_current]; + map-=txt_slot_size>>2; //this is weird, but necessary since we use map[d] above + txt_slot_size=txt_slot_current_size=0x020000; + } } } } - } - break; - } - case 6: //a5i3 - { - for(x = 0; x < imageSize; x++) - { - u16 c = pal[adr[x]&0x07]; - u8 alpha = (adr[x]>>3); - *dwdst++ = RGB15TO32(c,material_5bit_to_8bit[alpha]); - CHECKSLOT; + break; } - break; - } - case 7: //16bpp - { - unsigned short * map = ((unsigned short *)adr); - - for(x = 0; x < imageSize; ++x) + case 6: //a5i3 { - u16 c = map[x]; - int alpha = ((c&0x8000)?255:0); - *dwdst++ = RGB15TO32(c&0x7FFF,alpha); - - txt_slot_current_size-=2;; - if (txt_slot_current_size<=0) + pal = (unsigned short *)(ARM9Mem.texPalSlot[0] + (texturePalette<<4)); + for(x = 0; x < imageSize; x++) { - txt_slot_current++; - map=(unsigned short *)ARM9Mem.textureSlotAddr[txt_slot_current]; - map-=txt_slot_size>>1; - txt_slot_size=txt_slot_current_size=0x020000; + u16 c = pal[adr[x]&0x07]; + u8 alpha = (adr[x]>>3); + *dwdst++ = RGB15TO32(c,material_5bit_to_8bit[alpha]); + CHECKSLOT; } + break; + } + case 7: //16bpp + { + unsigned short * map = ((unsigned short *)adr); + pal = (unsigned short *)(ARM9Mem.texPalSlot[0] + (texturePalette<<4)); + + for(x = 0; x < imageSize; ++x) + { + u16 c = map[x]; + int alpha = ((c&0x8000)?255:0); + *dwdst++ = RGB15TO32(c&0x7FFF,alpha); + + txt_slot_current_size-=2;; + if (txt_slot_current_size<=0) + { + txt_slot_current++; + map=(unsigned short *)ARM9Mem.textureSlotAddr[txt_slot_current]; + map-=txt_slot_size>>1; + txt_slot_size=txt_slot_current_size=0x020000; + } + } + break; } - break; - } } + glTexImage2D(GL_TEXTURE_2D, 0, GL_RGBA, texcache[i].sizeX, texcache[i].sizeY, 0, GL_RGBA, GL_UNSIGNED_BYTE, texMAP); @@ -1086,7 +1039,7 @@ static void OGLRender() //printf("%d\n",gfx3d.projlist->count); //we're not using the alpha clear color right now - glClearColor(gfx3d.clearColor[0],gfx3d.clearColor[1],gfx3d.clearColor[2], gfx3d.clearColor[3]); + glClearColor(gfx3d.clearColor[0],gfx3d.clearColor[1],gfx3d.clearColor[2], clearAlpha); glClearDepth(gfx3d.clearDepth); glClear(GL_COLOR_BUFFER_BIT | GL_DEPTH_BUFFER_BIT | GL_STENCIL_BUFFER_BIT); @@ -1167,7 +1120,7 @@ static void GL_ReadFramebuffer() { if(!BEGINGL()) return; glFinish(); -// glReadPixels(0,0,256,192,GL_STENCIL_INDEX, GL_UNSIGNED_BYTE, GPU_screenStencil); + glReadPixels(0,0,256,192,GL_STENCIL_INDEX, GL_UNSIGNED_BYTE, GPU_screenStencil); glReadPixels(0,0,256,192,GL_BGRA_EXT, GL_UNSIGNED_BYTE, GPU_screen3D); ENDGL(); @@ -1209,31 +1162,30 @@ static void OGLGetLineCaptured(int line, u16* dst) } u8 *screen3D = (u8*)GPU_screen3D+((191-line)<<10); -// u8 *screenStencil = (u8*)GPU_screenStencil+((191-line)<<8); + u8 *screenStencil = (u8*)GPU_screenStencil+((191-line)<<8); for(int i = 0; i < 256; i++) { - /* u32 stencil = screenStencil[i]; + u32 stencil = screenStencil[i]; if(!stencil) { dst[i] = 0x0000; continue; - }*/ + } int t=i<<2; - /* u8 r = screen3D[t+2]; - u8 g = screen3D[t+1]; - u8 b = screen3D[t+0];*/ + u32 r = screen3D[t+2]; + u32 g = screen3D[t+1]; + u32 b = screen3D[t+0]; //if this math strikes you as wrong, be sure to look at GL_ReadFramebuffer() where the pixel format in screen3D is changed - //dst[i] = (b<<10) | (g<<5) | (r) | 0x8000; - dst[i] = (screen3D[t+2] | (screen3D[t+1] << 5) | (screen3D[t+0] << 10) | ((screen3D[t+3] > 0) ? 0x8000 : 0x0000)); + dst[i] = (b<<10) | (g<<5) | (r) | 0x8000; } } -static void OGLGetLine(int line, int start, int end_inclusive, u16* dst, u8* dstAlpha) +static void OGLGetLine(int line, int start, int end_inclusive, u16* dst) { assert(line<192 && line>=0); @@ -1243,7 +1195,7 @@ static void OGLGetLine(int line, int start, int end_inclusive, u16* dst, u8* dst } u8 *screen3D = (u8*)GPU_screen3D+((191-line)<<10); - //u8 *screenStencil = (u8*)GPU_screenStencil+((191-line)<<8); + u8 *screenStencil = (u8*)GPU_screenStencil+((191-line)<<8); //the renderer clears the stencil to 0 //then it sets it to 1 whenever it renders a pixel that passes the alpha test @@ -1257,18 +1209,15 @@ static void OGLGetLine(int line, int start, int end_inclusive, u16* dst, u8* dst for(int i = start, j=0; i <= end_inclusive; ++i, ++j) { - // u32 stencil = screenStencil[i]; + u32 stencil = screenStencil[i]; //you would use this if you wanted to use the stencil buffer to make decisions here - // if(!stencil) continue; + if(!stencil) continue; - // u16 oldcolor = dst[j]; + u16 oldcolor = dst[j]; int t=i<<2; - // u32 dstpixel; - - dst[j] = (screen3D[t+2] | (screen3D[t+1] << 5) | (screen3D[t+0] << 10) | ((screen3D[t+3] > 0) ? 0x8000 : 0x0000)); - dstAlpha[j] = (screen3D[t+3] / 2); + u32 dstpixel; //old debug reminder: display alpha channel //u32 r = screen3D[t+3]; @@ -1277,7 +1226,7 @@ static void OGLGetLine(int line, int start, int end_inclusive, u16* dst, u8* dst //if this math strikes you as wrong, be sure to look at GL_ReadFramebuffer() where the pixel format in screen3D is changed - /* u32 a = screen3D[t+3]; + u32 a = screen3D[t+3]; typedef u8 mixtbl[32][32]; mixtbl & mix = mixTable555[a]; @@ -1300,7 +1249,7 @@ static void OGLGetLine(int line, int start, int end_inclusive, u16* dst, u8* dst newpix = mix[newpix][oldpix]; dstpixel |= (newpix<<10); - dst[j] = dstpixel;*/ + dst[j] = dstpixel; } } diff --git a/desmume/src/OGLRender.h b/src/OGLRender.h similarity index 100% rename from desmume/src/OGLRender.h rename to src/OGLRender.h diff --git a/desmume/src/PACKED.h b/src/PACKED.h similarity index 100% rename from desmume/src/PACKED.h rename to src/PACKED.h diff --git a/desmume/src/PACKED_END.h b/src/PACKED_END.h similarity index 100% rename from desmume/src/PACKED_END.h rename to src/PACKED_END.h diff --git a/desmume/src/ROMReader.cpp b/src/ROMReader.cpp similarity index 100% rename from desmume/src/ROMReader.cpp rename to src/ROMReader.cpp diff --git a/desmume/src/ROMReader.h b/src/ROMReader.h similarity index 100% rename from desmume/src/ROMReader.h rename to src/ROMReader.h diff --git a/desmume/src/SPU.cpp b/src/SPU.cpp similarity index 100% rename from desmume/src/SPU.cpp rename to src/SPU.cpp diff --git a/desmume/src/SPU.h b/src/SPU.h similarity index 100% rename from desmume/src/SPU.h rename to src/SPU.h diff --git a/desmume/src/arm_instructions.cpp b/src/arm_instructions.cpp similarity index 96% rename from desmume/src/arm_instructions.cpp rename to src/arm_instructions.cpp index 5d0beca53..d2b0f1b9d 100644 --- a/desmume/src/arm_instructions.cpp +++ b/src/arm_instructions.cpp @@ -1,7823 +1,7823 @@ -/* Copyright (C) 2006 yopyop - Copyright (C) 2006 shash - yopyop156@ifrance.com - yopyop156.ifrance.com - - Copyright (C) 2006-2007 shash - - This file is part of DeSmuME - - DeSmuME is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - DeSmuME is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with DeSmuME; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include "cp15.h" -#include "debug.h" -#include "MMU.h" -#include "armcpu.h" -#include "NDSSystem.h" - -#define cpu (&ARMPROC) -#define TEMPLATE template - -extern volatile BOOL execute; - -#define LSL_IMM shift_op = cpu->R[REG_POS(i,0)]<<((i>>7)&0x1F); - -#define S_LSL_IMM u32 shift_op = ((i>>7)&0x1F);\ - u32 c = cpu->CPSR.bits.C;\ - if(shift_op==0)\ - shift_op=cpu->R[REG_POS(i,0)];\ - else\ - {\ - c = BIT_N(cpu->R[REG_POS(i,0)], 32-shift_op);\ - shift_op = cpu->R[REG_POS(i,0)]<<((i>>7)&0x1F);\ - } - -#define LSL_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\ - if(shift_op>=32)\ - shift_op=0;\ - else\ - shift_op=cpu->R[REG_POS(i,0)]<R[REG_POS(i,8)])&0xFF;\ - u32 c = cpu->CPSR.bits.C;\ - if(shift_op==0)\ - shift_op=cpu->R[REG_POS(i,0)];\ - else\ - if(shift_op<32)\ - {\ - c = BIT_N(cpu->R[REG_POS(i,0)], 32-shift_op);\ - shift_op = cpu->R[REG_POS(i,0)]<R[REG_POS(i,0)]);\ - }\ - else\ - {\ - shift_op = 0;\ - c = 0;\ - } - -#define LSR_IMM shift_op = ((i>>7)&0x1F);\ - if(shift_op!=0)\ - shift_op = cpu->R[REG_POS(i,0)]>>shift_op; - -#define S_LSR_IMM u32 shift_op = ((i>>7)&0x1F);\ - u32 c = cpu->CPSR.bits.C;\ - if(shift_op==0)\ - {\ - c = BIT31(cpu->R[REG_POS(i,0)]);\ - }\ - else\ - {\ - c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\ - shift_op = cpu->R[REG_POS(i,0)]>>shift_op;\ - } - -#define LSR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\ - if(shift_op>=32)\ - shift_op = 0;\ - else\ - shift_op = cpu->R[REG_POS(i,0)]>>shift_op; - -#define S_LSR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\ - u32 c = cpu->CPSR.bits.C;\ - if(shift_op==0)\ - {\ - shift_op = cpu->R[REG_POS(i,0)];\ - }\ - else\ - if(shift_op<32)\ - {\ - c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\ - shift_op = cpu->R[REG_POS(i,0)]>>shift_op;\ - }\ - else\ - if(shift_op==32)\ - {\ - c = BIT31(cpu->R[REG_POS(i,0)]);\ - shift_op = 0;\ - }\ - else\ - {\ - c = 0;\ - shift_op = 0;\ - } - -#define ASR_IMM shift_op = ((i>>7)&0x1F);\ - if(shift_op==0)\ - shift_op=BIT31(cpu->R[REG_POS(i,0)])*0xFFFFFFFF;\ - else\ - shift_op = (u32)(((s32)(cpu->R[REG_POS(i,0)]))>>shift_op); - -#define S_ASR_IMM u32 shift_op = ((i>>7)&0x1F);\ - u32 c = cpu->CPSR.bits.C;\ - if(shift_op==0)\ - {\ - shift_op=BIT31(cpu->R[REG_POS(i,0)])*0xFFFFFFFF;\ - c = BIT31(cpu->R[REG_POS(i,0)]);\ - }\ - else\ - {\ - c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\ - shift_op = (u32)(((s32)(cpu->R[REG_POS(i,0)]))>>shift_op);\ - } - -#define ASR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\ - if(shift_op==0)\ - shift_op=cpu->R[REG_POS(i,0)];\ - else\ - if(shift_op<32)\ - shift_op = (u32)(((s32)(cpu->R[REG_POS(i,0)]))>>shift_op);\ - else\ - shift_op=BIT31(cpu->R[REG_POS(i,0)])*0xFFFFFFFF; - -#define S_ASR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\ - u32 c = cpu->CPSR.bits.C;\ - if(shift_op==0)\ - shift_op=cpu->R[REG_POS(i,0)];\ - else\ - if(shift_op<32)\ - {\ - c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\ - shift_op = (u32)(((s32)(cpu->R[REG_POS(i,0)]))>>shift_op);\ - }\ - else\ - {\ - c = BIT31(cpu->R[REG_POS(i,0)]);\ - shift_op=BIT31(cpu->R[REG_POS(i,0)])*0xFFFFFFFF;\ - } - -#define ROR_IMM shift_op = ((i>>7)&0x1F);\ - if(shift_op==0)\ - {\ - u32 tmp = cpu->CPSR.bits.C;\ - shift_op = (tmp<<31)|(cpu->R[REG_POS(i,0)]>>1);\ - }\ - else\ - shift_op = ROR(cpu->R[REG_POS(i,0)],shift_op); - -#define S_ROR_IMM u32 shift_op = ((i>>7)&0x1F);\ - u32 c = cpu->CPSR.bits.C;\ - if(shift_op==0)\ - {\ - u32 tmp = cpu->CPSR.bits.C;\ - shift_op = (tmp<<31)|(cpu->R[REG_POS(i,0)]>>1);\ - c = BIT0(cpu->R[REG_POS(i,0)]);\ - }\ - else\ - {\ - c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\ - shift_op = ROR(cpu->R[REG_POS(i,0)],shift_op);\ - } - -#define ROR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\ - if((shift_op==0)||((shift_op&0xF)==0))\ - shift_op=cpu->R[REG_POS(i,0)];\ - else\ - shift_op = ROR(cpu->R[REG_POS(i,0)],(shift_op&0xF)); - -#define S_ROR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\ - u32 c = cpu->CPSR.bits.C;\ - if(shift_op==0)\ - shift_op=cpu->R[REG_POS(i,0)];\ - else\ - {\ - shift_op&=0xF;\ - if(shift_op==0)\ - {\ - shift_op=cpu->R[REG_POS(i,0)];\ - c = BIT31(cpu->R[REG_POS(i,0)]);\ - }\ - else\ - {\ - c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\ - shift_op = ROR(cpu->R[REG_POS(i,0)],(shift_op&0xF));\ - }\ - } - -#define IMM_VALUE u32 shift_op = ROR((i&0xFF), (i>>7)&0x1E); - -#define S_IMM_VALUE u32 shift_op = ROR((i&0xFF), (i>>7)&0x1E);\ - u32 c = cpu->CPSR.bits.C;\ - if((i>>8)&0xF)\ - c = BIT31(shift_op); - -#define IMM_OFF (((i>>4)&0xF0)+(i&0xF)) - -#define IMM_OFF_12 ((i)&0xFFF) - -TEMPLATE static u32 FASTCALL OP_UND() -{ - LOG("Undefined instruction: %08X\n", cpu->instruction); - emu_halt(); - LOG("Stopped (OP_UND)\n"); - return 1; -} - -#define TRAPUNDEF() \ - LOG("Undefined instruction: %#08X PC = %#08X\n", cpu->instruction, cpu->instruct_adr); \ - \ - if (((cpu->intVector != 0) ^ (PROCNUM == ARMCPU_ARM9))){ \ - Status_Reg tmp = cpu->CPSR; \ - armcpu_switchMode(cpu, UND); /* enter und mode */ \ - cpu->R[14] = cpu->R[15] - 4; /* jump to und Vector */ \ - cpu->SPSR = tmp; /* save old CPSR as new SPSR */ \ - cpu->CPSR.bits.T = 0; /* handle as ARM32 code */ \ - cpu->CPSR.bits.I = cpu->SPSR.bits.I; /* keep int disable flag */ \ - cpu->R[15] = cpu->intVector + 0x04; \ - cpu->next_instruction = cpu->R[15]; \ - return 4; \ - } \ - else \ - { \ - emu_halt(); \ - return 4; \ - } \ - -//-----------------------AND------------------------------------ - -#define OP_AND(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] & shift_op;\ - if(REG_POS(i,12)==15)\ - {\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - return a; - -#define OP_ANDS(a, b)\ - if(REG_POS(i,12)==15)\ - {\ - Status_Reg SPSR;\ - cpu->R[15] = cpu->R[REG_POS(i,16)] & shift_op;\ - SPSR = cpu->SPSR;\ - armcpu_switchMode(cpu, SPSR.bits.mode);\ - cpu->CPSR=SPSR;\ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] & shift_op;\ - cpu->CPSR.bits.C = c;\ - cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ - return a; - -TEMPLATE static u32 FASTCALL OP_AND_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSL_IMM; - OP_AND(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_AND_LSL_REG() -{ - const u32 &i = cpu->instruction; - LSL_REG; - OP_AND(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_AND_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSR_IMM; - OP_AND(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_AND_LSR_REG() -{ - const u32 &i = cpu->instruction; - LSR_REG; - OP_AND(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_AND_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ASR_IMM; - OP_AND(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_AND_ASR_REG() -{ - const u32 &i = cpu->instruction; - ASR_REG; - OP_AND(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_AND_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ROR_IMM; - OP_AND(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_AND_ROR_REG() -{ - const u32 &i = cpu->instruction; - ROR_REG; - OP_AND(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_AND_IMM_VAL() -{ - const u32 &i = cpu->instruction; - IMM_VALUE; - OP_AND(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_AND_S_LSL_IMM() -{ - const u32 &i = cpu->instruction; - S_LSL_IMM; - OP_ANDS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_AND_S_LSL_REG() -{ - const u32 &i = cpu->instruction; - S_LSL_REG; - OP_ANDS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_AND_S_LSR_IMM() -{ - const u32 &i = cpu->instruction; - S_LSR_IMM; - OP_ANDS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_AND_S_LSR_REG() -{ - const u32 &i = cpu->instruction; - S_LSR_REG; - OP_ANDS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_AND_S_ASR_IMM() -{ - const u32 &i = cpu->instruction; - S_ASR_IMM; - OP_ANDS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_AND_S_ASR_REG() -{ - const u32 &i = cpu->instruction; - S_ASR_REG; - OP_ANDS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_AND_S_ROR_IMM() -{ - const u32 &i = cpu->instruction; - S_ROR_IMM; - OP_ANDS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_AND_S_ROR_REG() -{ - const u32 &i = cpu->instruction; - S_ROR_REG; - OP_ANDS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_AND_S_IMM_VAL() -{ - const u32 &i = cpu->instruction; - S_IMM_VALUE; - OP_ANDS(2, 4); -} - -//--------------EOR------------------------------ - -#define OP_EOR(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] ^ shift_op;\ - if(REG_POS(i,12)==15)\ - {\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - return a; - -#define OP_EORS(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] ^ shift_op;\ - if(REG_POS(i,12)==15)\ - {\ - Status_Reg SPSR = cpu->SPSR;\ - armcpu_switchMode(cpu, SPSR.bits.mode);\ - cpu->CPSR=SPSR;\ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - cpu->CPSR.bits.C = c;\ - cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ - return a; - -TEMPLATE static u32 FASTCALL OP_EOR_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSL_IMM; - OP_EOR(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_EOR_LSL_REG() -{ - const u32 &i = cpu->instruction; - LSL_REG; - OP_EOR(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_EOR_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSR_IMM; - OP_EOR(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_EOR_LSR_REG() -{ - const u32 &i = cpu->instruction; - LSR_REG; - OP_EOR(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_EOR_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ASR_IMM; - OP_EOR(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_EOR_ASR_REG() -{ - const u32 &i = cpu->instruction; - ASR_REG; - OP_EOR(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_EOR_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ROR_IMM; - OP_EOR(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_EOR_ROR_REG() -{ - const u32 &i = cpu->instruction; - ROR_REG; - OP_EOR(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_EOR_IMM_VAL() -{ - const u32 &i = cpu->instruction; - IMM_VALUE; - OP_EOR(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_EOR_S_LSL_IMM() -{ - const u32 &i = cpu->instruction; - S_LSL_IMM; - OP_EORS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_EOR_S_LSL_REG() -{ - const u32 &i = cpu->instruction; - S_LSL_REG; - OP_EORS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_EOR_S_LSR_IMM() -{ - const u32 &i = cpu->instruction; - S_LSR_IMM; - OP_EORS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_EOR_S_LSR_REG() -{ - const u32 &i = cpu->instruction; - S_LSR_REG; - OP_EORS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_EOR_S_ASR_IMM() -{ - const u32 &i = cpu->instruction; - S_ASR_IMM; - OP_EORS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_EOR_S_ASR_REG() -{ - const u32 &i = cpu->instruction; - S_ASR_REG; - OP_EORS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_EOR_S_ROR_IMM() -{ - const u32 &i = cpu->instruction; - S_ROR_IMM; - OP_EORS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_EOR_S_ROR_REG() -{ - const u32 &i = cpu->instruction; - S_ROR_REG; - OP_EORS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_EOR_S_IMM_VAL() -{ - const u32 &i = cpu->instruction; - S_IMM_VALUE; - OP_EORS(2, 4); -} - -//-------------SUB------------------------------------- - -#define OP_SUB(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] - shift_op;\ - if(REG_POS(i,12)==15)\ - {\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - return a; - -#define OPSUBS(a, b) cpu->R[REG_POS(i,12)] = v - shift_op;\ - if(REG_POS(i,12)==15)\ - {\ - Status_Reg SPSR = cpu->SPSR;\ - armcpu_switchMode(cpu, SPSR.bits.mode);\ - cpu->CPSR=SPSR;\ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ - cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\ - cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\ - return a; - -TEMPLATE static u32 FASTCALL OP_SUB_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSL_IMM; - OP_SUB(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_SUB_LSL_REG() -{ - const u32 &i = cpu->instruction; - LSL_REG; - OP_SUB(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_SUB_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSR_IMM; - OP_SUB(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_SUB_LSR_REG() -{ - const u32 &i = cpu->instruction; - LSR_REG; - OP_SUB(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_SUB_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ASR_IMM; - OP_SUB(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_SUB_ASR_REG() -{ - const u32 &i = cpu->instruction; - ASR_REG; - OP_SUB(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_SUB_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ROR_IMM; - OP_SUB(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_SUB_ROR_REG() -{ - const u32 &i = cpu->instruction; - ROR_REG; - OP_SUB(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_SUB_IMM_VAL() -{ - const u32 &i = cpu->instruction; - IMM_VALUE; - OP_SUB(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_SUB_S_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - LSL_IMM; - OPSUBS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_SUB_S_LSL_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - LSL_REG; - OPSUBS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_SUB_S_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - LSR_IMM; - OPSUBS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_SUB_S_LSR_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - LSR_REG; - OPSUBS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_SUB_S_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - ASR_IMM; - OPSUBS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_SUB_S_ASR_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - ASR_REG; - OPSUBS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_SUB_S_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - ROR_IMM; - OPSUBS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_SUB_S_ROR_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - ROR_REG; - OPSUBS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_SUB_S_IMM_VAL() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - IMM_VALUE; - OPSUBS(2, 4); -} - -//------------------RSB------------------------ - -#define OP_RSB(a, b) cpu->R[REG_POS(i,12)] = shift_op - cpu->R[REG_POS(i,16)];\ - if(REG_POS(i,12)==15)\ - {\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - return a; - -#define OP_RSBS(a, b) cpu->R[REG_POS(i,12)] = shift_op - v;\ - if(REG_POS(i,12)==15)\ - {\ - Status_Reg SPSR = cpu->SPSR;\ - armcpu_switchMode(cpu, SPSR.bits.mode);\ - cpu->CPSR=SPSR;\ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ - cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(shift_op, v, cpu->R[REG_POS(i,12)]);\ - cpu->CPSR.bits.V = SIGNED_UNDERFLOW(shift_op, v, cpu->R[REG_POS(i,12)]);\ - return a; - -TEMPLATE static u32 FASTCALL OP_RSB_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSL_IMM; - OP_RSB(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_RSB_LSL_REG() -{ - const u32 &i = cpu->instruction; - LSL_REG; - OP_RSB(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_RSB_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSR_IMM; - OP_RSB(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_RSB_LSR_REG() -{ - const u32 &i = cpu->instruction; - LSR_REG; - OP_RSB(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_RSB_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ASR_IMM; - OP_RSB(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_RSB_ASR_REG() -{ - const u32 &i = cpu->instruction; - ASR_REG; - OP_RSB(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_RSB_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ROR_IMM; - OP_RSB(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_RSB_ROR_REG() -{ - const u32 &i = cpu->instruction; - ROR_REG; - OP_RSB(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_RSB_IMM_VAL() -{ - const u32 &i = cpu->instruction; - IMM_VALUE; - OP_RSB(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_RSB_S_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - LSL_IMM; - OP_RSBS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_RSB_S_LSL_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - LSL_REG; - OP_RSBS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_RSB_S_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - LSR_IMM; - OP_RSBS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_RSB_S_LSR_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - LSR_REG; - OP_RSBS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_RSB_S_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - ASR_IMM; - OP_RSBS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_RSB_S_ASR_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - ASR_REG; - OP_RSBS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_RSB_S_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - ROR_IMM; - OP_RSBS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_RSB_S_ROR_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - ROR_REG; - OP_RSBS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_RSB_S_IMM_VAL() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - IMM_VALUE; - OP_RSBS(2, 4); -} - -//------------------ADD----------------------------------- - -#define OP_ADD(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] + shift_op;\ - if(REG_POS(i,12)==15)\ - {\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - return a; - -TEMPLATE static u32 FASTCALL OP_ADD_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSL_IMM; - OP_ADD(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_ADD_LSL_REG() -{ - const u32 &i = cpu->instruction; - LSL_REG; - OP_ADD(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ADD_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSR_IMM; - OP_ADD(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_ADD_LSR_REG() -{ - const u32 &i = cpu->instruction; - LSR_REG; - OP_ADD(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ADD_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ASR_IMM; - OP_ADD(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_ADD_ASR_REG() -{ - const u32 &i = cpu->instruction; - ASR_REG; - OP_ADD(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ADD_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ROR_IMM; - OP_ADD(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_ADD_ROR_REG() -{ - const u32 &i = cpu->instruction; - ROR_REG; - OP_ADD(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ADD_IMM_VAL() -{ - const u32 &i = cpu->instruction; - IMM_VALUE; - OP_ADD(1, 3); -} - -#define OP_ADDS(a, b) cpu->R[REG_POS(i,12)] = v + shift_op;\ - if(REG_POS(i,12)==15)\ - {\ - Status_Reg SPSR = cpu->SPSR;\ - armcpu_switchMode(cpu, SPSR.bits.mode);\ - cpu->CPSR=SPSR;\ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ - cpu->CPSR.bits.C = UNSIGNED_OVERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\ - cpu->CPSR.bits.V = SIGNED_OVERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\ - return a; - -TEMPLATE static u32 FASTCALL OP_ADD_S_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - LSL_IMM; - OP_ADDS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ADD_S_LSL_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - LSL_REG; - OP_ADDS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_ADD_S_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - LSR_IMM; - OP_ADDS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ADD_S_LSR_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - LSR_REG; - OP_ADDS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_ADD_S_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - ASR_IMM; - OP_ADDS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ADD_S_ASR_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - ASR_REG; - OP_ADDS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_ADD_S_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - ROR_IMM; - OP_ADDS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ADD_S_ROR_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - ROR_REG; - OP_ADDS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_ADD_S_IMM_VAL() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - IMM_VALUE; - OP_ADDS(2, 4); -} - -//------------------ADC----------------------------------- - -#define OP_ADC(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] + shift_op + cpu->CPSR.bits.C;\ - if(REG_POS(i,12)==15)\ - {\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - return a; - -TEMPLATE static u32 FASTCALL OP_ADC_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSL_IMM; - OP_ADC(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_ADC_LSL_REG() -{ - const u32 &i = cpu->instruction; - LSL_REG; - OP_ADC(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ADC_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSR_IMM; - OP_ADC(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_ADC_LSR_REG() -{ - const u32 &i = cpu->instruction; - LSR_REG; - OP_ADC(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ADC_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ASR_IMM; - OP_ADC(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_ADC_ASR_REG() -{ - const u32 &i = cpu->instruction; - ASR_REG; - OP_ADC(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ADC_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ROR_IMM; - OP_ADC(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_ADC_ROR_REG() -{ - const u32 &i = cpu->instruction; - ROR_REG; - OP_ADC(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ADC_IMM_VAL() -{ - const u32 &i = cpu->instruction; - IMM_VALUE; - OP_ADC(1, 3); -} - -#define OP_ADCS(a, b) \ - { \ - u32 tmp = shift_op + cpu->CPSR.bits.C;\ - cpu->R[REG_POS(i,12)] = v + tmp;\ - if(REG_POS(i,12)==15)\ - {\ - Status_Reg SPSR = cpu->SPSR;\ - armcpu_switchMode(cpu, SPSR.bits.mode);\ - cpu->CPSR=SPSR;\ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ - cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(tmp, (u32)cpu->CPSR.bits.C, cpu->R[REG_POS(i,12)]); \ - cpu->CPSR.bits.V = SIGNED_UNDERFLOW(tmp, (u32)cpu->CPSR.bits.C, cpu->R[REG_POS(i,12)]); \ - return a; \ - } - -TEMPLATE static u32 FASTCALL OP_ADC_S_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - LSL_IMM; - OP_ADCS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ADC_S_LSL_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - LSL_REG; - OP_ADCS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_ADC_S_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - LSR_IMM; - OP_ADCS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ADC_S_LSR_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - LSR_REG; - OP_ADCS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_ADC_S_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - ASR_IMM; - OP_ADCS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ADC_S_ASR_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - ASR_REG; - OP_ADCS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_ADC_S_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - ROR_IMM; - OP_ADCS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ADC_S_ROR_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - ROR_REG; - OP_ADCS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_ADC_S_IMM_VAL() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - IMM_VALUE; - OP_ADCS(2, 4); -} - -//-------------SBC------------------------------------- - -#define OP_SBC(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] - shift_op - (!cpu->CPSR.bits.C);\ - if(REG_POS(i,12)==15)\ - {\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - return a; - -TEMPLATE static u32 FASTCALL OP_SBC_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSL_IMM; - OP_SBC(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_SBC_LSL_REG() -{ - const u32 &i = cpu->instruction; - LSL_REG; - OP_SBC(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_SBC_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSR_IMM; - OP_SBC(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_SBC_LSR_REG() -{ - const u32 &i = cpu->instruction; - LSR_REG; - OP_SBC(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_SBC_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ASR_IMM; - OP_SBC(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_SBC_ASR_REG() -{ - const u32 &i = cpu->instruction; - ASR_REG; - OP_SBC(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_SBC_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ROR_IMM; - OP_SBC(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_SBC_ROR_REG() -{ - const u32 &i = cpu->instruction; - ROR_REG; - OP_SBC(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_SBC_IMM_VAL() -{ - const u32 &i = cpu->instruction; - IMM_VALUE; - OP_SBC(1, 3); -} - -#define OP_SBCS(a, b) \ - { \ - u32 tmp = v - (!cpu->CPSR.bits.C);\ - cpu->R[REG_POS(i,12)] = tmp - shift_op;\ - if(REG_POS(i,12)==15)\ - {\ - Status_Reg SPSR = cpu->SPSR;\ - armcpu_switchMode(cpu, SPSR.bits.mode);\ - cpu->CPSR=SPSR;\ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ - cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\ - cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\ - return a; \ - } - -TEMPLATE static u32 FASTCALL OP_SBC_S_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - LSL_IMM; - OP_SBCS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_SBC_S_LSL_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - LSL_REG; - OP_SBCS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_SBC_S_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - LSR_IMM; - OP_SBCS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_SBC_S_LSR_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - LSR_REG; - OP_SBCS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_SBC_S_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - ASR_IMM; - OP_SBCS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_SBC_S_ASR_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - ASR_REG; - OP_SBCS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_SBC_S_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - ROR_IMM; - OP_SBCS(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_SBC_S_ROR_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - ROR_REG; - OP_SBCS(3, 5); -} - -TEMPLATE static u32 FASTCALL OP_SBC_S_IMM_VAL() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - IMM_VALUE; - OP_SBCS(2, 4); -} - -//---------------RSC---------------------------------- - -#define OP_RSC(a, b) cpu->R[REG_POS(i,12)] = shift_op - cpu->R[REG_POS(i,16)] - (!cpu->CPSR.bits.C);\ - if(REG_POS(i,12)==15)\ - {\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - return a; - -TEMPLATE static u32 FASTCALL OP_RSC_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSL_IMM; - OP_RSC(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_RSC_LSL_REG() -{ - const u32 &i = cpu->instruction; - LSL_REG; - OP_RSC(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_RSC_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSR_IMM; - OP_RSC(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_RSC_LSR_REG() -{ - const u32 &i = cpu->instruction; - LSR_REG; - OP_RSC(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_RSC_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ASR_IMM; - OP_RSC(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_RSC_ASR_REG() -{ - const u32 &i = cpu->instruction; - ASR_REG; - OP_RSC(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_RSC_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ROR_IMM; - OP_RSC(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_RSC_ROR_REG() -{ - const u32 &i = cpu->instruction; - ROR_REG; - OP_RSC(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_RSC_IMM_VAL() -{ - const u32 &i = cpu->instruction; - IMM_VALUE; - OP_RSC(1, 3); -} - -#define OP_RSCS(a,b) \ - { \ - u32 tmp = shift_op - (!cpu->CPSR.bits.C);\ - cpu->R[REG_POS(i,12)] = tmp - v;\ - if(REG_POS(i,12)==15)\ - {\ - Status_Reg SPSR = cpu->SPSR;\ - armcpu_switchMode(cpu, SPSR.bits.mode);\ - cpu->CPSR=SPSR;\ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ - cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\ - cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\ - return a; \ - } - -TEMPLATE static u32 FASTCALL OP_RSC_S_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - LSL_IMM; - OP_RSCS(2,4); -} - -TEMPLATE static u32 FASTCALL OP_RSC_S_LSL_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - LSL_REG; - OP_RSCS(3,5); -} - -TEMPLATE static u32 FASTCALL OP_RSC_S_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - LSR_IMM; - OP_RSCS(2,4); -} - -TEMPLATE static u32 FASTCALL OP_RSC_S_LSR_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - LSR_REG; - OP_RSCS(3,5); -} - -TEMPLATE static u32 FASTCALL OP_RSC_S_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - ASR_IMM; - OP_RSCS(2,4); -} - -TEMPLATE static u32 FASTCALL OP_RSC_S_ASR_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - ASR_REG; - OP_RSCS(3,5); -} - -TEMPLATE static u32 FASTCALL OP_RSC_S_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - u32 shift_op; - ROR_IMM; - OP_RSCS(2,4); -} - -TEMPLATE static u32 FASTCALL OP_RSC_S_ROR_REG() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - ROR_REG; - OP_RSCS(3,5); -} - -TEMPLATE static u32 FASTCALL OP_RSC_S_IMM_VAL() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,16)]; - IMM_VALUE; - OP_RSCS(2,4); -} - -//-------------------TST---------------------------- - -#define OP_TST(a) \ - { \ - unsigned tmp = cpu->R[REG_POS(i,16)] & shift_op;\ - cpu->CPSR.bits.C = c;\ - cpu->CPSR.bits.N = BIT31(tmp);\ - cpu->CPSR.bits.Z = (tmp==0);\ - return a; \ - } - -TEMPLATE static u32 FASTCALL OP_TST_LSL_IMM() -{ - const u32 &i = cpu->instruction; - S_LSL_IMM; - OP_TST(1); -} - -TEMPLATE static u32 FASTCALL OP_TST_LSL_REG() -{ - const u32 &i = cpu->instruction; - S_LSL_REG; - OP_TST(2); -} - -TEMPLATE static u32 FASTCALL OP_TST_LSR_IMM() -{ - const u32 &i = cpu->instruction; - S_LSR_IMM; - OP_TST(1); -} - -TEMPLATE static u32 FASTCALL OP_TST_LSR_REG() -{ - const u32 &i = cpu->instruction; - S_LSR_REG; - OP_TST(2); -} - -TEMPLATE static u32 FASTCALL OP_TST_ASR_IMM() -{ - const u32 &i = cpu->instruction; - S_ASR_IMM; - OP_TST(1); -} - -TEMPLATE static u32 FASTCALL OP_TST_ASR_REG() -{ - const u32 &i = cpu->instruction; - S_ASR_REG; - OP_TST(2); -} - -TEMPLATE static u32 FASTCALL OP_TST_ROR_IMM() -{ - const u32 &i = cpu->instruction; - S_ROR_IMM; - OP_TST(1); -} - -TEMPLATE static u32 FASTCALL OP_TST_ROR_REG() -{ - const u32 &i = cpu->instruction; - S_ROR_REG; - OP_TST(2); -} - -TEMPLATE static u32 FASTCALL OP_TST_IMM_VAL() -{ - const u32 &i = cpu->instruction; - S_IMM_VALUE; - OP_TST(1); -} - -//-------------------TEQ---------------------------- - -#define OP_TEQ(a) \ - { \ - unsigned tmp = cpu->R[REG_POS(i,16)] ^ shift_op;\ - cpu->CPSR.bits.C = c;\ - cpu->CPSR.bits.N = BIT31(tmp);\ - cpu->CPSR.bits.Z = (tmp==0);\ - return a; \ - } - -TEMPLATE static u32 FASTCALL OP_TEQ_LSL_IMM() -{ - const u32 &i = cpu->instruction; - S_LSL_IMM; - OP_TEQ(1); -} - -TEMPLATE static u32 FASTCALL OP_TEQ_LSL_REG() -{ - const u32 &i = cpu->instruction; - S_LSL_REG; - OP_TEQ(2); -} - -TEMPLATE static u32 FASTCALL OP_TEQ_LSR_IMM() -{ - const u32 &i = cpu->instruction; - S_LSR_IMM; - OP_TEQ(1); -} - -TEMPLATE static u32 FASTCALL OP_TEQ_LSR_REG() -{ - const u32 &i = cpu->instruction; - S_LSR_REG; - OP_TEQ(2); -} - -TEMPLATE static u32 FASTCALL OP_TEQ_ASR_IMM() -{ - const u32 &i = cpu->instruction; - S_ASR_IMM; - OP_TEQ(1); -} - -TEMPLATE static u32 FASTCALL OP_TEQ_ASR_REG() -{ - const u32 &i = cpu->instruction; - S_ASR_REG; - OP_TEQ(2); -} - -TEMPLATE static u32 FASTCALL OP_TEQ_ROR_IMM() -{ - const u32 &i = cpu->instruction; - S_ROR_IMM; - OP_TEQ(1); -} - -TEMPLATE static u32 FASTCALL OP_TEQ_ROR_REG() -{ - const u32 &i = cpu->instruction; - S_ROR_REG; - OP_TEQ(2); -} - -TEMPLATE static u32 FASTCALL OP_TEQ_IMM_VAL() -{ - const u32 &i = cpu->instruction; - S_IMM_VALUE; - OP_TEQ(1); -} - -//-------------CMP------------------------------------- - -#define OP_CMP(a) \ - { \ - u32 tmp = cpu->R[REG_POS(i,16)] - shift_op;\ - cpu->CPSR.bits.N = BIT31(tmp);\ - cpu->CPSR.bits.Z = (tmp==0);\ - cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(cpu->R[REG_POS(i,16)], shift_op, tmp);\ - cpu->CPSR.bits.V = SIGNED_UNDERFLOW(cpu->R[REG_POS(i,16)], shift_op, tmp);\ - return a; \ - } - -TEMPLATE static u32 FASTCALL OP_CMP_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSL_IMM; - OP_CMP(1); -} - -TEMPLATE static u32 FASTCALL OP_CMP_LSL_REG() -{ - const u32 &i = cpu->instruction; - LSL_REG; - OP_CMP(2); -} - -TEMPLATE static u32 FASTCALL OP_CMP_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSR_IMM; - OP_CMP(1); -} - -TEMPLATE static u32 FASTCALL OP_CMP_LSR_REG() -{ - const u32 &i = cpu->instruction; - LSR_REG; - OP_CMP(2); -} - -TEMPLATE static u32 FASTCALL OP_CMP_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ASR_IMM; - OP_CMP(1); -} - -TEMPLATE static u32 FASTCALL OP_CMP_ASR_REG() -{ - const u32 &i = cpu->instruction; - ASR_REG; - OP_CMP(2); -} - -TEMPLATE static u32 FASTCALL OP_CMP_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ROR_IMM; - OP_CMP(1); -} - -TEMPLATE static u32 FASTCALL OP_CMP_ROR_REG() -{ - const u32 &i = cpu->instruction; - ROR_REG; - OP_CMP(2); -} - -TEMPLATE static u32 FASTCALL OP_CMP_IMM_VAL() -{ - const u32 &i = cpu->instruction; - IMM_VALUE; - OP_CMP(1); -} - -//---------------CMN--------------------------- - -#define OP_CMN(a) \ - { \ - u32 tmp = cpu->R[REG_POS(i,16)] + shift_op;\ - cpu->CPSR.bits.N = BIT31(tmp);\ - cpu->CPSR.bits.Z = (tmp==0);\ - cpu->CPSR.bits.C = UNSIGNED_OVERFLOW(cpu->R[REG_POS(i,16)], shift_op, tmp);\ - cpu->CPSR.bits.V = SIGNED_OVERFLOW(cpu->R[REG_POS(i,16)], shift_op, tmp);\ - return a; \ - } - -TEMPLATE static u32 FASTCALL OP_CMN_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSL_IMM; - OP_CMN(1); -} - -TEMPLATE static u32 FASTCALL OP_CMN_LSL_REG() -{ - const u32 &i = cpu->instruction; - LSL_REG; - OP_CMN(2); -} - -TEMPLATE static u32 FASTCALL OP_CMN_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSR_IMM; - OP_CMN(1); -} - -TEMPLATE static u32 FASTCALL OP_CMN_LSR_REG() -{ - const u32 &i = cpu->instruction; - LSR_REG; - OP_CMN(2); -} - -TEMPLATE static u32 FASTCALL OP_CMN_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ASR_IMM; - OP_CMN(1); -} - -TEMPLATE static u32 FASTCALL OP_CMN_ASR_REG() -{ - const u32 &i = cpu->instruction; - ASR_REG; - OP_CMN(2); -} - -TEMPLATE static u32 FASTCALL OP_CMN_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ROR_IMM; - OP_CMN(1); -} - -TEMPLATE static u32 FASTCALL OP_CMN_ROR_REG() -{ - const u32 &i = cpu->instruction; - ROR_REG; - OP_CMN(2); -} - -TEMPLATE static u32 FASTCALL OP_CMN_IMM_VAL() -{ - const u32 &i = cpu->instruction; - IMM_VALUE; - OP_CMN(1); -} - -//------------------ORR------------------- - -#define OP_ORR(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] | shift_op;\ - if(REG_POS(i,12)==15)\ - {\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - return a; - -TEMPLATE static u32 FASTCALL OP_ORR_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSL_IMM; - OP_ORR(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_ORR_LSL_REG() -{ - const u32 &i = cpu->instruction; - LSL_REG; - OP_ORR(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ORR_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSR_IMM; - OP_ORR(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_ORR_LSR_REG() -{ - const u32 &i = cpu->instruction; - LSR_REG; - OP_ORR(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ORR_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ASR_IMM; - OP_ORR(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_ORR_ASR_REG() -{ - const u32 &i = cpu->instruction; - ASR_REG; - OP_ORR(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ORR_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ROR_IMM; - OP_ORR(1, 3); -} - -TEMPLATE static u32 FASTCALL OP_ORR_ROR_REG() -{ - const u32 &i = cpu->instruction; - ROR_REG; - OP_ORR(2, 4); -} - -TEMPLATE static u32 FASTCALL OP_ORR_IMM_VAL() -{ - const u32 &i = cpu->instruction; - IMM_VALUE; - OP_ORR(1, 3); -} - -#define OP_ORRS(a,b) \ - { \ - cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] | shift_op; \ - if(REG_POS(i,12)==15) \ - { \ - Status_Reg SPSR = cpu->SPSR; \ - armcpu_switchMode(cpu, SPSR.bits.mode); \ - cpu->CPSR=SPSR; \ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1)); \ - cpu->next_instruction = cpu->R[15]; \ - return b; \ - } \ - cpu->CPSR.bits.C = c; \ - cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \ - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \ - return a; \ - } - -TEMPLATE static u32 FASTCALL OP_ORR_S_LSL_IMM() -{ - const u32 &i = cpu->instruction; - S_LSL_IMM; - OP_ORRS(2,4); -} - -TEMPLATE static u32 FASTCALL OP_ORR_S_LSL_REG() -{ - const u32 &i = cpu->instruction; - S_LSL_REG; - OP_ORRS(3,5); -} - -TEMPLATE static u32 FASTCALL OP_ORR_S_LSR_IMM() -{ - const u32 &i = cpu->instruction; - S_LSR_IMM; - OP_ORRS(2,4); -} - -TEMPLATE static u32 FASTCALL OP_ORR_S_LSR_REG() -{ - const u32 &i = cpu->instruction; - S_LSR_REG; - OP_ORRS(3,5); -} - -TEMPLATE static u32 FASTCALL OP_ORR_S_ASR_IMM() -{ - const u32 &i = cpu->instruction; - S_ASR_IMM; - OP_ORRS(2,4); -} - -TEMPLATE static u32 FASTCALL OP_ORR_S_ASR_REG() -{ - const u32 &i = cpu->instruction; - S_ASR_REG; - OP_ORRS(3,5); -} - -TEMPLATE static u32 FASTCALL OP_ORR_S_ROR_IMM() -{ - const u32 &i = cpu->instruction; - S_ROR_IMM; - OP_ORRS(2,4); -} - -TEMPLATE static u32 FASTCALL OP_ORR_S_ROR_REG() -{ - const u32 &i = cpu->instruction; - S_ROR_REG; - OP_ORRS(3,5); -} - -TEMPLATE static u32 FASTCALL OP_ORR_S_IMM_VAL() -{ - const u32 &i = cpu->instruction; - S_IMM_VALUE; - OP_ORRS(2,4); -} - -//------------------MOV------------------- - -#define OP_MOV(a, b) cpu->R[REG_POS(i,12)] = shift_op;\ - if(REG_POS(i,12)==15)\ - {\ - cpu->next_instruction = shift_op;\ - return b;\ - }\ - return a; - -#define OP_MOV_S(a, b) cpu->R[REG_POS(i,12)] = shift_op;\ - if(BIT20(i) && REG_POS(i,12)==15)\ - {\ - Status_Reg SPSR = cpu->SPSR;\ - armcpu_switchMode(cpu, SPSR.bits.mode);\ - cpu->CPSR=SPSR;\ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - cpu->CPSR.bits.C = c;\ - cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ - return a;\ - -TEMPLATE static u32 FASTCALL OP_MOV_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSL_IMM; - OP_MOV(1,3); -} - -TEMPLATE static u32 FASTCALL OP_MOV_LSL_REG() -{ - const u32 &i = cpu->instruction; - LSL_REG; - if (REG_POS(i,0) == 15) shift_op += 4; - OP_MOV(2,4); -} - -TEMPLATE static u32 FASTCALL OP_MOV_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSR_IMM; - OP_MOV(1,3); -} - -TEMPLATE static u32 FASTCALL OP_MOV_LSR_REG() -{ - const u32 &i = cpu->instruction; - LSR_REG; - if (REG_POS(i,0) == 15) shift_op += 4; - OP_MOV(2,4); -} - -TEMPLATE static u32 FASTCALL OP_MOV_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ASR_IMM; - OP_MOV(1,3); -} - -TEMPLATE static u32 FASTCALL OP_MOV_ASR_REG() -{ - const u32 &i = cpu->instruction; - ASR_REG; - OP_MOV(2,4); -} - -TEMPLATE static u32 FASTCALL OP_MOV_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ROR_IMM; - OP_MOV(2,4); -} - -TEMPLATE static u32 FASTCALL OP_MOV_ROR_REG() -{ - const u32 &i = cpu->instruction; - ROR_REG; - OP_MOV(2,4); -} - -TEMPLATE static u32 FASTCALL OP_MOV_IMM_VAL() -{ - const u32 &i = cpu->instruction; - IMM_VALUE; - OP_MOV(1,3); -} - -TEMPLATE static u32 FASTCALL OP_MOV_S_LSL_IMM() -{ - const u32 &i = cpu->instruction; - S_LSL_IMM; - OP_MOV_S(2,4); -} - -TEMPLATE static u32 FASTCALL OP_MOV_S_LSL_REG() -{ - const u32 &i = cpu->instruction; - S_LSL_REG; - if (REG_POS(i,0) == 15) shift_op += 4; - OP_MOV_S(3,5); -} - -TEMPLATE static u32 FASTCALL OP_MOV_S_LSR_IMM() -{ - const u32 &i = cpu->instruction; - S_LSR_IMM; - OP_MOV_S(2,4); -} - -TEMPLATE static u32 FASTCALL OP_MOV_S_LSR_REG() -{ - const u32 &i = cpu->instruction; - S_LSR_REG; - if (REG_POS(i,0) == 15) shift_op += 4; - OP_MOV_S(3,5); -} - -TEMPLATE static u32 FASTCALL OP_MOV_S_ASR_IMM() -{ - const u32 &i = cpu->instruction; - S_ASR_IMM; - OP_MOV_S(2,4); -} - -TEMPLATE static u32 FASTCALL OP_MOV_S_ASR_REG() -{ - const u32 &i = cpu->instruction; - S_ASR_REG; - OP_MOV_S(3,5); -} - -TEMPLATE static u32 FASTCALL OP_MOV_S_ROR_IMM() -{ - const u32 &i = cpu->instruction; - S_ROR_IMM; - OP_MOV_S(2,4); -} - -TEMPLATE static u32 FASTCALL OP_MOV_S_ROR_REG() -{ - const u32 &i = cpu->instruction; - S_ROR_REG; - OP_MOV_S(3,5); -} - -TEMPLATE static u32 FASTCALL OP_MOV_S_IMM_VAL() -{ - const u32 &i = cpu->instruction; - S_IMM_VALUE; - OP_MOV_S(2,4); -} - -//------------------BIC------------------- -#define OPP_BIC(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] & (~shift_op);\ - if(REG_POS(i,12)==15)\ - {\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - return a; - -#define OPP_BIC_S(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] & (~shift_op);\ - if(REG_POS(i,12)==15)\ - {\ - Status_Reg SPSR = cpu->SPSR;\ - armcpu_switchMode(cpu, SPSR.bits.mode);\ - cpu->CPSR=SPSR;\ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - cpu->CPSR.bits.C = c;\ - cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ - return a; - -TEMPLATE static u32 FASTCALL OP_BIC_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSL_IMM; - OPP_BIC(1,3); -} - -TEMPLATE static u32 FASTCALL OP_BIC_LSL_REG() -{ - const u32 &i = cpu->instruction; - LSL_REG; - OPP_BIC(2,4); -} - -TEMPLATE static u32 FASTCALL OP_BIC_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSR_IMM; - OPP_BIC(1,3); -} - -TEMPLATE static u32 FASTCALL OP_BIC_LSR_REG() -{ - const u32 &i = cpu->instruction; - LSR_REG; - OPP_BIC(2,4); -} - -TEMPLATE static u32 FASTCALL OP_BIC_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ASR_IMM; - OPP_BIC(1,3); -} - -TEMPLATE static u32 FASTCALL OP_BIC_ASR_REG() -{ - const u32 &i = cpu->instruction; - ASR_REG; - OPP_BIC(2,4); -} - -TEMPLATE static u32 FASTCALL OP_BIC_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ROR_IMM; - OPP_BIC(1,3); -} - -TEMPLATE static u32 FASTCALL OP_BIC_ROR_REG() -{ - const u32 &i = cpu->instruction; - ROR_REG; - OPP_BIC(2,4); -} - -TEMPLATE static u32 FASTCALL OP_BIC_IMM_VAL() -{ - const u32 &i = cpu->instruction; - IMM_VALUE; - OPP_BIC(1,3); -} - -TEMPLATE static u32 FASTCALL OP_BIC_S_LSL_IMM() -{ - const u32 &i = cpu->instruction; - S_LSL_IMM; - OPP_BIC_S(2,4); -} - -TEMPLATE static u32 FASTCALL OP_BIC_S_LSL_REG() -{ - const u32 &i = cpu->instruction; - S_LSL_REG; - OPP_BIC_S(3,5); -} - -TEMPLATE static u32 FASTCALL OP_BIC_S_LSR_IMM() -{ - const u32 &i = cpu->instruction; - S_LSR_IMM; - OPP_BIC_S(2,4); -} - -TEMPLATE static u32 FASTCALL OP_BIC_S_LSR_REG() -{ - const u32 &i = cpu->instruction; - S_LSR_REG; - OPP_BIC_S(3,5); -} - -TEMPLATE static u32 FASTCALL OP_BIC_S_ASR_IMM() -{ - const u32 &i = cpu->instruction; - S_ASR_IMM; - OPP_BIC_S(2,4); -} - -TEMPLATE static u32 FASTCALL OP_BIC_S_ASR_REG() -{ - const u32 &i = cpu->instruction; - S_ASR_REG; - OPP_BIC_S(3,5); -} - -TEMPLATE static u32 FASTCALL OP_BIC_S_ROR_IMM() -{ - const u32 &i = cpu->instruction; - S_ROR_IMM; - OPP_BIC_S(2,4); -} - -TEMPLATE static u32 FASTCALL OP_BIC_S_ROR_REG() -{ - const u32 &i = cpu->instruction; - S_ROR_REG; - OPP_BIC_S(3,5); -} - -TEMPLATE static u32 FASTCALL OP_BIC_S_IMM_VAL() -{ - const u32 &i = cpu->instruction; - S_IMM_VALUE; - OPP_BIC_S(2,4); -} - -//------------------MVN------------------- -#define OPP_MVN(a, b) cpu->R[REG_POS(i,12)] = ~shift_op;\ - if(REG_POS(i,12)==15)\ - {\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - return a; - -#define OPP_MVN_S(a, b) cpu->R[REG_POS(i,12)] = ~shift_op;\ - if(REG_POS(i,12)==15)\ - {\ - Status_Reg SPSR = cpu->SPSR;\ - armcpu_switchMode(cpu, SPSR.bits.mode);\ - cpu->CPSR=SPSR;\ - cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ - cpu->next_instruction = cpu->R[15];\ - return b;\ - }\ - cpu->CPSR.bits.C = c;\ - cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ - return a; - -TEMPLATE static u32 FASTCALL OP_MVN_LSL_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSL_IMM; - OPP_MVN(1,3); -} - -TEMPLATE static u32 FASTCALL OP_MVN_LSL_REG() -{ - const u32 &i = cpu->instruction; - LSL_REG; - OPP_MVN(2,4); -} - -TEMPLATE static u32 FASTCALL OP_MVN_LSR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - LSR_IMM; - OPP_MVN(1,3); -} - -TEMPLATE static u32 FASTCALL OP_MVN_LSR_REG() -{ - const u32 &i = cpu->instruction; - LSR_REG; - OPP_MVN(2,4); -} - -TEMPLATE static u32 FASTCALL OP_MVN_ASR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ASR_IMM; - OPP_MVN(1,3); -} - -TEMPLATE static u32 FASTCALL OP_MVN_ASR_REG() -{ - const u32 &i = cpu->instruction; - ASR_REG; - OPP_MVN(2,4); -} - -TEMPLATE static u32 FASTCALL OP_MVN_ROR_IMM() -{ - const u32 &i = cpu->instruction; - u32 shift_op; - ROR_IMM; - OPP_MVN(1,3); -} - -TEMPLATE static u32 FASTCALL OP_MVN_ROR_REG() -{ - const u32 &i = cpu->instruction; - ROR_REG; - OPP_MVN(2,4); -} - -TEMPLATE static u32 FASTCALL OP_MVN_IMM_VAL() -{ - const u32 &i = cpu->instruction; - IMM_VALUE; - OPP_MVN(1,3); -} - -TEMPLATE static u32 FASTCALL OP_MVN_S_LSL_IMM() -{ - const u32 &i = cpu->instruction; - S_LSL_IMM; - OPP_MVN_S(2,4); -} - -TEMPLATE static u32 FASTCALL OP_MVN_S_LSL_REG() -{ - const u32 &i = cpu->instruction; - S_LSL_REG; - OPP_MVN_S(3,5); -} - -TEMPLATE static u32 FASTCALL OP_MVN_S_LSR_IMM() -{ - const u32 &i = cpu->instruction; - S_LSR_IMM; - OPP_MVN_S(2,4); -} - -TEMPLATE static u32 FASTCALL OP_MVN_S_LSR_REG() -{ - const u32 &i = cpu->instruction; - S_LSR_REG; - OPP_MVN_S(3,5); -} - -TEMPLATE static u32 FASTCALL OP_MVN_S_ASR_IMM() -{ - const u32 &i = cpu->instruction; - S_ASR_IMM; - OPP_MVN_S(2,4); -} - -TEMPLATE static u32 FASTCALL OP_MVN_S_ASR_REG() -{ - const u32 &i = cpu->instruction; - S_ASR_REG; - OPP_MVN_S(3,5); -} - -TEMPLATE static u32 FASTCALL OP_MVN_S_ROR_IMM() -{ - const u32 &i = cpu->instruction; - S_ROR_IMM; - OPP_MVN_S(2,4); -} - -TEMPLATE static u32 FASTCALL OP_MVN_S_ROR_REG() -{ - const u32 &i = cpu->instruction; - S_ROR_REG; - OPP_MVN_S(3,5); -} - -TEMPLATE static u32 FASTCALL OP_MVN_S_IMM_VAL() -{ - const u32 &i = cpu->instruction; - S_IMM_VALUE; - OPP_MVN_S(2,4); -} - -//-------------MUL------------------------ -#define OPP_M(a,b) v >>= 8;\ - if((v==0)||(v==0xFFFFFF))\ - return b;\ - v >>= 8;\ - if((v==0)||(v==0xFFFF))\ - return b+1;\ - v >>= 8;\ - if((v==0)||(v==0xFF))\ - return b+2;\ - return a;\ - -TEMPLATE static u32 FASTCALL OP_MUL() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,16)] = cpu->R[REG_POS(i,8)] * v; - OPP_M(5,2); -} - -TEMPLATE static u32 FASTCALL OP_MLA() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,0)]; - u32 a = cpu->R[REG_POS(i,8)]; - u32 b = cpu->R[REG_POS(i,12)]; - cpu->R[REG_POS(i,16)] = a * v + b; - - OPP_M(6,3); -} - -TEMPLATE static u32 FASTCALL OP_MUL_S() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,16)] = cpu->R[REG_POS(i,8)] * v; - - cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]); - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0); - - OPP_M(6,3); -} - -TEMPLATE static u32 FASTCALL OP_MLA_S() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,16)] = cpu->R[REG_POS(i,8)] * v + cpu->R[REG_POS(i,12)]; - cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]); - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0); - OPP_M(7,4); -} - -//----------UMUL-------------------------- - -TEMPLATE static u32 FASTCALL OP_UMULL() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,0)]; - u64 res = (u64)v * (u64)cpu->R[REG_POS(i,8)]; - - cpu->R[REG_POS(i,12)] = (u32)res; - cpu->R[REG_POS(i,16)] = (u32)(res>>32); - - OPP_M(6,3); -} - -TEMPLATE static u32 FASTCALL OP_UMLAL() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,0)]; - u64 res = (u64)v * (u64)cpu->R[REG_POS(i,8)] + (u64)cpu->R[REG_POS(i,12)]; - - cpu->R[REG_POS(i,12)] = (u32)res; - cpu->R[REG_POS(i,16)] += (u32)(res>>32); - - OPP_M(7,4); -} - -TEMPLATE static u32 FASTCALL OP_UMULL_S() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,0)]; - u64 res = (u64)v * (u64)cpu->R[REG_POS(i,8)]; - - cpu->R[REG_POS(i,12)] = (u32)res; - cpu->R[REG_POS(i,16)] = (u32)(res>>32); - - cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]); - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0); - - OPP_M(7,4); -} - -TEMPLATE static u32 FASTCALL OP_UMLAL_S() -{ - const u32 &i = cpu->instruction; - u32 v = cpu->R[REG_POS(i,0)]; - u64 res = (u64)v * (u64)cpu->R[REG_POS(i,8)] + (u64)cpu->R[REG_POS(i,12)]; - - cpu->R[REG_POS(i,12)] = (u32)res; - cpu->R[REG_POS(i,16)] += (u32)(res>>32); - - cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]); - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0); - - OPP_M(8,5); -} - -//----------SMUL-------------------------- - -TEMPLATE static u32 FASTCALL OP_SMULL() -{ - const u32 &i = cpu->instruction; - s64 v = (s32)cpu->R[REG_POS(i,0)]; - s64 b = (s32)cpu->R[REG_POS(i,8)]; - s64 res = v * b; - - cpu->R[REG_POS(i,12)] = (u32)(res&0xFFFFFFFF); - cpu->R[REG_POS(i,16)] = (u32)(res>>32); - - v &= 0xFFFFFFFF; - - OPP_M(6,3); -} - -TEMPLATE static u32 FASTCALL OP_SMLAL() -{ - const u32 &i = cpu->instruction; - - s64 v = (s32)cpu->R[REG_POS(i,0)]; - s64 b = (s32)cpu->R[REG_POS(i,8)]; - s64 res = v * b + (u64)cpu->R[REG_POS(i,12)]; - - //LOG("%08X * %08X + %08X%08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], cpu->R[REG_POS(i,16)], cpu->R[REG_POS(i,12)]); - - cpu->R[REG_POS(i,12)] = (u32)res; - cpu->R[REG_POS(i,16)] += (u32)(res>>32); - - //LOG("= %08X%08X %08X%08X\r\n", cpu->R[REG_POS(i,16)], cpu->R[REG_POS(i,12)], res); - - v &= 0xFFFFFFFF; - - OPP_M(7,4); -} - -TEMPLATE static u32 FASTCALL OP_SMULL_S() -{ - const u32 &i = cpu->instruction; - s64 v = (s32)cpu->R[REG_POS(i,0)]; - s64 b = (s32)cpu->R[REG_POS(i,8)]; - s64 res = v * b; - - cpu->R[REG_POS(i,12)] = (u32)res; - cpu->R[REG_POS(i,16)] = (u32)(res>>32); - - cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]); - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0); - - v &= 0xFFFFFFFF; - - OPP_M(7,4); -} - -TEMPLATE static u32 FASTCALL OP_SMLAL_S() -{ - const u32 &i = cpu->instruction; - s64 v = (s32)cpu->R[REG_POS(i,0)]; - s64 b = (s32)cpu->R[REG_POS(i,8)]; - s64 res = v * b + (u64)cpu->R[REG_POS(i,12)]; - - cpu->R[REG_POS(i,12)] = (u32)res; - cpu->R[REG_POS(i,16)] += (u32)(res>>32); - - cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]); - cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0); - - v &= 0xFFFFFFFF; - - OPP_M(8,5); -} - -//---------------SWP------------------------------ - -TEMPLATE static u32 FASTCALL OP_SWP() -{ - u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - u32 tmp = ROR(READ32(cpu->mem_if->data, adr), ((cpu->R[REG_POS(i,16)]&3)<<3)); - - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,0)]); - cpu->R[REG_POS(i,12)] = tmp; - - return 4 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]*2; -} - -TEMPLATE static u32 FASTCALL OP_SWPB() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - u8 tmp = READ8(cpu->mem_if->data, adr); - WRITE8(cpu->mem_if->data, adr, (u8)(cpu->R[REG_POS(i,0)]&0xFF)); - cpu->R[REG_POS(i,12)] = tmp; - - return 4 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]*2; -} - -//------------LDRH----------------------------- - -TEMPLATE static u32 FASTCALL OP_LDRH_P_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; - cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRH_M_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; - cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRH_P_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRH_M_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_P_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_M_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_P_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] =(u32)READ16(cpu->mem_if->data, adr); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_M_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_P_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] += IMM_OFF; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_M_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] -= IMM_OFF; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_P_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_M_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -//------------STRH----------------------------- - -TEMPLATE static u32 FASTCALL OP_STRH_P_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; - WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRH_M_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; - WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRH_P_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; - WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRH_M_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; - WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_P_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; - cpu->R[REG_POS(i,16)] = adr; - WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_M_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; - WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_P_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; - WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_M_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; - WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_P_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] += IMM_OFF; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_M_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] -= IMM_OFF; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_P_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_M_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -//----------------LDRSH-------------------------- - -TEMPLATE static u32 FASTCALL OP_LDRSH_P_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; - cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSH_M_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; - cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSH_P_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSH_M_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_P_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; - cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - cpu->R[REG_POS(i,16)] = adr; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_M_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; - cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - cpu->R[REG_POS(i,16)] = adr; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_P_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - cpu->R[REG_POS(i,16)] = adr; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_M_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - cpu->R[REG_POS(i,16)] = adr; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_P_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - cpu->R[REG_POS(i,16)] += IMM_OFF; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_M_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - cpu->R[REG_POS(i,16)] -= IMM_OFF; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_P_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_M_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); - cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -//----------------------LDRSB---------------------- - -TEMPLATE static u32 FASTCALL OP_LDRSB_P_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; - cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSB_M_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; - cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSB_P_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSB_M_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_P_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; - cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - cpu->R[REG_POS(i,16)] = adr; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_M_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; - cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - cpu->R[REG_POS(i,16)] = adr; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_P_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - cpu->R[REG_POS(i,16)] = adr; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_M_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; - cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - cpu->R[REG_POS(i,16)] = adr; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_P_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - cpu->R[REG_POS(i,16)] += IMM_OFF; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_M_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - cpu->R[REG_POS(i,16)] -= IMM_OFF; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_P_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_M_REG_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); - cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -//--------------MRS-------------------------------- - -TEMPLATE static u32 FASTCALL OP_MRS_CPSR() -{ - cpu->R[REG_POS(cpu->instruction,12)] = cpu->CPSR.val; - - return 1; -} - -TEMPLATE static u32 FASTCALL OP_MRS_SPSR() -{ - cpu->R[REG_POS(cpu->instruction,12)] = cpu->SPSR.val; - - return 1; -} - -//--------------MSR-------------------------------- - -TEMPLATE static u32 FASTCALL OP_MSR_CPSR() -{ - const u32 &i = cpu->instruction; - u32 operand = cpu->R[REG_POS(i,0)]; - - if(cpu->CPSR.bits.mode!=USR) - { - if(BIT16(i)) - { - armcpu_switchMode(cpu, operand & 0x1F); - cpu->CPSR.val = (cpu->CPSR.val & 0xFFFFFF00) | (operand & 0xFF); - } - if(BIT17(i)) - cpu->CPSR.val = (cpu->CPSR.val & 0xFFFF00FF) | (operand & 0xFF00); - if(BIT18(i)) - cpu->CPSR.val = (cpu->CPSR.val & 0xFF00FFFF) | (operand & 0xFF0000); - } - if(BIT19(i)) - cpu->CPSR.val = (cpu->CPSR.val & 0x00FFFFFF) | (operand & 0xFF000000); - - return 1; -} - -TEMPLATE static u32 FASTCALL OP_MSR_SPSR() -{ - const u32 &i = cpu->instruction; - u32 operand = cpu->R[REG_POS(i,0)]; - - if(cpu->CPSR.bits.mode!=USR) - { - if(BIT16(i)) - { - cpu->SPSR.val = (cpu->SPSR.val & 0xFFFFFF00) | (operand & 0XFF); - } - if(BIT17(i)) - cpu->SPSR.val = (cpu->SPSR.val & 0xFFFF00FF) | (operand & 0XFF00); - if(BIT18(i)) - cpu->SPSR.val = (cpu->SPSR.val & 0xFF00FFFF) | (operand & 0XFF0000); - } - if(BIT19(i)) - cpu->SPSR.val = (cpu->SPSR.val & 0x00FFFFFF) | (operand & 0XFF000000); - - return 1; -} - -TEMPLATE static u32 FASTCALL OP_MSR_CPSR_IMM_VAL() -{ - const u32 &i = cpu->instruction; - IMM_VALUE; - - if(cpu->CPSR.bits.mode!=USR) - { - if(BIT16(i)) - { - armcpu_switchMode(cpu, shift_op & 0x1F); - cpu->CPSR.val = (cpu->CPSR.val & 0xFFFFFF00) | (shift_op & 0XFF); - } - if(BIT17(i)) - cpu->CPSR.val = (cpu->CPSR.val & 0xFFFF00FF) | (shift_op & 0XFF00); - if(BIT18(i)) - cpu->CPSR.val = (cpu->CPSR.val & 0xFF00FFFF) | (shift_op & 0XFF0000); - } - if(BIT19(i)) - { - //cpu->CPSR.val = (cpu->CPSR.val & 0xFF000000) | (shift_op & 0XFF000000); - cpu->CPSR.val = (cpu->CPSR.val & 0x00FFFFFF) | (shift_op & 0xFF000000); - } - - return 1; -} - -TEMPLATE static u32 FASTCALL OP_MSR_SPSR_IMM_VAL() -{ - const u32 &i = cpu->instruction; - IMM_VALUE; - - if(cpu->CPSR.bits.mode!=USR) - { - if(BIT16(i)) - { - cpu->SPSR.val = (cpu->SPSR.val & 0xFFFFFF00) | (shift_op & 0XFF); - } - if(BIT17(i)) - cpu->SPSR.val = (cpu->SPSR.val & 0xFFFF00FF) | (shift_op & 0XFF00); - if(BIT18(i)) - cpu->SPSR.val = (cpu->SPSR.val & 0xFF00FFFF) | (shift_op & 0XFF0000); - } - if(BIT19(i)) - cpu->SPSR.val = (cpu->SPSR.val & 0xFF000000) | (shift_op & 0XFF000000); - - return 1; -} - -//-----------------BRANCH-------------------------- - -TEMPLATE static u32 FASTCALL OP_BX() -{ - u32 tmp = cpu->R[REG_POS(cpu->instruction, 0)]; - - cpu->CPSR.bits.T = BIT0(tmp); - cpu->R[15] = tmp & 0xFFFFFFFE; - cpu->next_instruction = cpu->R[15]; - return 3; -} - -TEMPLATE static u32 FASTCALL OP_BLX_REG() -{ - u32 tmp = cpu->R[REG_POS(cpu->instruction, 0)]; - - cpu->R[14] = cpu->next_instruction; - cpu->CPSR.bits.T = BIT0(tmp); - cpu->R[15] = tmp & 0xFFFFFFFE; - cpu->next_instruction = cpu->R[15]; - return 3; -} - -#define SIGNEXTEND_24(i) (((s32)((i)<<8))>>8) - -TEMPLATE static u32 FASTCALL OP_B() -{ - u32 off = SIGNEXTEND_24(cpu->instruction); - if(CONDITION(cpu->instruction)==0xF) - { - cpu->R[14] = cpu->next_instruction; - cpu->CPSR.bits.T = 1; - } - cpu->R[15] += (off<<2); - cpu->next_instruction = cpu->R[15]; - - return 3; -} - -TEMPLATE static u32 FASTCALL OP_BL() -{ - u32 off = SIGNEXTEND_24(cpu->instruction); - if(CONDITION(cpu->instruction)==0xF) - { - cpu->CPSR.bits.T = 1; - cpu->R[15] += 2; - } - cpu->R[14] = cpu->next_instruction; - cpu->R[15] += (off<<2); - cpu->next_instruction = cpu->R[15]; - - return 3; -} - -//----------------CLZ------------------------------- - -u8 CLZ_TAB[16]= -{ - 0, // 0000 - 1, // 0001 - 2, 2, // 001X - 3, 3, 3, 3, // 01XX - 4, 4, 4, 4, 4, 4, 4, 4 // 1XXX -}; - -TEMPLATE static u32 FASTCALL OP_CLZ() -{ - const u32 &i = cpu->instruction; - u32 Rm = cpu->R[REG_POS(i,0)]; - u32 pos; - - if(Rm==0) - { - cpu->R[REG_POS(i,12)]=32; - return 2; - } - - Rm |= (Rm >>1); - Rm |= (Rm >>2); - Rm |= (Rm >>4); - Rm |= (Rm >>8); - Rm |= (Rm >>16); - - pos = - CLZ_TAB[Rm&0xF] + - CLZ_TAB[(Rm>>4)&0xF] + - CLZ_TAB[(Rm>>8)&0xF] + - CLZ_TAB[(Rm>>12)&0xF] + - CLZ_TAB[(Rm>>16)&0xF] + - CLZ_TAB[(Rm>>20)&0xF] + - CLZ_TAB[(Rm>>24)&0xF] + - CLZ_TAB[(Rm>>28)&0xF]; - - cpu->R[REG_POS(i,12)]=32 - pos; - - return 2; -} - -//--------------------QADD--QSUB------------------------------ - -TEMPLATE static u32 FASTCALL OP_QADD() -{ - const u32 &i = cpu->instruction; - u32 res = cpu->R[REG_POS(i,16)]+cpu->R[REG_POS(i,0)]; - - LOG("spe add\r\n"); - if(SIGNED_OVERFLOW(cpu->R[REG_POS(i,16)],cpu->R[REG_POS(i,0)], res)) - { - cpu->CPSR.bits.Q=1; - cpu->R[REG_POS(i,12)]=0x80000000-BIT31(res); - return 2; - } - cpu->R[REG_POS(i,12)]=res; - if(REG_POS(i,12)==15) - { - cpu->R[15] &= 0XFFFFFFFC; - cpu->next_instruction = cpu->R[15]; - return 3; - } - return 2; -} - -TEMPLATE static u32 FASTCALL OP_QSUB() -{ - const u32 &i = cpu->instruction; - u32 res = cpu->R[REG_POS(i,0)]-cpu->R[REG_POS(i,16)]; - - LOG("spe add\r\n"); - if(SIGNED_UNDERFLOW(cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,16)], res)) - { - cpu->CPSR.bits.Q=1; - cpu->R[REG_POS(i,12)]=0x80000000-BIT31(res); - return 2; - } - cpu->R[REG_POS(i,12)]=res; - if(REG_POS(i,12)==15) - { - cpu->R[15] &= 0XFFFFFFFC; - cpu->next_instruction = cpu->R[15]; - return 3; - } - return 2; -} - -TEMPLATE static u32 FASTCALL OP_QDADD() -{ - const u32 &i = cpu->instruction; - u32 mul = cpu->R[REG_POS(i,16)]<<1; - u32 res; - - - LOG("spe add\r\n"); - if(BIT31(cpu->R[REG_POS(i,16)])!=BIT31(mul)) - { - cpu->CPSR.bits.Q=1; - mul = 0x80000000-BIT31(mul); - } - - res = mul + cpu->R[REG_POS(i,0)]; - if(SIGNED_OVERFLOW(cpu->R[REG_POS(i,0)],mul, res)) - { - cpu->CPSR.bits.Q=1; - cpu->R[REG_POS(i,12)]=0x80000000-BIT31(res); - return 2; - } - cpu->R[REG_POS(i,12)]=res; - if(REG_POS(i,12)==15) - { - cpu->R[15] &= 0XFFFFFFFC; - cpu->next_instruction = cpu->R[15]; - return 3; - } - return 2; -} - -TEMPLATE static u32 FASTCALL OP_QDSUB() -{ - const u32 &i = cpu->instruction; - u32 mul = cpu->R[REG_POS(i,16)]<<1; - u32 res; - - - LOG("spe add\r\n"); - if(BIT31(cpu->R[REG_POS(i,16)])!=BIT31(mul)) - { - cpu->CPSR.bits.Q=1; - mul = 0x80000000-BIT31(mul); - } - - res = cpu->R[REG_POS(i,0)] - mul; - if(SIGNED_UNDERFLOW(cpu->R[REG_POS(i,0)], mul, res)) - { - cpu->CPSR.bits.Q=1; - cpu->R[REG_POS(i,12)]=0x80000000-BIT31(res); - return 2; - } - cpu->R[REG_POS(i,12)]=res; - if(REG_POS(i,12)==15) - { - cpu->R[15] &= 0XFFFFFFFC; - cpu->next_instruction = cpu->R[15]; - return 3; - } - return 2; -} - -//-----------------SMUL------------------------------- - -#define HWORD(i) ((s32)(((s32)(i))>>16)) -#define LWORD(i) (s32)(((s32)((i)<<16))>>16) - -TEMPLATE static u32 FASTCALL OP_SMUL_B_B() -{ - const u32 &i = cpu->instruction; - - cpu->R[REG_POS(i,16)] = (u32)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); - - return 2; -} - -TEMPLATE static u32 FASTCALL OP_SMUL_B_T() -{ - const u32 &i = cpu->instruction; - - cpu->R[REG_POS(i,16)] = (u32)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); - - return 2; -} - -TEMPLATE static u32 FASTCALL OP_SMUL_T_B() -{ - const u32 &i = cpu->instruction; - - cpu->R[REG_POS(i,16)] = (u32)(HWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); - - return 2; -} - -TEMPLATE static u32 FASTCALL OP_SMUL_T_T() -{ - const u32 &i = cpu->instruction; - - cpu->R[REG_POS(i,16)] = (u32)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); - - return 2; -} - -//-----------SMLA---------------------------- - -TEMPLATE static u32 FASTCALL OP_SMLA_B_B() -{ - const u32 &i = cpu->instruction; - u32 tmp = (u32)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); - u32 a = cpu->R[REG_POS(i,12)]; - - //LOG("SMLABB %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a); - cpu->R[REG_POS(i,16)] = tmp + a; - - if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)])) - cpu->CPSR.bits.Q = 1; - - return 2; -} - -TEMPLATE static u32 FASTCALL OP_SMLA_B_T() -{ - const u32 &i = cpu->instruction; - u32 tmp = (u32)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); - u32 a = cpu->R[REG_POS(i,12)]; - - //LOG("SMLABT %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a); - cpu->R[REG_POS(i,16)] = tmp + a; - - if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)])) - cpu->CPSR.bits.Q = 1; - - return 2; -} - -TEMPLATE static u32 FASTCALL OP_SMLA_T_B() -{ - const u32 &i = cpu->instruction; - u32 tmp = (u32)(HWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); - u32 a = cpu->R[REG_POS(i,12)]; - - //LOG("SMLATB %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a); - cpu->R[REG_POS(i,16)] = tmp + a; - - if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)])) - cpu->CPSR.bits.Q = 1; - - return 2; -} - -TEMPLATE static u32 FASTCALL OP_SMLA_T_T() -{ - const u32 &i = cpu->instruction; - u32 tmp = (u32)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); - u32 a = cpu->R[REG_POS(i,12)]; - - //LOG("SMLATT %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a); - cpu->R[REG_POS(i,16)] = tmp + a; - - if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)])) - cpu->CPSR.bits.Q = 1; - - return 2; -} - -//--------------SMLAL--------------------------------------- - -TEMPLATE static u32 FASTCALL OP_SMLAL_B_B() -{ - const u32 &i = cpu->instruction; - s64 tmp = (s64)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); - u64 res = (u64)tmp + cpu->R[REG_POS(i,12)]; - - LOG("SMLALBB %08X * %08X + %08X%08X = %08X%08X\r\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + (res + ((tmp<0)*0xFFFFFFFF))), (int)(u32) res); - - cpu->R[REG_POS(i,12)] = (u32) res; - cpu->R[REG_POS(i,16)] += (res + ((tmp<0)*0xFFFFFFFF)); - - return 2; -} - -TEMPLATE static u32 FASTCALL OP_SMLAL_B_T() -{ - const u32 &i = cpu->instruction; - s64 tmp = (s64)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); - u64 res = (u64)tmp + cpu->R[REG_POS(i,12)]; - - LOG("SMLALBT %08X * %08X + %08X%08X = %08X%08X\r\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(u32) res); - - cpu->R[REG_POS(i,12)] = (u32) res; - cpu->R[REG_POS(i,16)] += res + ((tmp<0)*0xFFFFFFFF); - - return 2; -} - -TEMPLATE static u32 FASTCALL OP_SMLAL_T_B() -{ - const u32 &i = cpu->instruction; - s64 tmp = (s64)(HWORD(cpu->R[REG_POS(i,0)])* (s64)LWORD(cpu->R[REG_POS(i,8)])); - u64 res = (u64)tmp + cpu->R[REG_POS(i,12)]; - - LOG("SMLALTB %08X * %08X + %08X%08X = %08X%08X\r\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(u32) res); - - cpu->R[REG_POS(i,12)] = (u32) res; - cpu->R[REG_POS(i,16)] += res + ((tmp<0)*0xFFFFFFFF); - - return 2; -} - -TEMPLATE static u32 FASTCALL OP_SMLAL_T_T() -{ - const u32 &i = cpu->instruction; - s64 tmp = (s64)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); - u64 res = (u64)tmp + cpu->R[REG_POS(i,12)]; - - LOG("SMLALTT %08X * %08X + %08X%08X = %08X%08X\r\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(u32) res); - - cpu->R[REG_POS(i,12)] = (u32) res; - cpu->R[REG_POS(i,16)] += res + ((tmp<0)*0xFFFFFFFF); - - return 2; -} - -//--------------SMULW-------------------- - -TEMPLATE static u32 FASTCALL OP_SMULW_B() -{ - const u32 &i = cpu->instruction; - s64 tmp = (s64)LWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); - - //LOG("SMULWB %08X * %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], ((tmp>>16)&0xFFFFFFFF); - - cpu->R[REG_POS(i,16)] = ((tmp>>16)&0xFFFFFFFF); - - return 2; -} - -TEMPLATE static u32 FASTCALL OP_SMULW_T() -{ - const u32 &i = cpu->instruction; - s64 tmp = (s64)HWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); - - //LOG("SMULWT %08X * %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], ((tmp>>16)&0xFFFFFFFF)); - - cpu->R[REG_POS(i,16)] = ((tmp>>16)&0xFFFFFFFF); - - return 2; -} - -//--------------SMLAW------------------- -TEMPLATE static u32 FASTCALL OP_SMLAW_B() -{ - const u32 &i = cpu->instruction; - s64 tmp = (s64)LWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); - u32 a = cpu->R[REG_POS(i,12)]; - - //LOG("SMLAWB %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, (tmp>>16) + a); - - tmp = (tmp>>16); - - cpu->R[REG_POS(i,16)] = tmp + a; - - if(SIGNED_OVERFLOW((u32)tmp, a, cpu->R[REG_POS(i,16)])) - cpu->CPSR.bits.Q = 1; - - return 2; -} - -TEMPLATE static u32 FASTCALL OP_SMLAW_T() -{ - const u32 &i = cpu->instruction; - s64 tmp = (s64)HWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); - u32 a = cpu->R[REG_POS(i,12)]; - - //LOG("SMLAWT %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, ((tmp>>16)&0xFFFFFFFF) + a); - - tmp = ((tmp>>16)&0xFFFFFFFF); - cpu->R[REG_POS(i,16)] = tmp + a; - - if(SIGNED_OVERFLOW((u32)tmp, a, cpu->R[REG_POS(i,16)])) - cpu->CPSR.bits.Q = 1; - - return 2; -} - -//------------LDR--------------------------- - -TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - u32 val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,12)] = val; - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - u32 val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - u32 val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - u32 val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - u32 val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -//------------------------------------------------------------ -TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND2() -{ - const u32 &i = cpu->instruction; - - u32 adr = cpu->R[REG_POS(i,16)]; - u32 val = READ32(cpu->mem_if->data, adr); - u32 old; - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - old = armcpu_switchMode(cpu, USR); - cpu->R[REG_POS(i,12)] = val; - armcpu_switchMode(cpu, old); - - cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -//------------------------------------------------------------ - -TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - u32 val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr + shift_op; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr - shift_op; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr + shift_op; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr - shift_op; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr + shift_op; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr - shift_op; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr + shift_op; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ32(cpu->mem_if->data, adr); - - if(adr&3) - val = ROR(val, 8*(adr&3)); - - if(REG_POS(i,12)==15) - { - cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); - cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; - cpu->next_instruction = cpu->R[15]; - cpu->R[REG_POS(i,16)] = adr - shift_op; - return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; - } - - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -//-----------------LDRB------------------------------------------- - -TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - u32 val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_M_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - u32 val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - u32 val = READ8(cpu->mem_if->data, adr); - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_M_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - u32 val = READ8(cpu->mem_if->data, adr); - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ8(cpu->mem_if->data, adr); - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ8(cpu->mem_if->data, adr); - - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] = adr; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - u32 val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_M_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - u32 val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] = adr + shift_op; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 val; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,16)] = adr - shift_op; - cpu->R[REG_POS(i,12)] = val; - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -//----------------------STR-------------------------------- - -TEMPLATE static u32 FASTCALL OP_STR_P_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - -// emu_halt(); - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_P_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_P_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + shift_op; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - shift_op; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + shift_op; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - shift_op; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + shift_op; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - shift_op; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + shift_op; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - shift_op; - - return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; -} - -//-----------------------STRB------------------------------------- - -TEMPLATE static u32 FASTCALL OP_STRB_P_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_M_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_P_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; - WRITE8(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_M_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)] + shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_PREIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)] - shift_op; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_P_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_M_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + shift_op; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - shift_op; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + shift_op; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - shift_op; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + shift_op; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - shift_op; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + shift_op; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND() -{ - const u32 &i = cpu->instruction; - u32 adr; - u32 shift_op; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - shift_op; - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -//-----------------------LDRBT------------------------------------- - -TEMPLATE static u32 FASTCALL OP_LDRBT_P_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - - if(cpu->CPSR.bits.mode==USR) - return 2; - oldmode = armcpu_switchMode(cpu, SYS); - - i = cpu->instruction; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_M_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - - if(cpu->CPSR.bits.mode==USR) - return 2; - oldmode = armcpu_switchMode(cpu, SYS); - - //emu_halt(); - LOG("Untested opcode: OP_LDRBT_M_IMM_OFF_POSTIND\n"); - - - i = cpu->instruction; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_P_REG_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - //emu_halt(); - LOG("Untested opcode: OP_LDRBT_P_REG_OFF_POSTIND\n"); - - - i = cpu->instruction; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr + cpu->R[REG_POS(i,0)]; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_P_LSL_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - oldmode = armcpu_switchMode(cpu, SYS); - //emu_halt(); - LOG("Untested opcode: OP_LDRBT_P_LSL_IMM_OFF_POSTIND\n"); - - - i = cpu->instruction; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr + shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_M_LSL_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - //emu_halt(); - LOG("Untested opcode: OP_LDRBT_M_LSL_IMM_OFF_POSTIND\n"); - - - i = cpu->instruction; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr - shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_P_LSR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - //emu_halt(); - LOG("Untested opcode: OP_LDRBT_P_LSR_IMM_OFF_POSTIND\n"); - - - i = cpu->instruction; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr + shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_M_LSR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - //emu_halt(); - LOG("Untested opcode: OP_LDRBT_M_LSR_IMM_OFF_POSTIND\n"); - - - i = cpu->instruction; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr - shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_P_ASR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - //emu_halt(); - LOG("Untested opcode: OP_LDRBT_P_ASR_IMM_OFF_POSTIND\n"); - - - i = cpu->instruction; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr + shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_M_ASR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - //emu_halt(); - LOG("Untested opcode: OP_LDRBT_M_ASR_IMM_OFF_POSTIND\n"); - - - i = cpu->instruction; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr - shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_P_ROR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - //emu_halt(); - LOG("Untested opcode: OP_LDRBT_P_ROR_IMM_OFF_POSTIND\n"); - - - i = cpu->instruction; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr + shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_LDRBT_M_ROR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 val; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - //emu_halt(); - LOG("Untested opcode: OP_LDRBT_M_ROR_IMM_OFF_POSTIND\n"); - - - i = cpu->instruction; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - val = READ8(cpu->mem_if->data, adr); - cpu->R[REG_POS(i,12)] = val; - cpu->R[REG_POS(i,16)] = adr - shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -//----------------------STRBT---------------------------- - -TEMPLATE static u32 FASTCALL OP_STRBT_P_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_M_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_P_REG_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + cpu->R[REG_POS(i,0)]; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_M_REG_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - cpu->R[REG_POS(i,0)]; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_P_LSL_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_M_LSL_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - LSL_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_P_LSR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_M_LSR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - LSR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_P_ASR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_M_ASR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - ASR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_P_ROR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr + shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -TEMPLATE static u32 FASTCALL OP_STRBT_M_ROR_IMM_OFF_POSTIND() -{ - u32 oldmode; - u32 i; - u32 adr; - u32 shift_op; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - oldmode = armcpu_switchMode(cpu, SYS); - - - i = cpu->instruction; - ROR_IMM; - adr = cpu->R[REG_POS(i,16)]; - WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); - cpu->R[REG_POS(i,16)] = adr - shift_op; - - armcpu_switchMode(cpu, oldmode); - - return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; -} - -//---------------------LDM----------------------------- - -#define OP_L_IA(reg, adr) if(BIT##reg(i))\ - {\ - registres[reg] = READ32(cpu->mem_if->data, start);\ - c += waitState[(start>>24)&0xF];\ - adr += 4;\ - } - -#define OP_L_IB(reg, adr) if(BIT##reg(i))\ - {\ - adr += 4;\ - registres[reg] = READ32(cpu->mem_if->data, start);\ - c += waitState[(start>>24)&0xF];\ - } - -#define OP_L_DA(reg, adr) if(BIT##reg(i))\ - {\ - registres[reg] = READ32(cpu->mem_if->data, start);\ - c += waitState[(start>>24)&0xF];\ - adr -= 4;\ - } - -#define OP_L_DB(reg, adr) if(BIT##reg(i))\ - {\ - adr -= 4;\ - registres[reg] = READ32(cpu->mem_if->data, start);\ - c += waitState[(start>>24)&0xF];\ - } - -TEMPLATE static u32 FASTCALL OP_LDMIA() -{ - const u32 &i = cpu->instruction; - u32 c = 0; - u32 start = cpu->R[REG_POS(i,16)]; - - u32 * registres = cpu->R; - TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; - - OP_L_IA(0, start); - OP_L_IA(1, start); - OP_L_IA(2, start); - OP_L_IA(3, start); - OP_L_IA(4, start); - OP_L_IA(5, start); - OP_L_IA(6, start); - OP_L_IA(7, start); - OP_L_IA(8, start); - OP_L_IA(9, start); - OP_L_IA(10, start); - OP_L_IA(11, start); - OP_L_IA(12, start); - OP_L_IA(13, start); - OP_L_IA(14, start); - - if(BIT15(i)) - { - u32 tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR.bits.T = BIT0(tmp); - //start += 4; - cpu->next_instruction = registres[15]; - c += waitState[(start>>24)&0xF]; - } - - return c + 2; -} - -TEMPLATE static u32 FASTCALL OP_LDMIB() -{ - const u32 &i = cpu->instruction; - u32 c = 0; - u32 start = cpu->R[REG_POS(i,16)]; - - u32 * registres = cpu->R; - TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; - - OP_L_IB(0, start); - OP_L_IB(1, start); - OP_L_IB(2, start); - OP_L_IB(3, start); - OP_L_IB(4, start); - OP_L_IB(5, start); - OP_L_IB(6, start); - OP_L_IB(7, start); - OP_L_IB(8, start); - OP_L_IB(9, start); - OP_L_IB(10, start); - OP_L_IB(11, start); - OP_L_IB(12, start); - OP_L_IB(13, start); - OP_L_IB(14, start); - - if(BIT15(i)) - { - u32 tmp; - start += 4; - c += waitState[(start>>24)&0xF]; - tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR.bits.T = BIT0(tmp); - cpu->next_instruction = registres[15]; - c += 2 + (c==0); - } - - return c + 2; -} - -TEMPLATE static u32 FASTCALL OP_LDMDA() -{ - const u32 &i = cpu->instruction; - u32 c = 0; - u32 start = cpu->R[REG_POS(i,16)]; - - u32 * registres = cpu->R; - TWaitState * waitState = MMU.MMU_WAIT32[PROCNUM]; - - if(BIT15(i)) - { - u32 tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR.bits.T = BIT0(tmp); - c += waitState[(start>>24)&0xF]; - start -= 4; - cpu->next_instruction = registres[15]; - } - - OP_L_DA(14, start); - OP_L_DA(13, start); - OP_L_DA(12, start); - OP_L_DA(11, start); - OP_L_DA(10, start); - OP_L_DA(9, start); - OP_L_DA(8, start); - OP_L_DA(7, start); - OP_L_DA(6, start); - OP_L_DA(5, start); - OP_L_DA(4, start); - OP_L_DA(3, start); - OP_L_DA(2, start); - OP_L_DA(1, start); - OP_L_DA(0, start); - - return c + 2; -} - -TEMPLATE static u32 FASTCALL OP_LDMDB() -{ - const u32 &i = cpu->instruction; - u32 c = 0; - u32 start = cpu->R[REG_POS(i,16)]; - - u32 * registres = cpu->R; - TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; - - if(BIT15(i)) - { - u32 tmp; - start -= 4; - tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR.bits.T = BIT0(tmp); - cpu->next_instruction = registres[15]; - c += waitState[(start>>24)&0xF]; - } - - OP_L_DB(14, start); - OP_L_DB(13, start); - OP_L_DB(12, start); - OP_L_DB(11, start); - OP_L_DB(10, start); - OP_L_DB(9, start); - OP_L_DB(8, start); - OP_L_DB(7, start); - OP_L_DB(6, start); - OP_L_DB(5, start); - OP_L_DB(4, start); - OP_L_DB(3, start); - OP_L_DB(2, start); - OP_L_DB(1, start); - OP_L_DB(0, start); - - return c + 2; -} - -TEMPLATE static u32 FASTCALL OP_LDMIA_W() -{ - const u32 &i = cpu->instruction; - u32 c = 0; - u32 start = cpu->R[REG_POS(i,16)]; - u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF; - - u32 * registres = cpu->R; - TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; - - OP_L_IA(0, start); - OP_L_IA(1, start); - OP_L_IA(2, start); - OP_L_IA(3, start); - OP_L_IA(4, start); - OP_L_IA(5, start); - OP_L_IA(6, start); - OP_L_IA(7, start); - OP_L_IA(8, start); - OP_L_IA(9, start); - OP_L_IA(10, start); - OP_L_IA(11, start); - OP_L_IA(12, start); - OP_L_IA(13, start); - OP_L_IA(14, start); - - if(BIT15(i)) - { - u32 tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR.bits.T = BIT0(tmp); - c += waitState[(start>>24)&0xF]; - start += 4; - cpu->next_instruction = registres[15]; - } - - if(i & (1 << REG_POS(i,16))) { - if(i & bitList) - cpu->R[REG_POS(i,16)] = start; - } - else - cpu->R[REG_POS(i,16)] = start; - - return c + 2; -} - -TEMPLATE static u32 FASTCALL OP_LDMIB_W() -{ - const u32 &i = cpu->instruction; - u32 c = 0; - u32 start = cpu->R[REG_POS(i,16)]; - u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF; - - u32 * registres = cpu->R; - TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; - - OP_L_IB(0, start); - OP_L_IB(1, start); - OP_L_IB(2, start); - OP_L_IB(3, start); - OP_L_IB(4, start); - OP_L_IB(5, start); - OP_L_IB(6, start); - OP_L_IB(7, start); - OP_L_IB(8, start); - OP_L_IB(9, start); - OP_L_IB(10, start); - OP_L_IB(11, start); - OP_L_IB(12, start); - OP_L_IB(13, start); - OP_L_IB(14, start); - - if(BIT15(i)) - { - u32 tmp; - start += 4; - c += waitState[(start>>24)&0xF]; - tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR.bits.T = BIT0(tmp); - cpu->next_instruction = registres[15]; - c += 2 + (c==0); - } - - if(i & (1 << REG_POS(i,16))) { - if(i & bitList) - cpu->R[REG_POS(i,16)] = start; - } - else - cpu->R[REG_POS(i,16)] = start; - - return c + 2; -} - -TEMPLATE static u32 FASTCALL OP_LDMDA_W() -{ - const u32 &i = cpu->instruction; - u32 c = 0; - u32 start = cpu->R[REG_POS(i,16)]; - u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF; - - u32 * registres = cpu->R; - TWaitState * waitState = MMU.MMU_WAIT32[PROCNUM]; - - if(BIT15(i)) - { - u32 tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR.bits.T = BIT0(tmp); - c += waitState[(start>>24)&0xF]; - start -= 4; - cpu->next_instruction = registres[15]; - } - - OP_L_DA(14, start); - OP_L_DA(13, start); - OP_L_DA(12, start); - OP_L_DA(11, start); - OP_L_DA(10, start); - OP_L_DA(9, start); - OP_L_DA(8, start); - OP_L_DA(7, start); - OP_L_DA(6, start); - OP_L_DA(5, start); - OP_L_DA(4, start); - OP_L_DA(3, start); - OP_L_DA(2, start); - OP_L_DA(1, start); - OP_L_DA(0, start); - - if(i & (1 << REG_POS(i,16))) { - if(i & bitList) - cpu->R[REG_POS(i,16)] = start; - } - else - cpu->R[REG_POS(i,16)] = start; - - return c + 2; -} - -TEMPLATE static u32 FASTCALL OP_LDMDB_W() -{ - const u32 &i = cpu->instruction; - u32 c = 0; - u32 start = cpu->R[REG_POS(i,16)]; - u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF; - u32 * registres = cpu->R; - TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; - - if(BIT15(i)) - { - u32 tmp; - start -= 4; - tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR.bits.T = BIT0(tmp); - cpu->next_instruction = registres[15]; - c += waitState[(start>>24)&0xF]; - } - - OP_L_DB(14, start); - OP_L_DB(13, start); - OP_L_DB(12, start); - OP_L_DB(11, start); - OP_L_DB(10, start); - OP_L_DB(9, start); - OP_L_DB(8, start); - OP_L_DB(7, start); - OP_L_DB(6, start); - OP_L_DB(5, start); - OP_L_DB(4, start); - OP_L_DB(3, start); - OP_L_DB(2, start); - OP_L_DB(1, start); - OP_L_DB(0, start); - - if(i & (1 << REG_POS(i,16))) { - if(i & bitList) - cpu->R[REG_POS(i,16)] = start; - } - else - cpu->R[REG_POS(i,16)] = start; - - return c + 2; -} - -TEMPLATE static u32 FASTCALL OP_LDMIA2() -{ - const u32 &i = cpu->instruction; - u32 oldmode = 0; - - u32 c = 0; - - u32 start = cpu->R[REG_POS(i,16)]; - u32 * registres; - TWaitState* waitState; - - if(BIT15(i)==0) - { - if(cpu->CPSR.bits.mode==USR) - return 1; - oldmode = armcpu_switchMode(cpu, SYS); - } - - registres = cpu->R; - waitState = MMU.MMU_WAIT32[PROCNUM]; - - OP_L_IA(0, start); - OP_L_IA(1, start); - OP_L_IA(2, start); - OP_L_IA(3, start); - OP_L_IA(4, start); - OP_L_IA(5, start); - OP_L_IA(6, start); - OP_L_IA(7, start); - OP_L_IA(8, start); - OP_L_IA(9, start); - OP_L_IA(10, start); - OP_L_IA(11, start); - OP_L_IA(12, start); - OP_L_IA(13, start); - OP_L_IA(14, start); - - if(BIT15(i) == 0) - { - armcpu_switchMode(cpu, oldmode); - } - else - { - - u32 tmp = READ32(cpu->mem_if->data, start); - Status_Reg SPSR; - cpu->R[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - SPSR = cpu->SPSR; - armcpu_switchMode(cpu, SPSR.bits.mode); - cpu->CPSR=SPSR; - //start += 4; - cpu->next_instruction = cpu->R[15]; - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; - } - return c + 2; -} - -TEMPLATE static u32 FASTCALL OP_LDMIB2() -{ - const u32 &i = cpu->instruction; - u32 oldmode = 0; - u32 c = 0; - - u32 start = cpu->R[REG_POS(i,16)]; - u32 * registres; - TWaitState* waitState; - //emu_halt(); - LOG("Untested opcode: OP_LDMIB2\n"); - - if(BIT15(i)==0) - { - if(cpu->CPSR.bits.mode==USR) - return 2; - oldmode = armcpu_switchMode(cpu, SYS); - } - - registres = cpu->R; - waitState = MMU.MMU_WAIT32[PROCNUM]; - - OP_L_IB(0, start); - OP_L_IB(1, start); - OP_L_IB(2, start); - OP_L_IB(3, start); - OP_L_IB(4, start); - OP_L_IB(5, start); - OP_L_IB(6, start); - OP_L_IB(7, start); - OP_L_IB(8, start); - OP_L_IB(9, start); - OP_L_IB(10, start); - OP_L_IB(11, start); - OP_L_IB(12, start); - OP_L_IB(13, start); - OP_L_IB(14, start); - - if(BIT15(i) == 0) - { - armcpu_switchMode(cpu, oldmode); - } - else - { - u32 tmp; - Status_Reg SPSR; - start += 4; - tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - SPSR = cpu->SPSR; - armcpu_switchMode(cpu, SPSR.bits.mode); - cpu->CPSR=SPSR; - cpu->next_instruction = registres[15]; - c += waitState[(start>>24)&0xF]; - } - return c + 2; -} - -TEMPLATE static u32 FASTCALL OP_LDMDA2() -{ - const u32 &i = cpu->instruction; - - u32 oldmode = 0; - u32 c = 0; - u32 * registres; - TWaitState* waitState; - - u32 start = cpu->R[REG_POS(i,16)]; - //emu_halt(); - LOG("Untested opcode: OP_LDMDA2\n"); - - if(BIT15(i)==0) - { - if(cpu->CPSR.bits.mode==USR) - return 2; - oldmode = armcpu_switchMode(cpu, SYS); - } - - registres = cpu->R; - waitState = MMU.MMU_WAIT32[PROCNUM]; - - if(BIT15(i)) - { - u32 tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR = cpu->SPSR; - c += waitState[(start>>24)&0xF]; - start -= 4; - cpu->next_instruction = registres[15]; - } - - OP_L_DA(14, start); - OP_L_DA(13, start); - OP_L_DA(12, start); - OP_L_DA(11, start); - OP_L_DA(10, start); - OP_L_DA(9, start); - OP_L_DA(8, start); - OP_L_DA(7, start); - OP_L_DA(6, start); - OP_L_DA(5, start); - OP_L_DA(4, start); - OP_L_DA(3, start); - OP_L_DA(2, start); - OP_L_DA(1, start); - OP_L_DA(0, start); - - if(BIT15(i)==0) - { - armcpu_switchMode(cpu, oldmode); - } - else - { - Status_Reg SPSR = cpu->SPSR; - armcpu_switchMode(cpu, SPSR.bits.mode); - cpu->CPSR=SPSR; - } - - return c + 2; -} - -TEMPLATE static u32 FASTCALL OP_LDMDB2() -{ - const u32 &i = cpu->instruction; - - u32 oldmode = 0; - u32 c = 0; - u32 * registres; - TWaitState* waitState; - - u32 start = cpu->R[REG_POS(i,16)]; - if(BIT15(i)==0) - { - if(cpu->CPSR.bits.mode==USR) - return 2; - oldmode = armcpu_switchMode(cpu, SYS); - } - - registres = cpu->R; - waitState = MMU.MMU_WAIT32[PROCNUM]; - - if(BIT15(i)) - { - u32 tmp; - start -= 4; - tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR = cpu->SPSR; - cpu->next_instruction = registres[15]; - c += waitState[(start>>24)&0xF]; - } - - OP_L_DB(14, start); - OP_L_DB(13, start); - OP_L_DB(12, start); - OP_L_DB(11, start); - OP_L_DB(10, start); - OP_L_DB(9, start); - OP_L_DB(8, start); - OP_L_DB(7, start); - OP_L_DB(6, start); - OP_L_DB(5, start); - OP_L_DB(4, start); - OP_L_DB(3, start); - OP_L_DB(2, start); - OP_L_DB(1, start); - OP_L_DB(0, start); - - if(BIT15(i)==0) - { - armcpu_switchMode(cpu, oldmode); - } - else - { - Status_Reg SPSR = cpu->SPSR; - armcpu_switchMode(cpu, SPSR.bits.mode); - cpu->CPSR=SPSR; - } - - return 2 + c; -} - -TEMPLATE static u32 FASTCALL OP_LDMIA2_W() -{ - const u32 &i = cpu->instruction; - u32 c = 0; - - u32 oldmode = 0; - u32 start = cpu->R[REG_POS(i,16)]; - u32 * registres; - TWaitState* waitState; - u32 tmp; - Status_Reg SPSR; -// emu_halt(); - if(BIT15(i)==0) - { - if(cpu->CPSR.bits.mode==USR) - return 2; - oldmode = armcpu_switchMode(cpu, SYS); - } - - registres = cpu->R; - waitState = MMU.MMU_WAIT32[PROCNUM]; - - OP_L_IA(0, start); - OP_L_IA(1, start); - OP_L_IA(2, start); - OP_L_IA(3, start); - OP_L_IA(4, start); - OP_L_IA(5, start); - OP_L_IA(6, start); - OP_L_IA(7, start); - OP_L_IA(8, start); - OP_L_IA(9, start); - OP_L_IA(10, start); - OP_L_IA(11, start); - OP_L_IA(12, start); - OP_L_IA(13, start); - OP_L_IA(14, start); - - if(BIT15(i)==0) - { - registres[REG_POS(i,16)] = start; - armcpu_switchMode(cpu, oldmode); - return c + 2; - } - - registres[REG_POS(i,16)] = start + 4; - tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - SPSR = cpu->SPSR; - armcpu_switchMode(cpu, SPSR.bits.mode); - cpu->CPSR=SPSR; - cpu->next_instruction = registres[15]; - c += waitState[(start>>24)&0xF]; - - return c + 2; -} - -TEMPLATE static u32 FASTCALL OP_LDMIB2_W() -{ - const u32 &i = cpu->instruction; - u32 c = 0; - - u32 oldmode = 0; - u32 start = cpu->R[REG_POS(i,16)]; - u32 * registres; - TWaitState* waitState; - u32 tmp; - Status_Reg SPSR; - - if(BIT15(i)==0) - { - if(cpu->CPSR.bits.mode==USR) - return 2; - oldmode = armcpu_switchMode(cpu, SYS); - } - - registres = cpu->R; - waitState = MMU.MMU_WAIT32[PROCNUM]; - - OP_L_IB(0, start); - OP_L_IB(1, start); - OP_L_IB(2, start); - OP_L_IB(3, start); - OP_L_IB(4, start); - OP_L_IB(5, start); - OP_L_IB(6, start); - OP_L_IB(7, start); - OP_L_IB(8, start); - OP_L_IB(9, start); - OP_L_IB(10, start); - OP_L_IB(11, start); - OP_L_IB(12, start); - OP_L_IB(13, start); - OP_L_IB(14, start); - - if(BIT15(i)==0) - { - armcpu_switchMode(cpu, oldmode); - registres[REG_POS(i,16)] = start; - - return c + 2; - } - - registres[REG_POS(i,16)] = start + 4; - tmp = READ32(cpu->mem_if->data, start + 4); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR = cpu->SPSR; - cpu->next_instruction = registres[15]; - SPSR = cpu->SPSR; - armcpu_switchMode(cpu, SPSR.bits.mode); - cpu->CPSR=SPSR; - c += waitState[(start>>24)&0xF]; - - return c + 2; -} - -TEMPLATE static u32 FASTCALL OP_LDMDA2_W() -{ - const u32 &i = cpu->instruction; - u32 c = 0; - - u32 oldmode = 0; - u32 start = cpu->R[REG_POS(i,16)]; - u32 * registres; - TWaitState * waitState; - Status_Reg SPSR; -// emu_halt(); - if(BIT15(i)==0) - { - if(cpu->CPSR.bits.mode==USR) - return 2; - oldmode = armcpu_switchMode(cpu, SYS); - } - - registres = cpu->R; - waitState = MMU.MMU_WAIT32[PROCNUM]; - - if(BIT15(i)) - { - u32 tmp = READ32(cpu->mem_if->data, start); - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - c += waitState[(start>>24)&0xF]; - start -= 4; - cpu->next_instruction = registres[15]; - } - - OP_L_DA(14, start); - OP_L_DA(13, start); - OP_L_DA(12, start); - OP_L_DA(11, start); - OP_L_DA(10, start); - OP_L_DA(9, start); - OP_L_DA(8, start); - OP_L_DA(7, start); - OP_L_DA(6, start); - OP_L_DA(5, start); - OP_L_DA(4, start); - OP_L_DA(3, start); - OP_L_DA(2, start); - OP_L_DA(1, start); - OP_L_DA(0, start); - - registres[REG_POS(i,16)] = start; - - if(BIT15(i)==0) - { - armcpu_switchMode(cpu, oldmode); - return c + 2; - } - - SPSR = cpu->SPSR; - armcpu_switchMode(cpu, SPSR.bits.mode); - cpu->CPSR=SPSR; - return c + 2; -} - -TEMPLATE static u32 FASTCALL OP_LDMDB2_W() -{ - const u32 &i = cpu->instruction; - u32 c = 0; - - u32 oldmode = 0; - u32 start = cpu->R[REG_POS(i,16)]; - u32 * registres; - TWaitState* waitState; - Status_Reg SPSR; -// emu_halt(); - if(BIT15(i)==0) - { - if(cpu->CPSR.bits.mode==USR) - return 2; - oldmode = armcpu_switchMode(cpu, SYS); - } - - registres = cpu->R; - waitState = MMU.MMU_WAIT32[PROCNUM]; - - if(BIT15(i)) - { - u32 tmp; - start -= 4; - tmp = READ32(cpu->mem_if->data, start); - c += waitState[(start>>24)&0xF]; - registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); - cpu->CPSR = cpu->SPSR; - cpu->next_instruction = registres[15]; - } - - OP_L_DB(14, start); - OP_L_DB(13, start); - OP_L_DB(12, start); - OP_L_DB(11, start); - OP_L_DB(10, start); - OP_L_DB(9, start); - OP_L_DB(8, start); - OP_L_DB(7, start); - OP_L_DB(6, start); - OP_L_DB(5, start); - OP_L_DB(4, start); - OP_L_DB(3, start); - OP_L_DB(2, start); - OP_L_DB(1, start); - OP_L_DB(0, start); - - registres[REG_POS(i,16)] = start; - - if(BIT15(i)==0) - { - armcpu_switchMode(cpu, oldmode); - return c + 2; - } - - SPSR = cpu->SPSR; - armcpu_switchMode(cpu, SPSR.bits.mode); - cpu->CPSR=SPSR; - return c + 2; -} - -//------------------------------STM---------------------------------- - -TEMPLATE static u32 FASTCALL OP_STMIA() -{ - const u32 &i = cpu->instruction; - u32 c = 0, b; - u32 start = cpu->R[REG_POS(i,16)]; - - for(b=0; b<16; ++b) - { - if(BIT_N(i, b)) - { - WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; - start += 4; - } - } - return c + 1; -} - -TEMPLATE static u32 FASTCALL OP_STMIB() -{ - const u32 &i = cpu->instruction; - u32 c = 0, b; - u32 start = cpu->R[REG_POS(i,16)]; - - for(b=0; b<16; ++b) - { - if(BIT_N(i, b)) - { - start += 4; - WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; - } - } - return c + 1; -} - -TEMPLATE static u32 FASTCALL OP_STMDA() -{ - const u32 &i = cpu->instruction; - u32 c = 0, b; - u32 start = cpu->R[REG_POS(i,16)]; - - for(b=0; b<16; ++b) - { - if(BIT_N(i, 15-b)) - { - WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; - start -= 4; - } - } - return c + 1; -} - -TEMPLATE static u32 FASTCALL OP_STMDB() -{ - const u32 &i = cpu->instruction; - u32 c = 0, b; - u32 start = cpu->R[REG_POS(i,16)]; - - for(b=0; b<16; ++b) - { - if(BIT_N(i, 15-b)) - { - start -= 4; - WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; - } - } - return c + 1; -} - -TEMPLATE static u32 FASTCALL OP_STMIA_W() -{ - const u32 &i = cpu->instruction; - u32 c = 0, b; - u32 start = cpu->R[REG_POS(i,16)]; - - for(b=0; b<16; ++b) - { - if(BIT_N(i, b)) - { - WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; - start += 4; - } - } - - cpu->R[REG_POS(i,16)] = start; - return c + 1; -} - -TEMPLATE static u32 FASTCALL OP_STMIB_W() -{ - const u32 &i = cpu->instruction; - u32 c = 0, b; - u32 start = cpu->R[REG_POS(i,16)]; - - for(b=0; b<16; ++b) - { - if(BIT_N(i, b)) - { - start += 4; - WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; - } - } - cpu->R[REG_POS(i,16)] = start; - return c + 1; -} - -TEMPLATE static u32 FASTCALL OP_STMDA_W() -{ - const u32 &i = cpu->instruction; - u32 c = 0, b; - u32 start = cpu->R[REG_POS(i,16)]; - - for(b=0; b<16; ++b) - { - if(BIT_N(i, 15-b)) - { - WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; - start -= 4; - } - } - - cpu->R[REG_POS(i,16)] = start; - return c + 1; -} - -TEMPLATE static u32 FASTCALL OP_STMDB_W() -{ - const u32 &i = cpu->instruction; - u32 c = 0, b; - u32 start = cpu->R[REG_POS(i,16)]; - - for(b=0; b<16; ++b) - { - if(BIT_N(i, 15-b)) - { - start -= 4; - WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; - } - } - - cpu->R[REG_POS(i,16)] = start; - return c + 1; -} - -TEMPLATE static u32 FASTCALL OP_STMIA2() -{ - const u32 &i = cpu->instruction; - u32 c, b; - u32 start; - u32 oldmode; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - c = 0; - start = cpu->R[REG_POS(i,16)]; - oldmode = armcpu_switchMode(cpu, SYS); - - //emu_halt(); - LOG("Untested opcode: OP_STMIA2\n"); - - for(b=0; b<16; ++b) - { - if(BIT_N(i, b)) - { - WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; - start += 4; - } - } - - armcpu_switchMode(cpu, oldmode); - return c + 1; -} - -TEMPLATE static u32 FASTCALL OP_STMIB2() -{ - const u32 &i = cpu->instruction; - u32 c, b; - u32 start; - u32 oldmode; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - c = 0; - start = cpu->R[REG_POS(i,16)]; - oldmode = armcpu_switchMode(cpu, SYS); - - //emu_halt(); - LOG("Untested opcode: OP_STMIB2\n"); - - for(b=0; b<16; ++b) - { - if(BIT_N(i, b)) - { - start += 4; - WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; - } - } - - armcpu_switchMode(cpu, oldmode); - return c + 1; -} - -TEMPLATE static u32 FASTCALL OP_STMDA2() -{ - const u32 &i=cpu->instruction; - u32 c, b; - u32 start; - u32 oldmode; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - c = 0; - start = cpu->R[REG_POS(i,16)]; - oldmode = armcpu_switchMode(cpu, SYS); - - //emu_halt(); - LOG("Untested opcode: OP_STMDA2\n"); - - for(b=0; b<16; ++b) - { - if(BIT_N(i, 15-b)) - { - WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; - start -= 4; - } - } - - armcpu_switchMode(cpu, oldmode); - return c + 1; -} - -TEMPLATE static u32 FASTCALL OP_STMDB2() -{ - const u32 &i = cpu->instruction; - u32 c, b; - u32 start; - u32 oldmode; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - c=0; - start = cpu->R[REG_POS(i,16)]; - oldmode = armcpu_switchMode(cpu, SYS); - - for(b=0; b<16; ++b) - { - if(BIT_N(i, 15-b)) - { - start -= 4; - WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; - } - } - - armcpu_switchMode(cpu, oldmode); - return c + 1; -} - -TEMPLATE static u32 FASTCALL OP_STMIA2_W() -{ - u32 i, c, b; - u32 start; - u32 oldmode; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - i = cpu->instruction; - c=0; - start = cpu->R[REG_POS(i,16)]; - oldmode = armcpu_switchMode(cpu, SYS); - - //emu_halt(); - LOG("Untested opcode: OP_STMIA2_W\n"); - - for(b=0; b<16; ++b) - { - if(BIT_N(i, b)) - { - WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; - start += 4; - } - } - - cpu->R[REG_POS(i,16)] = start; - - armcpu_switchMode(cpu, oldmode); - return c + 1; -} - -TEMPLATE static u32 FASTCALL OP_STMIB2_W() -{ - u32 i, c, b; - u32 start; - u32 oldmode; - - if(cpu->CPSR.bits.mode==USR) - return 2; - i = cpu->instruction; - c=0; - start = cpu->R[REG_POS(i,16)]; - oldmode = armcpu_switchMode(cpu, SYS); - - for(b=0; b<16; ++b) - { - if(BIT_N(i, b)) - { - start += 4; - WRITE32(cpu->mem_if->data, start, cpu->R[b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; - } - } - armcpu_switchMode(cpu, oldmode); - cpu->R[REG_POS(i,16)] = start; - - return c + 1; -} - -TEMPLATE static u32 FASTCALL OP_STMDA2_W() -{ - u32 i, c, b; - u32 start; - u32 oldmode; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - i = cpu->instruction; - c = 0; - start = cpu->R[REG_POS(i,16)]; - oldmode = armcpu_switchMode(cpu, SYS); - //emu_halt(); - LOG("Untested opcode: OP_STMDA2_W\n"); - - for(b=0; b<16; ++b) - { - if(BIT_N(i, 15-b)) - { - WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; - start -= 4; - } - } - - cpu->R[REG_POS(i,16)] = start; - - armcpu_switchMode(cpu, oldmode); - return c + 1; -} - -TEMPLATE static u32 FASTCALL OP_STMDB2_W() -{ - u32 i, c, b; - u32 start; - u32 oldmode; - - if(cpu->CPSR.bits.mode==USR) - return 2; - - i = cpu->instruction; - c = 0; - - start = cpu->R[REG_POS(i,16)]; - oldmode = armcpu_switchMode(cpu, SYS); - - //emu_halt(); - LOG("Untested opcode: OP_STMDB2_W\n"); - - for(b=0; b<16; ++b) - { - if(BIT_N(i, 15-b)) - { - start -= 4; - WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); - c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; - } - } - - cpu->R[REG_POS(i,16)] = start; - - armcpu_switchMode(cpu, oldmode); - return c + 1; -} - -/* - * - * The Enhanced DSP Extension LDRD and STRD instructions. - * - */ -TEMPLATE static u32 FASTCALL -OP_LDRD_STRD_POST_INDEX( ) { - const u32 &i = cpu->instruction; - u32 Rd_num = REG_POS( i, 12); - u32 addr = cpu->R[REG_POS(i,16)]; - u32 index; - - /* I bit - immediate or register */ - if ( BIT22(i)) - index = IMM_OFF; - else - index = cpu->R[REG_POS(i,0)]; - - /* U bit - add or subtract */ - if ( BIT23(i)) - cpu->R[REG_POS(i,16)] += index; - else - cpu->R[REG_POS(i,16)] -= index; - - if ( !(Rd_num & 0x1)) { - /* Store/Load */ - if ( BIT5(i)) { - WRITE32(cpu->mem_if->data, addr, cpu->R[Rd_num]); - WRITE32(cpu->mem_if->data, addr + 4, cpu->R[Rd_num + 1]); - } - else { - cpu->R[Rd_num] = READ32(cpu->mem_if->data, addr); - cpu->R[Rd_num + 1] = READ32(cpu->mem_if->data, addr + 4); - } - } - - return 3 + (MMU.MMU_WAIT32[PROCNUM][(addr>>24)&0xF] * 2); -} - -TEMPLATE static u32 FASTCALL -OP_LDRD_STRD_OFFSET_PRE_INDEX( ) { - const u32 &i = cpu->instruction; - u32 Rd_num = REG_POS( i, 12); - u32 addr = cpu->R[REG_POS(i,16)]; - u32 index; - - /* I bit - immediate or register */ - if ( BIT22(i)) - index = IMM_OFF; - else - index = cpu->R[REG_POS(i,0)]; - - /* U bit - add or subtract */ - if ( BIT23(i)) { - addr += index; - - /* W bit - writeback */ - if ( BIT21(i)) - cpu->R[REG_POS(i,16)] = addr; - } - else { - addr -= index; - - /* W bit - writeback */ - if ( BIT21(i)) - cpu->R[REG_POS(i,16)] = addr; - } - - if ( !(Rd_num & 0x1)) { - /* Store/Load */ - if ( BIT5(i)) { - WRITE32(cpu->mem_if->data, addr, cpu->R[Rd_num]); - WRITE32(cpu->mem_if->data, addr + 4, cpu->R[Rd_num + 1]); - } - else { - cpu->R[Rd_num] = READ32(cpu->mem_if->data, addr); - cpu->R[Rd_num + 1] = READ32(cpu->mem_if->data, addr + 4); - } - } - - return 3 + (MMU.MMU_WAIT32[PROCNUM][(addr>>24)&0xF] * 2); -} - - - -//---------------------STC---------------------------------- -/* the NDS has no coproc that responses to a STC, no feedback is given to the arm */ - -TEMPLATE static u32 FASTCALL OP_STC_P_IMM_OFF() -{ - TRAPUNDEF(); -} - -TEMPLATE static u32 FASTCALL OP_STC_M_IMM_OFF() -{ - TRAPUNDEF(); -} - -TEMPLATE static u32 FASTCALL OP_STC_P_PREIND() -{ - TRAPUNDEF(); -} - -TEMPLATE static u32 FASTCALL OP_STC_M_PREIND() -{ - TRAPUNDEF(); -} - -TEMPLATE static u32 FASTCALL OP_STC_P_POSTIND() -{ - TRAPUNDEF(); -} - -TEMPLATE static u32 FASTCALL OP_STC_M_POSTIND() -{ - TRAPUNDEF(); -} - -TEMPLATE static u32 FASTCALL OP_STC_OPTION() -{ - TRAPUNDEF(); -} - -//---------------------LDC---------------------------------- -/* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */ - -TEMPLATE static u32 FASTCALL OP_LDC_P_IMM_OFF() -{ - TRAPUNDEF(); -} - -TEMPLATE static u32 FASTCALL OP_LDC_M_IMM_OFF() -{ - TRAPUNDEF(); -} - -TEMPLATE static u32 FASTCALL OP_LDC_P_PREIND() -{ - TRAPUNDEF(); -} - -TEMPLATE static u32 FASTCALL OP_LDC_M_PREIND() -{ - TRAPUNDEF(); -} - -TEMPLATE static u32 FASTCALL OP_LDC_P_POSTIND() -{ - TRAPUNDEF(); -} - -TEMPLATE static u32 FASTCALL OP_LDC_M_POSTIND() -{ - TRAPUNDEF(); -} - -TEMPLATE static u32 FASTCALL OP_LDC_OPTION() -{ - TRAPUNDEF(); - return 2; -} - -//----------------MCR----------------------- - -TEMPLATE static u32 FASTCALL OP_MCR() -{ - const u32 &i = cpu->instruction; - u32 cpnum = REG_POS(i, 8); - - if(!cpu->coproc[cpnum]) - { - emu_halt(); - LOG("Stopped (OP_MCR)\n"); - return 2; - } - - armcp15_moveARM2CP((armcp15_t*)cpu->coproc[cpnum], cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7); - //cpu->coproc[cpnum]->moveARM2CP(cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7); - return 2; -} - -//----------------MRC----------------------- - -TEMPLATE static u32 FASTCALL OP_MRC() -{ - const u32 &i = cpu->instruction; - u32 cpnum = REG_POS(i, 8); - - if(!cpu->coproc[cpnum]) - { - emu_halt(); - LOG("Stopped (OP_MRC)\n"); - return 2; - } - - armcp15_moveCP2ARM((armcp15_t*)cpu->coproc[cpnum], &cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7); - //cpu->coproc[cpnum]->moveCP2ARM(&cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7); - return 4; -} - -//--------------SWI------------------------------- -TEMPLATE static u32 FASTCALL OP_SWI() -{ - if(cpu->swi_tab) { - u32 swinum = (cpu->instruction>>16)&0x1F; - return cpu->swi_tab[swinum]() + 3; - } else { - /* TODO (#1#): translocated SWI vectors */ - /* we use an irq thats not in the irq tab, as - it was replaced duie to a changed intVector */ - Status_Reg tmp = cpu->CPSR; - armcpu_switchMode(cpu, SVC); /* enter svc mode */ - cpu->R[14] = cpu->next_instruction; - cpu->SPSR = tmp; /* save old CPSR as new SPSR */ - cpu->CPSR.bits.T = 0; /* handle as ARM32 code */ - cpu->CPSR.bits.I = 1; - cpu->R[15] = cpu->intVector + 0x08; - cpu->next_instruction = cpu->R[15]; - return 4; - } -} - -//----------------BKPT------------------------- -TEMPLATE static u32 FASTCALL OP_BKPT() -{ - LOG("Stopped (OP_BKPT)\n"); - TRAPUNDEF(); -} - -//----------------CDP----------------------- - -TEMPLATE static u32 FASTCALL OP_CDP() -{ - LOG("Stopped (OP_CDP)\n"); - TRAPUNDEF(); -} - -#define TYPE_RETOUR u32 -#define PARAMETRES -#define CALLTYPE FASTCALL -#define NOM_TAB arm_instructions_set_0 -#define TABDECL(x) x<0> - -#include "instruction_tabdef.inc" - -#undef TYPE_RETOUR -#undef PARAMETRES -#undef CALLTYPE -#undef NOM_TAB -#undef TABDECL - -#define TYPE_RETOUR u32 -#define PARAMETRES -#define CALLTYPE FASTCALL -#define NOM_TAB arm_instructions_set_1 -#define TABDECL(x) x<1> - -#include "instruction_tabdef.inc" +/* Copyright (C) 2006 yopyop + Copyright (C) 2006 shash + yopyop156@ifrance.com + yopyop156.ifrance.com + + Copyright (C) 2006-2007 shash + + This file is part of DeSmuME + + DeSmuME is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + DeSmuME is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with DeSmuME; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include "cp15.h" +#include "debug.h" +#include "MMU.h" +#include "armcpu.h" +#include "NDSSystem.h" + +#define cpu (&ARMPROC) +#define TEMPLATE template + +extern volatile BOOL execute; + +#define LSL_IMM shift_op = cpu->R[REG_POS(i,0)]<<((i>>7)&0x1F); + +#define S_LSL_IMM u32 shift_op = ((i>>7)&0x1F);\ + u32 c = cpu->CPSR.bits.C;\ + if(shift_op==0)\ + shift_op=cpu->R[REG_POS(i,0)];\ + else\ + {\ + c = BIT_N(cpu->R[REG_POS(i,0)], 32-shift_op);\ + shift_op = cpu->R[REG_POS(i,0)]<<((i>>7)&0x1F);\ + } + +#define LSL_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\ + if(shift_op>=32)\ + shift_op=0;\ + else\ + shift_op=cpu->R[REG_POS(i,0)]<R[REG_POS(i,8)])&0xFF;\ + u32 c = cpu->CPSR.bits.C;\ + if(shift_op==0)\ + shift_op=cpu->R[REG_POS(i,0)];\ + else\ + if(shift_op<32)\ + {\ + c = BIT_N(cpu->R[REG_POS(i,0)], 32-shift_op);\ + shift_op = cpu->R[REG_POS(i,0)]<R[REG_POS(i,0)]);\ + }\ + else\ + {\ + shift_op = 0;\ + c = 0;\ + } + +#define LSR_IMM shift_op = ((i>>7)&0x1F);\ + if(shift_op!=0)\ + shift_op = cpu->R[REG_POS(i,0)]>>shift_op; + +#define S_LSR_IMM u32 shift_op = ((i>>7)&0x1F);\ + u32 c = cpu->CPSR.bits.C;\ + if(shift_op==0)\ + {\ + c = BIT31(cpu->R[REG_POS(i,0)]);\ + }\ + else\ + {\ + c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\ + shift_op = cpu->R[REG_POS(i,0)]>>shift_op;\ + } + +#define LSR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\ + if(shift_op>=32)\ + shift_op = 0;\ + else\ + shift_op = cpu->R[REG_POS(i,0)]>>shift_op; + +#define S_LSR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\ + u32 c = cpu->CPSR.bits.C;\ + if(shift_op==0)\ + {\ + shift_op = cpu->R[REG_POS(i,0)];\ + }\ + else\ + if(shift_op<32)\ + {\ + c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\ + shift_op = cpu->R[REG_POS(i,0)]>>shift_op;\ + }\ + else\ + if(shift_op==32)\ + {\ + c = BIT31(cpu->R[REG_POS(i,0)]);\ + shift_op = 0;\ + }\ + else\ + {\ + c = 0;\ + shift_op = 0;\ + } + +#define ASR_IMM shift_op = ((i>>7)&0x1F);\ + if(shift_op==0)\ + shift_op=BIT31(cpu->R[REG_POS(i,0)])*0xFFFFFFFF;\ + else\ + shift_op = (u32)(((s32)(cpu->R[REG_POS(i,0)]))>>shift_op); + +#define S_ASR_IMM u32 shift_op = ((i>>7)&0x1F);\ + u32 c = cpu->CPSR.bits.C;\ + if(shift_op==0)\ + {\ + shift_op=BIT31(cpu->R[REG_POS(i,0)])*0xFFFFFFFF;\ + c = BIT31(cpu->R[REG_POS(i,0)]);\ + }\ + else\ + {\ + c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\ + shift_op = (u32)(((s32)(cpu->R[REG_POS(i,0)]))>>shift_op);\ + } + +#define ASR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\ + if(shift_op==0)\ + shift_op=cpu->R[REG_POS(i,0)];\ + else\ + if(shift_op<32)\ + shift_op = (u32)(((s32)(cpu->R[REG_POS(i,0)]))>>shift_op);\ + else\ + shift_op=BIT31(cpu->R[REG_POS(i,0)])*0xFFFFFFFF; + +#define S_ASR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\ + u32 c = cpu->CPSR.bits.C;\ + if(shift_op==0)\ + shift_op=cpu->R[REG_POS(i,0)];\ + else\ + if(shift_op<32)\ + {\ + c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\ + shift_op = (u32)(((s32)(cpu->R[REG_POS(i,0)]))>>shift_op);\ + }\ + else\ + {\ + c = BIT31(cpu->R[REG_POS(i,0)]);\ + shift_op=BIT31(cpu->R[REG_POS(i,0)])*0xFFFFFFFF;\ + } + +#define ROR_IMM shift_op = ((i>>7)&0x1F);\ + if(shift_op==0)\ + {\ + u32 tmp = cpu->CPSR.bits.C;\ + shift_op = (tmp<<31)|(cpu->R[REG_POS(i,0)]>>1);\ + }\ + else\ + shift_op = ROR(cpu->R[REG_POS(i,0)],shift_op); + +#define S_ROR_IMM u32 shift_op = ((i>>7)&0x1F);\ + u32 c = cpu->CPSR.bits.C;\ + if(shift_op==0)\ + {\ + u32 tmp = cpu->CPSR.bits.C;\ + shift_op = (tmp<<31)|(cpu->R[REG_POS(i,0)]>>1);\ + c = BIT0(cpu->R[REG_POS(i,0)]);\ + }\ + else\ + {\ + c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\ + shift_op = ROR(cpu->R[REG_POS(i,0)],shift_op);\ + } + +#define ROR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\ + if((shift_op==0)||((shift_op&0xF)==0))\ + shift_op=cpu->R[REG_POS(i,0)];\ + else\ + shift_op = ROR(cpu->R[REG_POS(i,0)],(shift_op&0xF)); + +#define S_ROR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\ + u32 c = cpu->CPSR.bits.C;\ + if(shift_op==0)\ + shift_op=cpu->R[REG_POS(i,0)];\ + else\ + {\ + shift_op&=0xF;\ + if(shift_op==0)\ + {\ + shift_op=cpu->R[REG_POS(i,0)];\ + c = BIT31(cpu->R[REG_POS(i,0)]);\ + }\ + else\ + {\ + c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\ + shift_op = ROR(cpu->R[REG_POS(i,0)],(shift_op&0xF));\ + }\ + } + +#define IMM_VALUE u32 shift_op = ROR((i&0xFF), (i>>7)&0x1E); + +#define S_IMM_VALUE u32 shift_op = ROR((i&0xFF), (i>>7)&0x1E);\ + u32 c = cpu->CPSR.bits.C;\ + if((i>>8)&0xF)\ + c = BIT31(shift_op); + +#define IMM_OFF (((i>>4)&0xF0)+(i&0xF)) + +#define IMM_OFF_12 ((i)&0xFFF) + +TEMPLATE static u32 FASTCALL OP_UND() +{ + LOG("Undefined instruction: %08X\n", cpu->instruction); + emu_halt(); + LOG("Stopped (OP_UND)\n"); + return 1; +} + +#define TRAPUNDEF() \ + LOG("Undefined instruction: %#08X PC = %#08X\n", cpu->instruction, cpu->instruct_adr); \ + \ + if (((cpu->intVector != 0) ^ (PROCNUM == ARMCPU_ARM9))){ \ + Status_Reg tmp = cpu->CPSR; \ + armcpu_switchMode(cpu, UND); /* enter und mode */ \ + cpu->R[14] = cpu->R[15] - 4; /* jump to und Vector */ \ + cpu->SPSR = tmp; /* save old CPSR as new SPSR */ \ + cpu->CPSR.bits.T = 0; /* handle as ARM32 code */ \ + cpu->CPSR.bits.I = cpu->SPSR.bits.I; /* keep int disable flag */ \ + cpu->R[15] = cpu->intVector + 0x04; \ + cpu->next_instruction = cpu->R[15]; \ + return 4; \ + } \ + else \ + { \ + emu_halt(); \ + return 4; \ + } \ + +//-----------------------AND------------------------------------ + +#define OP_AND(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] & shift_op;\ + if(REG_POS(i,12)==15)\ + {\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + return a; + +#define OP_ANDS(a, b)\ + if(REG_POS(i,12)==15)\ + {\ + Status_Reg SPSR;\ + cpu->R[15] = cpu->R[REG_POS(i,16)] & shift_op;\ + SPSR = cpu->SPSR;\ + armcpu_switchMode(cpu, SPSR.bits.mode);\ + cpu->CPSR=SPSR;\ + cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] & shift_op;\ + cpu->CPSR.bits.C = c;\ + cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ + return a; + +TEMPLATE static u32 FASTCALL OP_AND_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSL_IMM; + OP_AND(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_AND_LSL_REG() +{ + const u32 &i = cpu->instruction; + LSL_REG; + OP_AND(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_AND_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSR_IMM; + OP_AND(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_AND_LSR_REG() +{ + const u32 &i = cpu->instruction; + LSR_REG; + OP_AND(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_AND_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ASR_IMM; + OP_AND(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_AND_ASR_REG() +{ + const u32 &i = cpu->instruction; + ASR_REG; + OP_AND(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_AND_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ROR_IMM; + OP_AND(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_AND_ROR_REG() +{ + const u32 &i = cpu->instruction; + ROR_REG; + OP_AND(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_AND_IMM_VAL() +{ + const u32 &i = cpu->instruction; + IMM_VALUE; + OP_AND(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_AND_S_LSL_IMM() +{ + const u32 &i = cpu->instruction; + S_LSL_IMM; + OP_ANDS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_AND_S_LSL_REG() +{ + const u32 &i = cpu->instruction; + S_LSL_REG; + OP_ANDS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_AND_S_LSR_IMM() +{ + const u32 &i = cpu->instruction; + S_LSR_IMM; + OP_ANDS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_AND_S_LSR_REG() +{ + const u32 &i = cpu->instruction; + S_LSR_REG; + OP_ANDS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_AND_S_ASR_IMM() +{ + const u32 &i = cpu->instruction; + S_ASR_IMM; + OP_ANDS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_AND_S_ASR_REG() +{ + const u32 &i = cpu->instruction; + S_ASR_REG; + OP_ANDS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_AND_S_ROR_IMM() +{ + const u32 &i = cpu->instruction; + S_ROR_IMM; + OP_ANDS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_AND_S_ROR_REG() +{ + const u32 &i = cpu->instruction; + S_ROR_REG; + OP_ANDS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_AND_S_IMM_VAL() +{ + const u32 &i = cpu->instruction; + S_IMM_VALUE; + OP_ANDS(2, 4); +} + +//--------------EOR------------------------------ + +#define OP_EOR(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] ^ shift_op;\ + if(REG_POS(i,12)==15)\ + {\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + return a; + +#define OP_EORS(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] ^ shift_op;\ + if(REG_POS(i,12)==15)\ + {\ + Status_Reg SPSR = cpu->SPSR;\ + armcpu_switchMode(cpu, SPSR.bits.mode);\ + cpu->CPSR=SPSR;\ + cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + cpu->CPSR.bits.C = c;\ + cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ + return a; + +TEMPLATE static u32 FASTCALL OP_EOR_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSL_IMM; + OP_EOR(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_EOR_LSL_REG() +{ + const u32 &i = cpu->instruction; + LSL_REG; + OP_EOR(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_EOR_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSR_IMM; + OP_EOR(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_EOR_LSR_REG() +{ + const u32 &i = cpu->instruction; + LSR_REG; + OP_EOR(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_EOR_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ASR_IMM; + OP_EOR(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_EOR_ASR_REG() +{ + const u32 &i = cpu->instruction; + ASR_REG; + OP_EOR(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_EOR_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ROR_IMM; + OP_EOR(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_EOR_ROR_REG() +{ + const u32 &i = cpu->instruction; + ROR_REG; + OP_EOR(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_EOR_IMM_VAL() +{ + const u32 &i = cpu->instruction; + IMM_VALUE; + OP_EOR(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_EOR_S_LSL_IMM() +{ + const u32 &i = cpu->instruction; + S_LSL_IMM; + OP_EORS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_EOR_S_LSL_REG() +{ + const u32 &i = cpu->instruction; + S_LSL_REG; + OP_EORS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_EOR_S_LSR_IMM() +{ + const u32 &i = cpu->instruction; + S_LSR_IMM; + OP_EORS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_EOR_S_LSR_REG() +{ + const u32 &i = cpu->instruction; + S_LSR_REG; + OP_EORS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_EOR_S_ASR_IMM() +{ + const u32 &i = cpu->instruction; + S_ASR_IMM; + OP_EORS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_EOR_S_ASR_REG() +{ + const u32 &i = cpu->instruction; + S_ASR_REG; + OP_EORS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_EOR_S_ROR_IMM() +{ + const u32 &i = cpu->instruction; + S_ROR_IMM; + OP_EORS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_EOR_S_ROR_REG() +{ + const u32 &i = cpu->instruction; + S_ROR_REG; + OP_EORS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_EOR_S_IMM_VAL() +{ + const u32 &i = cpu->instruction; + S_IMM_VALUE; + OP_EORS(2, 4); +} + +//-------------SUB------------------------------------- + +#define OP_SUB(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] - shift_op;\ + if(REG_POS(i,12)==15)\ + {\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + return a; + +#define OPSUBS(a, b) cpu->R[REG_POS(i,12)] = v - shift_op;\ + if(REG_POS(i,12)==15)\ + {\ + Status_Reg SPSR = cpu->SPSR;\ + armcpu_switchMode(cpu, SPSR.bits.mode);\ + cpu->CPSR=SPSR;\ + cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ + cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\ + cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\ + return a; + +TEMPLATE static u32 FASTCALL OP_SUB_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSL_IMM; + OP_SUB(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_SUB_LSL_REG() +{ + const u32 &i = cpu->instruction; + LSL_REG; + OP_SUB(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_SUB_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSR_IMM; + OP_SUB(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_SUB_LSR_REG() +{ + const u32 &i = cpu->instruction; + LSR_REG; + OP_SUB(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_SUB_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ASR_IMM; + OP_SUB(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_SUB_ASR_REG() +{ + const u32 &i = cpu->instruction; + ASR_REG; + OP_SUB(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_SUB_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ROR_IMM; + OP_SUB(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_SUB_ROR_REG() +{ + const u32 &i = cpu->instruction; + ROR_REG; + OP_SUB(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_SUB_IMM_VAL() +{ + const u32 &i = cpu->instruction; + IMM_VALUE; + OP_SUB(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_SUB_S_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + LSL_IMM; + OPSUBS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_SUB_S_LSL_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + LSL_REG; + OPSUBS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_SUB_S_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + LSR_IMM; + OPSUBS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_SUB_S_LSR_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + LSR_REG; + OPSUBS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_SUB_S_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + ASR_IMM; + OPSUBS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_SUB_S_ASR_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + ASR_REG; + OPSUBS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_SUB_S_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + ROR_IMM; + OPSUBS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_SUB_S_ROR_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + ROR_REG; + OPSUBS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_SUB_S_IMM_VAL() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + IMM_VALUE; + OPSUBS(2, 4); +} + +//------------------RSB------------------------ + +#define OP_RSB(a, b) cpu->R[REG_POS(i,12)] = shift_op - cpu->R[REG_POS(i,16)];\ + if(REG_POS(i,12)==15)\ + {\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + return a; + +#define OP_RSBS(a, b) cpu->R[REG_POS(i,12)] = shift_op - v;\ + if(REG_POS(i,12)==15)\ + {\ + Status_Reg SPSR = cpu->SPSR;\ + armcpu_switchMode(cpu, SPSR.bits.mode);\ + cpu->CPSR=SPSR;\ + cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ + cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(shift_op, v, cpu->R[REG_POS(i,12)]);\ + cpu->CPSR.bits.V = SIGNED_UNDERFLOW(shift_op, v, cpu->R[REG_POS(i,12)]);\ + return a; + +TEMPLATE static u32 FASTCALL OP_RSB_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSL_IMM; + OP_RSB(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_RSB_LSL_REG() +{ + const u32 &i = cpu->instruction; + LSL_REG; + OP_RSB(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_RSB_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSR_IMM; + OP_RSB(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_RSB_LSR_REG() +{ + const u32 &i = cpu->instruction; + LSR_REG; + OP_RSB(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_RSB_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ASR_IMM; + OP_RSB(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_RSB_ASR_REG() +{ + const u32 &i = cpu->instruction; + ASR_REG; + OP_RSB(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_RSB_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ROR_IMM; + OP_RSB(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_RSB_ROR_REG() +{ + const u32 &i = cpu->instruction; + ROR_REG; + OP_RSB(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_RSB_IMM_VAL() +{ + const u32 &i = cpu->instruction; + IMM_VALUE; + OP_RSB(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_RSB_S_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + LSL_IMM; + OP_RSBS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_RSB_S_LSL_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + LSL_REG; + OP_RSBS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_RSB_S_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + LSR_IMM; + OP_RSBS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_RSB_S_LSR_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + LSR_REG; + OP_RSBS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_RSB_S_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + ASR_IMM; + OP_RSBS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_RSB_S_ASR_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + ASR_REG; + OP_RSBS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_RSB_S_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + ROR_IMM; + OP_RSBS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_RSB_S_ROR_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + ROR_REG; + OP_RSBS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_RSB_S_IMM_VAL() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + IMM_VALUE; + OP_RSBS(2, 4); +} + +//------------------ADD----------------------------------- + +#define OP_ADD(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] + shift_op;\ + if(REG_POS(i,12)==15)\ + {\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + return a; + +TEMPLATE static u32 FASTCALL OP_ADD_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSL_IMM; + OP_ADD(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_ADD_LSL_REG() +{ + const u32 &i = cpu->instruction; + LSL_REG; + OP_ADD(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ADD_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSR_IMM; + OP_ADD(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_ADD_LSR_REG() +{ + const u32 &i = cpu->instruction; + LSR_REG; + OP_ADD(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ADD_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ASR_IMM; + OP_ADD(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_ADD_ASR_REG() +{ + const u32 &i = cpu->instruction; + ASR_REG; + OP_ADD(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ADD_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ROR_IMM; + OP_ADD(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_ADD_ROR_REG() +{ + const u32 &i = cpu->instruction; + ROR_REG; + OP_ADD(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ADD_IMM_VAL() +{ + const u32 &i = cpu->instruction; + IMM_VALUE; + OP_ADD(1, 3); +} + +#define OP_ADDS(a, b) cpu->R[REG_POS(i,12)] = v + shift_op;\ + if(REG_POS(i,12)==15)\ + {\ + Status_Reg SPSR = cpu->SPSR;\ + armcpu_switchMode(cpu, SPSR.bits.mode);\ + cpu->CPSR=SPSR;\ + cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ + cpu->CPSR.bits.C = UNSIGNED_OVERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\ + cpu->CPSR.bits.V = SIGNED_OVERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\ + return a; + +TEMPLATE static u32 FASTCALL OP_ADD_S_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + LSL_IMM; + OP_ADDS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ADD_S_LSL_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + LSL_REG; + OP_ADDS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_ADD_S_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + LSR_IMM; + OP_ADDS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ADD_S_LSR_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + LSR_REG; + OP_ADDS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_ADD_S_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + ASR_IMM; + OP_ADDS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ADD_S_ASR_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + ASR_REG; + OP_ADDS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_ADD_S_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + ROR_IMM; + OP_ADDS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ADD_S_ROR_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + ROR_REG; + OP_ADDS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_ADD_S_IMM_VAL() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + IMM_VALUE; + OP_ADDS(2, 4); +} + +//------------------ADC----------------------------------- + +#define OP_ADC(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] + shift_op + cpu->CPSR.bits.C;\ + if(REG_POS(i,12)==15)\ + {\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + return a; + +TEMPLATE static u32 FASTCALL OP_ADC_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSL_IMM; + OP_ADC(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_ADC_LSL_REG() +{ + const u32 &i = cpu->instruction; + LSL_REG; + OP_ADC(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ADC_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSR_IMM; + OP_ADC(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_ADC_LSR_REG() +{ + const u32 &i = cpu->instruction; + LSR_REG; + OP_ADC(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ADC_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ASR_IMM; + OP_ADC(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_ADC_ASR_REG() +{ + const u32 &i = cpu->instruction; + ASR_REG; + OP_ADC(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ADC_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ROR_IMM; + OP_ADC(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_ADC_ROR_REG() +{ + const u32 &i = cpu->instruction; + ROR_REG; + OP_ADC(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ADC_IMM_VAL() +{ + const u32 &i = cpu->instruction; + IMM_VALUE; + OP_ADC(1, 3); +} + +#define OP_ADCS(a, b) \ + { \ + u32 tmp = shift_op + cpu->CPSR.bits.C;\ + cpu->R[REG_POS(i,12)] = v + tmp;\ + if(REG_POS(i,12)==15)\ + {\ + Status_Reg SPSR = cpu->SPSR;\ + armcpu_switchMode(cpu, SPSR.bits.mode);\ + cpu->CPSR=SPSR;\ + cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ + cpu->CPSR.bits.C = UNSIGNED_OVERFLOW(shift_op, (u32) cpu->CPSR.bits.C, tmp) | UNSIGNED_OVERFLOW(v, tmp, cpu->R[REG_POS(i,12)]);\ + cpu->CPSR.bits.V = SIGNED_OVERFLOW(shift_op, (u32) cpu->CPSR.bits.C, tmp) | SIGNED_OVERFLOW(v, tmp, cpu->R[REG_POS(i,12)]);\ + return a; \ + } + +TEMPLATE static u32 FASTCALL OP_ADC_S_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + LSL_IMM; + OP_ADCS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ADC_S_LSL_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + LSL_REG; + OP_ADCS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_ADC_S_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + LSR_IMM; + OP_ADCS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ADC_S_LSR_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + LSR_REG; + OP_ADCS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_ADC_S_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + ASR_IMM; + OP_ADCS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ADC_S_ASR_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + ASR_REG; + OP_ADCS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_ADC_S_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + ROR_IMM; + OP_ADCS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ADC_S_ROR_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + ROR_REG; + OP_ADCS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_ADC_S_IMM_VAL() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + IMM_VALUE; + OP_ADCS(2, 4); +} + +//-------------SBC------------------------------------- + +#define OP_SBC(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] - shift_op - (!cpu->CPSR.bits.C);\ + if(REG_POS(i,12)==15)\ + {\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + return a; + +TEMPLATE static u32 FASTCALL OP_SBC_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSL_IMM; + OP_SBC(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_SBC_LSL_REG() +{ + const u32 &i = cpu->instruction; + LSL_REG; + OP_SBC(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_SBC_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSR_IMM; + OP_SBC(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_SBC_LSR_REG() +{ + const u32 &i = cpu->instruction; + LSR_REG; + OP_SBC(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_SBC_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ASR_IMM; + OP_SBC(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_SBC_ASR_REG() +{ + const u32 &i = cpu->instruction; + ASR_REG; + OP_SBC(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_SBC_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ROR_IMM; + OP_SBC(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_SBC_ROR_REG() +{ + const u32 &i = cpu->instruction; + ROR_REG; + OP_SBC(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_SBC_IMM_VAL() +{ + const u32 &i = cpu->instruction; + IMM_VALUE; + OP_SBC(1, 3); +} + +#define OP_SBCS(a, b) \ + { \ + u32 tmp = v - (!cpu->CPSR.bits.C);\ + cpu->R[REG_POS(i,12)] = tmp - shift_op;\ + if(REG_POS(i,12)==15)\ + {\ + Status_Reg SPSR = cpu->SPSR;\ + armcpu_switchMode(cpu, SPSR.bits.mode);\ + cpu->CPSR=SPSR;\ + cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ + cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\ + cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\ + return a; \ + } + +TEMPLATE static u32 FASTCALL OP_SBC_S_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + LSL_IMM; + OP_SBCS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_SBC_S_LSL_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + LSL_REG; + OP_SBCS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_SBC_S_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + LSR_IMM; + OP_SBCS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_SBC_S_LSR_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + LSR_REG; + OP_SBCS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_SBC_S_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + ASR_IMM; + OP_SBCS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_SBC_S_ASR_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + ASR_REG; + OP_SBCS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_SBC_S_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + ROR_IMM; + OP_SBCS(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_SBC_S_ROR_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + ROR_REG; + OP_SBCS(3, 5); +} + +TEMPLATE static u32 FASTCALL OP_SBC_S_IMM_VAL() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + IMM_VALUE; + OP_SBCS(2, 4); +} + +//---------------RSC---------------------------------- + +#define OP_RSC(a, b) cpu->R[REG_POS(i,12)] = shift_op - cpu->R[REG_POS(i,16)] - (!cpu->CPSR.bits.C);\ + if(REG_POS(i,12)==15)\ + {\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + return a; + +TEMPLATE static u32 FASTCALL OP_RSC_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSL_IMM; + OP_RSC(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_RSC_LSL_REG() +{ + const u32 &i = cpu->instruction; + LSL_REG; + OP_RSC(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_RSC_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSR_IMM; + OP_RSC(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_RSC_LSR_REG() +{ + const u32 &i = cpu->instruction; + LSR_REG; + OP_RSC(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_RSC_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ASR_IMM; + OP_RSC(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_RSC_ASR_REG() +{ + const u32 &i = cpu->instruction; + ASR_REG; + OP_RSC(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_RSC_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ROR_IMM; + OP_RSC(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_RSC_ROR_REG() +{ + const u32 &i = cpu->instruction; + ROR_REG; + OP_RSC(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_RSC_IMM_VAL() +{ + const u32 &i = cpu->instruction; + IMM_VALUE; + OP_RSC(1, 3); +} + +#define OP_RSCS(a,b) \ + { \ + u32 tmp = shift_op - (!cpu->CPSR.bits.C);\ + cpu->R[REG_POS(i,12)] = tmp - v;\ + if(REG_POS(i,12)==15)\ + {\ + Status_Reg SPSR = cpu->SPSR;\ + armcpu_switchMode(cpu, SPSR.bits.mode);\ + cpu->CPSR=SPSR;\ + cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ + cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\ + cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\ + return a; \ + } + +TEMPLATE static u32 FASTCALL OP_RSC_S_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + LSL_IMM; + OP_RSCS(2,4); +} + +TEMPLATE static u32 FASTCALL OP_RSC_S_LSL_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + LSL_REG; + OP_RSCS(3,5); +} + +TEMPLATE static u32 FASTCALL OP_RSC_S_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + LSR_IMM; + OP_RSCS(2,4); +} + +TEMPLATE static u32 FASTCALL OP_RSC_S_LSR_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + LSR_REG; + OP_RSCS(3,5); +} + +TEMPLATE static u32 FASTCALL OP_RSC_S_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + ASR_IMM; + OP_RSCS(2,4); +} + +TEMPLATE static u32 FASTCALL OP_RSC_S_ASR_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + ASR_REG; + OP_RSCS(3,5); +} + +TEMPLATE static u32 FASTCALL OP_RSC_S_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + u32 shift_op; + ROR_IMM; + OP_RSCS(2,4); +} + +TEMPLATE static u32 FASTCALL OP_RSC_S_ROR_REG() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + ROR_REG; + OP_RSCS(3,5); +} + +TEMPLATE static u32 FASTCALL OP_RSC_S_IMM_VAL() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,16)]; + IMM_VALUE; + OP_RSCS(2,4); +} + +//-------------------TST---------------------------- + +#define OP_TST(a) \ + { \ + unsigned tmp = cpu->R[REG_POS(i,16)] & shift_op;\ + cpu->CPSR.bits.C = c;\ + cpu->CPSR.bits.N = BIT31(tmp);\ + cpu->CPSR.bits.Z = (tmp==0);\ + return a; \ + } + +TEMPLATE static u32 FASTCALL OP_TST_LSL_IMM() +{ + const u32 &i = cpu->instruction; + S_LSL_IMM; + OP_TST(1); +} + +TEMPLATE static u32 FASTCALL OP_TST_LSL_REG() +{ + const u32 &i = cpu->instruction; + S_LSL_REG; + OP_TST(2); +} + +TEMPLATE static u32 FASTCALL OP_TST_LSR_IMM() +{ + const u32 &i = cpu->instruction; + S_LSR_IMM; + OP_TST(1); +} + +TEMPLATE static u32 FASTCALL OP_TST_LSR_REG() +{ + const u32 &i = cpu->instruction; + S_LSR_REG; + OP_TST(2); +} + +TEMPLATE static u32 FASTCALL OP_TST_ASR_IMM() +{ + const u32 &i = cpu->instruction; + S_ASR_IMM; + OP_TST(1); +} + +TEMPLATE static u32 FASTCALL OP_TST_ASR_REG() +{ + const u32 &i = cpu->instruction; + S_ASR_REG; + OP_TST(2); +} + +TEMPLATE static u32 FASTCALL OP_TST_ROR_IMM() +{ + const u32 &i = cpu->instruction; + S_ROR_IMM; + OP_TST(1); +} + +TEMPLATE static u32 FASTCALL OP_TST_ROR_REG() +{ + const u32 &i = cpu->instruction; + S_ROR_REG; + OP_TST(2); +} + +TEMPLATE static u32 FASTCALL OP_TST_IMM_VAL() +{ + const u32 &i = cpu->instruction; + S_IMM_VALUE; + OP_TST(1); +} + +//-------------------TEQ---------------------------- + +#define OP_TEQ(a) \ + { \ + unsigned tmp = cpu->R[REG_POS(i,16)] ^ shift_op;\ + cpu->CPSR.bits.C = c;\ + cpu->CPSR.bits.N = BIT31(tmp);\ + cpu->CPSR.bits.Z = (tmp==0);\ + return a; \ + } + +TEMPLATE static u32 FASTCALL OP_TEQ_LSL_IMM() +{ + const u32 &i = cpu->instruction; + S_LSL_IMM; + OP_TEQ(1); +} + +TEMPLATE static u32 FASTCALL OP_TEQ_LSL_REG() +{ + const u32 &i = cpu->instruction; + S_LSL_REG; + OP_TEQ(2); +} + +TEMPLATE static u32 FASTCALL OP_TEQ_LSR_IMM() +{ + const u32 &i = cpu->instruction; + S_LSR_IMM; + OP_TEQ(1); +} + +TEMPLATE static u32 FASTCALL OP_TEQ_LSR_REG() +{ + const u32 &i = cpu->instruction; + S_LSR_REG; + OP_TEQ(2); +} + +TEMPLATE static u32 FASTCALL OP_TEQ_ASR_IMM() +{ + const u32 &i = cpu->instruction; + S_ASR_IMM; + OP_TEQ(1); +} + +TEMPLATE static u32 FASTCALL OP_TEQ_ASR_REG() +{ + const u32 &i = cpu->instruction; + S_ASR_REG; + OP_TEQ(2); +} + +TEMPLATE static u32 FASTCALL OP_TEQ_ROR_IMM() +{ + const u32 &i = cpu->instruction; + S_ROR_IMM; + OP_TEQ(1); +} + +TEMPLATE static u32 FASTCALL OP_TEQ_ROR_REG() +{ + const u32 &i = cpu->instruction; + S_ROR_REG; + OP_TEQ(2); +} + +TEMPLATE static u32 FASTCALL OP_TEQ_IMM_VAL() +{ + const u32 &i = cpu->instruction; + S_IMM_VALUE; + OP_TEQ(1); +} + +//-------------CMP------------------------------------- + +#define OP_CMP(a) \ + { \ + u32 tmp = cpu->R[REG_POS(i,16)] - shift_op;\ + cpu->CPSR.bits.N = BIT31(tmp);\ + cpu->CPSR.bits.Z = (tmp==0);\ + cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(cpu->R[REG_POS(i,16)], shift_op, tmp);\ + cpu->CPSR.bits.V = SIGNED_UNDERFLOW(cpu->R[REG_POS(i,16)], shift_op, tmp);\ + return a; \ + } + +TEMPLATE static u32 FASTCALL OP_CMP_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSL_IMM; + OP_CMP(1); +} + +TEMPLATE static u32 FASTCALL OP_CMP_LSL_REG() +{ + const u32 &i = cpu->instruction; + LSL_REG; + OP_CMP(2); +} + +TEMPLATE static u32 FASTCALL OP_CMP_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSR_IMM; + OP_CMP(1); +} + +TEMPLATE static u32 FASTCALL OP_CMP_LSR_REG() +{ + const u32 &i = cpu->instruction; + LSR_REG; + OP_CMP(2); +} + +TEMPLATE static u32 FASTCALL OP_CMP_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ASR_IMM; + OP_CMP(1); +} + +TEMPLATE static u32 FASTCALL OP_CMP_ASR_REG() +{ + const u32 &i = cpu->instruction; + ASR_REG; + OP_CMP(2); +} + +TEMPLATE static u32 FASTCALL OP_CMP_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ROR_IMM; + OP_CMP(1); +} + +TEMPLATE static u32 FASTCALL OP_CMP_ROR_REG() +{ + const u32 &i = cpu->instruction; + ROR_REG; + OP_CMP(2); +} + +TEMPLATE static u32 FASTCALL OP_CMP_IMM_VAL() +{ + const u32 &i = cpu->instruction; + IMM_VALUE; + OP_CMP(1); +} + +//---------------CMN--------------------------- + +#define OP_CMN(a) \ + { \ + u32 tmp = cpu->R[REG_POS(i,16)] + shift_op;\ + cpu->CPSR.bits.N = BIT31(tmp);\ + cpu->CPSR.bits.Z = (tmp==0);\ + cpu->CPSR.bits.C = UNSIGNED_OVERFLOW(cpu->R[REG_POS(i,16)], shift_op, tmp);\ + cpu->CPSR.bits.V = SIGNED_OVERFLOW(cpu->R[REG_POS(i,16)], shift_op, tmp);\ + return a; \ + } + +TEMPLATE static u32 FASTCALL OP_CMN_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSL_IMM; + OP_CMN(1); +} + +TEMPLATE static u32 FASTCALL OP_CMN_LSL_REG() +{ + const u32 &i = cpu->instruction; + LSL_REG; + OP_CMN(2); +} + +TEMPLATE static u32 FASTCALL OP_CMN_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSR_IMM; + OP_CMN(1); +} + +TEMPLATE static u32 FASTCALL OP_CMN_LSR_REG() +{ + const u32 &i = cpu->instruction; + LSR_REG; + OP_CMN(2); +} + +TEMPLATE static u32 FASTCALL OP_CMN_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ASR_IMM; + OP_CMN(1); +} + +TEMPLATE static u32 FASTCALL OP_CMN_ASR_REG() +{ + const u32 &i = cpu->instruction; + ASR_REG; + OP_CMN(2); +} + +TEMPLATE static u32 FASTCALL OP_CMN_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ROR_IMM; + OP_CMN(1); +} + +TEMPLATE static u32 FASTCALL OP_CMN_ROR_REG() +{ + const u32 &i = cpu->instruction; + ROR_REG; + OP_CMN(2); +} + +TEMPLATE static u32 FASTCALL OP_CMN_IMM_VAL() +{ + const u32 &i = cpu->instruction; + IMM_VALUE; + OP_CMN(1); +} + +//------------------ORR------------------- + +#define OP_ORR(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] | shift_op;\ + if(REG_POS(i,12)==15)\ + {\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + return a; + +TEMPLATE static u32 FASTCALL OP_ORR_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSL_IMM; + OP_ORR(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_ORR_LSL_REG() +{ + const u32 &i = cpu->instruction; + LSL_REG; + OP_ORR(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ORR_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSR_IMM; + OP_ORR(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_ORR_LSR_REG() +{ + const u32 &i = cpu->instruction; + LSR_REG; + OP_ORR(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ORR_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ASR_IMM; + OP_ORR(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_ORR_ASR_REG() +{ + const u32 &i = cpu->instruction; + ASR_REG; + OP_ORR(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ORR_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ROR_IMM; + OP_ORR(1, 3); +} + +TEMPLATE static u32 FASTCALL OP_ORR_ROR_REG() +{ + const u32 &i = cpu->instruction; + ROR_REG; + OP_ORR(2, 4); +} + +TEMPLATE static u32 FASTCALL OP_ORR_IMM_VAL() +{ + const u32 &i = cpu->instruction; + IMM_VALUE; + OP_ORR(1, 3); +} + +#define OP_ORRS(a,b) \ + { \ + cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] | shift_op; \ + if(REG_POS(i,12)==15) \ + { \ + Status_Reg SPSR = cpu->SPSR; \ + armcpu_switchMode(cpu, SPSR.bits.mode); \ + cpu->CPSR=SPSR; \ + cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1)); \ + cpu->next_instruction = cpu->R[15]; \ + return b; \ + } \ + cpu->CPSR.bits.C = c; \ + cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \ + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \ + return a; \ + } + +TEMPLATE static u32 FASTCALL OP_ORR_S_LSL_IMM() +{ + const u32 &i = cpu->instruction; + S_LSL_IMM; + OP_ORRS(2,4); +} + +TEMPLATE static u32 FASTCALL OP_ORR_S_LSL_REG() +{ + const u32 &i = cpu->instruction; + S_LSL_REG; + OP_ORRS(3,5); +} + +TEMPLATE static u32 FASTCALL OP_ORR_S_LSR_IMM() +{ + const u32 &i = cpu->instruction; + S_LSR_IMM; + OP_ORRS(2,4); +} + +TEMPLATE static u32 FASTCALL OP_ORR_S_LSR_REG() +{ + const u32 &i = cpu->instruction; + S_LSR_REG; + OP_ORRS(3,5); +} + +TEMPLATE static u32 FASTCALL OP_ORR_S_ASR_IMM() +{ + const u32 &i = cpu->instruction; + S_ASR_IMM; + OP_ORRS(2,4); +} + +TEMPLATE static u32 FASTCALL OP_ORR_S_ASR_REG() +{ + const u32 &i = cpu->instruction; + S_ASR_REG; + OP_ORRS(3,5); +} + +TEMPLATE static u32 FASTCALL OP_ORR_S_ROR_IMM() +{ + const u32 &i = cpu->instruction; + S_ROR_IMM; + OP_ORRS(2,4); +} + +TEMPLATE static u32 FASTCALL OP_ORR_S_ROR_REG() +{ + const u32 &i = cpu->instruction; + S_ROR_REG; + OP_ORRS(3,5); +} + +TEMPLATE static u32 FASTCALL OP_ORR_S_IMM_VAL() +{ + const u32 &i = cpu->instruction; + S_IMM_VALUE; + OP_ORRS(2,4); +} + +//------------------MOV------------------- + +#define OP_MOV(a, b) cpu->R[REG_POS(i,12)] = shift_op;\ + if(REG_POS(i,12)==15)\ + {\ + cpu->next_instruction = shift_op;\ + return b;\ + }\ + return a; + +#define OP_MOV_S(a, b) cpu->R[REG_POS(i,12)] = shift_op;\ + if(BIT20(i) && REG_POS(i,12)==15)\ + {\ + Status_Reg SPSR = cpu->SPSR;\ + armcpu_switchMode(cpu, SPSR.bits.mode);\ + cpu->CPSR=SPSR;\ + cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + cpu->CPSR.bits.C = c;\ + cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ + return a;\ + +TEMPLATE static u32 FASTCALL OP_MOV_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSL_IMM; + OP_MOV(1,3); +} + +TEMPLATE static u32 FASTCALL OP_MOV_LSL_REG() +{ + const u32 &i = cpu->instruction; + LSL_REG; + if (REG_POS(i,0) == 15) shift_op += 4; + OP_MOV(2,4); +} + +TEMPLATE static u32 FASTCALL OP_MOV_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSR_IMM; + OP_MOV(1,3); +} + +TEMPLATE static u32 FASTCALL OP_MOV_LSR_REG() +{ + const u32 &i = cpu->instruction; + LSR_REG; + if (REG_POS(i,0) == 15) shift_op += 4; + OP_MOV(2,4); +} + +TEMPLATE static u32 FASTCALL OP_MOV_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ASR_IMM; + OP_MOV(1,3); +} + +TEMPLATE static u32 FASTCALL OP_MOV_ASR_REG() +{ + const u32 &i = cpu->instruction; + ASR_REG; + OP_MOV(2,4); +} + +TEMPLATE static u32 FASTCALL OP_MOV_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ROR_IMM; + OP_MOV(2,4); +} + +TEMPLATE static u32 FASTCALL OP_MOV_ROR_REG() +{ + const u32 &i = cpu->instruction; + ROR_REG; + OP_MOV(2,4); +} + +TEMPLATE static u32 FASTCALL OP_MOV_IMM_VAL() +{ + const u32 &i = cpu->instruction; + IMM_VALUE; + OP_MOV(1,3); +} + +TEMPLATE static u32 FASTCALL OP_MOV_S_LSL_IMM() +{ + const u32 &i = cpu->instruction; + S_LSL_IMM; + OP_MOV_S(2,4); +} + +TEMPLATE static u32 FASTCALL OP_MOV_S_LSL_REG() +{ + const u32 &i = cpu->instruction; + S_LSL_REG; + if (REG_POS(i,0) == 15) shift_op += 4; + OP_MOV_S(3,5); +} + +TEMPLATE static u32 FASTCALL OP_MOV_S_LSR_IMM() +{ + const u32 &i = cpu->instruction; + S_LSR_IMM; + OP_MOV_S(2,4); +} + +TEMPLATE static u32 FASTCALL OP_MOV_S_LSR_REG() +{ + const u32 &i = cpu->instruction; + S_LSR_REG; + if (REG_POS(i,0) == 15) shift_op += 4; + OP_MOV_S(3,5); +} + +TEMPLATE static u32 FASTCALL OP_MOV_S_ASR_IMM() +{ + const u32 &i = cpu->instruction; + S_ASR_IMM; + OP_MOV_S(2,4); +} + +TEMPLATE static u32 FASTCALL OP_MOV_S_ASR_REG() +{ + const u32 &i = cpu->instruction; + S_ASR_REG; + OP_MOV_S(3,5); +} + +TEMPLATE static u32 FASTCALL OP_MOV_S_ROR_IMM() +{ + const u32 &i = cpu->instruction; + S_ROR_IMM; + OP_MOV_S(2,4); +} + +TEMPLATE static u32 FASTCALL OP_MOV_S_ROR_REG() +{ + const u32 &i = cpu->instruction; + S_ROR_REG; + OP_MOV_S(3,5); +} + +TEMPLATE static u32 FASTCALL OP_MOV_S_IMM_VAL() +{ + const u32 &i = cpu->instruction; + S_IMM_VALUE; + OP_MOV_S(2,4); +} + +//------------------BIC------------------- +#define OPP_BIC(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] & (~shift_op);\ + if(REG_POS(i,12)==15)\ + {\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + return a; + +#define OPP_BIC_S(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] & (~shift_op);\ + if(REG_POS(i,12)==15)\ + {\ + Status_Reg SPSR = cpu->SPSR;\ + armcpu_switchMode(cpu, SPSR.bits.mode);\ + cpu->CPSR=SPSR;\ + cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + cpu->CPSR.bits.C = c;\ + cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ + return a; + +TEMPLATE static u32 FASTCALL OP_BIC_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSL_IMM; + OPP_BIC(1,3); +} + +TEMPLATE static u32 FASTCALL OP_BIC_LSL_REG() +{ + const u32 &i = cpu->instruction; + LSL_REG; + OPP_BIC(2,4); +} + +TEMPLATE static u32 FASTCALL OP_BIC_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSR_IMM; + OPP_BIC(1,3); +} + +TEMPLATE static u32 FASTCALL OP_BIC_LSR_REG() +{ + const u32 &i = cpu->instruction; + LSR_REG; + OPP_BIC(2,4); +} + +TEMPLATE static u32 FASTCALL OP_BIC_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ASR_IMM; + OPP_BIC(1,3); +} + +TEMPLATE static u32 FASTCALL OP_BIC_ASR_REG() +{ + const u32 &i = cpu->instruction; + ASR_REG; + OPP_BIC(2,4); +} + +TEMPLATE static u32 FASTCALL OP_BIC_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ROR_IMM; + OPP_BIC(1,3); +} + +TEMPLATE static u32 FASTCALL OP_BIC_ROR_REG() +{ + const u32 &i = cpu->instruction; + ROR_REG; + OPP_BIC(2,4); +} + +TEMPLATE static u32 FASTCALL OP_BIC_IMM_VAL() +{ + const u32 &i = cpu->instruction; + IMM_VALUE; + OPP_BIC(1,3); +} + +TEMPLATE static u32 FASTCALL OP_BIC_S_LSL_IMM() +{ + const u32 &i = cpu->instruction; + S_LSL_IMM; + OPP_BIC_S(2,4); +} + +TEMPLATE static u32 FASTCALL OP_BIC_S_LSL_REG() +{ + const u32 &i = cpu->instruction; + S_LSL_REG; + OPP_BIC_S(3,5); +} + +TEMPLATE static u32 FASTCALL OP_BIC_S_LSR_IMM() +{ + const u32 &i = cpu->instruction; + S_LSR_IMM; + OPP_BIC_S(2,4); +} + +TEMPLATE static u32 FASTCALL OP_BIC_S_LSR_REG() +{ + const u32 &i = cpu->instruction; + S_LSR_REG; + OPP_BIC_S(3,5); +} + +TEMPLATE static u32 FASTCALL OP_BIC_S_ASR_IMM() +{ + const u32 &i = cpu->instruction; + S_ASR_IMM; + OPP_BIC_S(2,4); +} + +TEMPLATE static u32 FASTCALL OP_BIC_S_ASR_REG() +{ + const u32 &i = cpu->instruction; + S_ASR_REG; + OPP_BIC_S(3,5); +} + +TEMPLATE static u32 FASTCALL OP_BIC_S_ROR_IMM() +{ + const u32 &i = cpu->instruction; + S_ROR_IMM; + OPP_BIC_S(2,4); +} + +TEMPLATE static u32 FASTCALL OP_BIC_S_ROR_REG() +{ + const u32 &i = cpu->instruction; + S_ROR_REG; + OPP_BIC_S(3,5); +} + +TEMPLATE static u32 FASTCALL OP_BIC_S_IMM_VAL() +{ + const u32 &i = cpu->instruction; + S_IMM_VALUE; + OPP_BIC_S(2,4); +} + +//------------------MVN------------------- +#define OPP_MVN(a, b) cpu->R[REG_POS(i,12)] = ~shift_op;\ + if(REG_POS(i,12)==15)\ + {\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + return a; + +#define OPP_MVN_S(a, b) cpu->R[REG_POS(i,12)] = ~shift_op;\ + if(REG_POS(i,12)==15)\ + {\ + Status_Reg SPSR = cpu->SPSR;\ + armcpu_switchMode(cpu, SPSR.bits.mode);\ + cpu->CPSR=SPSR;\ + cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\ + cpu->next_instruction = cpu->R[15];\ + return b;\ + }\ + cpu->CPSR.bits.C = c;\ + cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ + return a; + +TEMPLATE static u32 FASTCALL OP_MVN_LSL_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSL_IMM; + OPP_MVN(1,3); +} + +TEMPLATE static u32 FASTCALL OP_MVN_LSL_REG() +{ + const u32 &i = cpu->instruction; + LSL_REG; + OPP_MVN(2,4); +} + +TEMPLATE static u32 FASTCALL OP_MVN_LSR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + LSR_IMM; + OPP_MVN(1,3); +} + +TEMPLATE static u32 FASTCALL OP_MVN_LSR_REG() +{ + const u32 &i = cpu->instruction; + LSR_REG; + OPP_MVN(2,4); +} + +TEMPLATE static u32 FASTCALL OP_MVN_ASR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ASR_IMM; + OPP_MVN(1,3); +} + +TEMPLATE static u32 FASTCALL OP_MVN_ASR_REG() +{ + const u32 &i = cpu->instruction; + ASR_REG; + OPP_MVN(2,4); +} + +TEMPLATE static u32 FASTCALL OP_MVN_ROR_IMM() +{ + const u32 &i = cpu->instruction; + u32 shift_op; + ROR_IMM; + OPP_MVN(1,3); +} + +TEMPLATE static u32 FASTCALL OP_MVN_ROR_REG() +{ + const u32 &i = cpu->instruction; + ROR_REG; + OPP_MVN(2,4); +} + +TEMPLATE static u32 FASTCALL OP_MVN_IMM_VAL() +{ + const u32 &i = cpu->instruction; + IMM_VALUE; + OPP_MVN(1,3); +} + +TEMPLATE static u32 FASTCALL OP_MVN_S_LSL_IMM() +{ + const u32 &i = cpu->instruction; + S_LSL_IMM; + OPP_MVN_S(2,4); +} + +TEMPLATE static u32 FASTCALL OP_MVN_S_LSL_REG() +{ + const u32 &i = cpu->instruction; + S_LSL_REG; + OPP_MVN_S(3,5); +} + +TEMPLATE static u32 FASTCALL OP_MVN_S_LSR_IMM() +{ + const u32 &i = cpu->instruction; + S_LSR_IMM; + OPP_MVN_S(2,4); +} + +TEMPLATE static u32 FASTCALL OP_MVN_S_LSR_REG() +{ + const u32 &i = cpu->instruction; + S_LSR_REG; + OPP_MVN_S(3,5); +} + +TEMPLATE static u32 FASTCALL OP_MVN_S_ASR_IMM() +{ + const u32 &i = cpu->instruction; + S_ASR_IMM; + OPP_MVN_S(2,4); +} + +TEMPLATE static u32 FASTCALL OP_MVN_S_ASR_REG() +{ + const u32 &i = cpu->instruction; + S_ASR_REG; + OPP_MVN_S(3,5); +} + +TEMPLATE static u32 FASTCALL OP_MVN_S_ROR_IMM() +{ + const u32 &i = cpu->instruction; + S_ROR_IMM; + OPP_MVN_S(2,4); +} + +TEMPLATE static u32 FASTCALL OP_MVN_S_ROR_REG() +{ + const u32 &i = cpu->instruction; + S_ROR_REG; + OPP_MVN_S(3,5); +} + +TEMPLATE static u32 FASTCALL OP_MVN_S_IMM_VAL() +{ + const u32 &i = cpu->instruction; + S_IMM_VALUE; + OPP_MVN_S(2,4); +} + +//-------------MUL------------------------ +#define OPP_M(a,b) v >>= 8;\ + if((v==0)||(v==0xFFFFFF))\ + return b;\ + v >>= 8;\ + if((v==0)||(v==0xFFFF))\ + return b+1;\ + v >>= 8;\ + if((v==0)||(v==0xFF))\ + return b+2;\ + return a;\ + +TEMPLATE static u32 FASTCALL OP_MUL() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,0)]; + cpu->R[REG_POS(i,16)] = cpu->R[REG_POS(i,8)] * v; + OPP_M(5,2); +} + +TEMPLATE static u32 FASTCALL OP_MLA() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,0)]; + u32 a = cpu->R[REG_POS(i,8)]; + u32 b = cpu->R[REG_POS(i,12)]; + cpu->R[REG_POS(i,16)] = a * v + b; + + OPP_M(6,3); +} + +TEMPLATE static u32 FASTCALL OP_MUL_S() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,0)]; + cpu->R[REG_POS(i,16)] = cpu->R[REG_POS(i,8)] * v; + + cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]); + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0); + + OPP_M(6,3); +} + +TEMPLATE static u32 FASTCALL OP_MLA_S() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,0)]; + cpu->R[REG_POS(i,16)] = cpu->R[REG_POS(i,8)] * v + cpu->R[REG_POS(i,12)]; + cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]); + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0); + OPP_M(7,4); +} + +//----------UMUL-------------------------- + +TEMPLATE static u32 FASTCALL OP_UMULL() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,0)]; + u64 res = (u64)v * (u64)cpu->R[REG_POS(i,8)]; + + cpu->R[REG_POS(i,12)] = (u32)res; + cpu->R[REG_POS(i,16)] = (u32)(res>>32); + + OPP_M(6,3); +} + +TEMPLATE static u32 FASTCALL OP_UMLAL() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,0)]; + u64 res = (u64)v * (u64)cpu->R[REG_POS(i,8)] + (u64)cpu->R[REG_POS(i,12)]; + + cpu->R[REG_POS(i,12)] = (u32)res; + cpu->R[REG_POS(i,16)] += (u32)(res>>32); + + OPP_M(7,4); +} + +TEMPLATE static u32 FASTCALL OP_UMULL_S() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,0)]; + u64 res = (u64)v * (u64)cpu->R[REG_POS(i,8)]; + + cpu->R[REG_POS(i,12)] = (u32)res; + cpu->R[REG_POS(i,16)] = (u32)(res>>32); + + cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]); + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0); + + OPP_M(7,4); +} + +TEMPLATE static u32 FASTCALL OP_UMLAL_S() +{ + const u32 &i = cpu->instruction; + u32 v = cpu->R[REG_POS(i,0)]; + u64 res = (u64)v * (u64)cpu->R[REG_POS(i,8)] + (u64)cpu->R[REG_POS(i,12)]; + + cpu->R[REG_POS(i,12)] = (u32)res; + cpu->R[REG_POS(i,16)] += (u32)(res>>32); + + cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]); + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0); + + OPP_M(8,5); +} + +//----------SMUL-------------------------- + +TEMPLATE static u32 FASTCALL OP_SMULL() +{ + const u32 &i = cpu->instruction; + s64 v = (s32)cpu->R[REG_POS(i,0)]; + s64 b = (s32)cpu->R[REG_POS(i,8)]; + s64 res = v * b; + + cpu->R[REG_POS(i,12)] = (u32)(res&0xFFFFFFFF); + cpu->R[REG_POS(i,16)] = (u32)(res>>32); + + v &= 0xFFFFFFFF; + + OPP_M(6,3); +} + +TEMPLATE static u32 FASTCALL OP_SMLAL() +{ + const u32 &i = cpu->instruction; + + s64 v = (s32)cpu->R[REG_POS(i,0)]; + s64 b = (s32)cpu->R[REG_POS(i,8)]; + s64 res = v * b + (u64)cpu->R[REG_POS(i,12)]; + + //LOG("%08X * %08X + %08X%08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], cpu->R[REG_POS(i,16)], cpu->R[REG_POS(i,12)]); + + cpu->R[REG_POS(i,12)] = (u32)res; + cpu->R[REG_POS(i,16)] += (u32)(res>>32); + + //LOG("= %08X%08X %08X%08X\r\n", cpu->R[REG_POS(i,16)], cpu->R[REG_POS(i,12)], res); + + v &= 0xFFFFFFFF; + + OPP_M(7,4); +} + +TEMPLATE static u32 FASTCALL OP_SMULL_S() +{ + const u32 &i = cpu->instruction; + s64 v = (s32)cpu->R[REG_POS(i,0)]; + s64 b = (s32)cpu->R[REG_POS(i,8)]; + s64 res = v * b; + + cpu->R[REG_POS(i,12)] = (u32)res; + cpu->R[REG_POS(i,16)] = (u32)(res>>32); + + cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]); + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0); + + v &= 0xFFFFFFFF; + + OPP_M(7,4); +} + +TEMPLATE static u32 FASTCALL OP_SMLAL_S() +{ + const u32 &i = cpu->instruction; + s64 v = (s32)cpu->R[REG_POS(i,0)]; + s64 b = (s32)cpu->R[REG_POS(i,8)]; + s64 res = v * b + (u64)cpu->R[REG_POS(i,12)]; + + cpu->R[REG_POS(i,12)] = (u32)res; + cpu->R[REG_POS(i,16)] += (u32)(res>>32); + + cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]); + cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0); + + v &= 0xFFFFFFFF; + + OPP_M(8,5); +} + +//---------------SWP------------------------------ + +TEMPLATE static u32 FASTCALL OP_SWP() +{ + u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + u32 tmp = ROR(READ32(cpu->mem_if->data, adr), ((cpu->R[REG_POS(i,16)]&3)<<3)); + + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,0)]); + cpu->R[REG_POS(i,12)] = tmp; + + return 4 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]*2; +} + +TEMPLATE static u32 FASTCALL OP_SWPB() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + u8 tmp = READ8(cpu->mem_if->data, adr); + WRITE8(cpu->mem_if->data, adr, (u8)(cpu->R[REG_POS(i,0)]&0xFF)); + cpu->R[REG_POS(i,12)] = tmp; + + return 4 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]*2; +} + +//------------LDRH----------------------------- + +TEMPLATE static u32 FASTCALL OP_LDRH_P_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRH_M_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRH_P_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRH_M_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_P_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_M_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); + + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_P_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] =(u32)READ16(cpu->mem_if->data, adr); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRH_PRE_INDE_M_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_P_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] += IMM_OFF; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_M_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] -= IMM_OFF; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_P_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRH_POS_INDE_M_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +//------------STRH----------------------------- + +TEMPLATE static u32 FASTCALL OP_STRH_P_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRH_M_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRH_P_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRH_M_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_P_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; + cpu->R[REG_POS(i,16)] = adr; + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_M_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_P_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRH_PRE_INDE_M_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_P_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] += IMM_OFF; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_M_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] -= IMM_OFF; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_P_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRH_POS_INDE_M_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +//----------------LDRSH-------------------------- + +TEMPLATE static u32 FASTCALL OP_LDRSH_P_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSH_M_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSH_P_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSH_M_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_P_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,16)] = adr; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_M_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,16)] = adr; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_P_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,16)] = adr; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSH_PRE_INDE_M_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,16)] = adr; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_P_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,16)] += IMM_OFF; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_M_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,16)] -= IMM_OFF; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_P_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSH_POS_INDE_M_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +//----------------------LDRSB---------------------- + +TEMPLATE static u32 FASTCALL OP_LDRSB_P_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSB_M_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSB_P_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSB_M_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_P_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF; + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,16)] = adr; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_M_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF; + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,16)] = adr; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_P_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)]; + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,16)] = adr; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSB_PRE_INDE_M_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)]; + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,16)] = adr; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_P_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,16)] += IMM_OFF; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_M_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,16)] -= IMM_OFF; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_P_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)]; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRSB_POS_INDE_M_REG_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr)); + cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)]; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +//--------------MRS-------------------------------- + +TEMPLATE static u32 FASTCALL OP_MRS_CPSR() +{ + cpu->R[REG_POS(cpu->instruction,12)] = cpu->CPSR.val; + + return 1; +} + +TEMPLATE static u32 FASTCALL OP_MRS_SPSR() +{ + cpu->R[REG_POS(cpu->instruction,12)] = cpu->SPSR.val; + + return 1; +} + +//--------------MSR-------------------------------- + +TEMPLATE static u32 FASTCALL OP_MSR_CPSR() +{ + const u32 &i = cpu->instruction; + u32 operand = cpu->R[REG_POS(i,0)]; + + if(cpu->CPSR.bits.mode!=USR) + { + if(BIT16(i)) + { + armcpu_switchMode(cpu, operand & 0x1F); + cpu->CPSR.val = (cpu->CPSR.val & 0xFFFFFF00) | (operand & 0xFF); + } + if(BIT17(i)) + cpu->CPSR.val = (cpu->CPSR.val & 0xFFFF00FF) | (operand & 0xFF00); + if(BIT18(i)) + cpu->CPSR.val = (cpu->CPSR.val & 0xFF00FFFF) | (operand & 0xFF0000); + } + if(BIT19(i)) + cpu->CPSR.val = (cpu->CPSR.val & 0x00FFFFFF) | (operand & 0xFF000000); + + return 1; +} + +TEMPLATE static u32 FASTCALL OP_MSR_SPSR() +{ + const u32 &i = cpu->instruction; + u32 operand = cpu->R[REG_POS(i,0)]; + + if(cpu->CPSR.bits.mode!=USR) + { + if(BIT16(i)) + { + cpu->SPSR.val = (cpu->SPSR.val & 0xFFFFFF00) | (operand & 0XFF); + } + if(BIT17(i)) + cpu->SPSR.val = (cpu->SPSR.val & 0xFFFF00FF) | (operand & 0XFF00); + if(BIT18(i)) + cpu->SPSR.val = (cpu->SPSR.val & 0xFF00FFFF) | (operand & 0XFF0000); + } + if(BIT19(i)) + cpu->SPSR.val = (cpu->SPSR.val & 0x00FFFFFF) | (operand & 0XFF000000); + + return 1; +} + +TEMPLATE static u32 FASTCALL OP_MSR_CPSR_IMM_VAL() +{ + const u32 &i = cpu->instruction; + IMM_VALUE; + + if(cpu->CPSR.bits.mode!=USR) + { + if(BIT16(i)) + { + armcpu_switchMode(cpu, shift_op & 0x1F); + cpu->CPSR.val = (cpu->CPSR.val & 0xFFFFFF00) | (shift_op & 0XFF); + } + if(BIT17(i)) + cpu->CPSR.val = (cpu->CPSR.val & 0xFFFF00FF) | (shift_op & 0XFF00); + if(BIT18(i)) + cpu->CPSR.val = (cpu->CPSR.val & 0xFF00FFFF) | (shift_op & 0XFF0000); + } + if(BIT19(i)) + { + //cpu->CPSR.val = (cpu->CPSR.val & 0xFF000000) | (shift_op & 0XFF000000); + cpu->CPSR.val = (cpu->CPSR.val & 0x00FFFFFF) | (shift_op & 0xFF000000); + } + + return 1; +} + +TEMPLATE static u32 FASTCALL OP_MSR_SPSR_IMM_VAL() +{ + const u32 &i = cpu->instruction; + IMM_VALUE; + + if(cpu->CPSR.bits.mode!=USR) + { + if(BIT16(i)) + { + cpu->SPSR.val = (cpu->SPSR.val & 0xFFFFFF00) | (shift_op & 0XFF); + } + if(BIT17(i)) + cpu->SPSR.val = (cpu->SPSR.val & 0xFFFF00FF) | (shift_op & 0XFF00); + if(BIT18(i)) + cpu->SPSR.val = (cpu->SPSR.val & 0xFF00FFFF) | (shift_op & 0XFF0000); + } + if(BIT19(i)) + cpu->SPSR.val = (cpu->SPSR.val & 0xFF000000) | (shift_op & 0XFF000000); + + return 1; +} + +//-----------------BRANCH-------------------------- + +TEMPLATE static u32 FASTCALL OP_BX() +{ + u32 tmp = cpu->R[REG_POS(cpu->instruction, 0)]; + + cpu->CPSR.bits.T = BIT0(tmp); + cpu->R[15] = tmp & 0xFFFFFFFE; + cpu->next_instruction = cpu->R[15]; + return 3; +} + +TEMPLATE static u32 FASTCALL OP_BLX_REG() +{ + u32 tmp = cpu->R[REG_POS(cpu->instruction, 0)]; + + cpu->R[14] = cpu->next_instruction; + cpu->CPSR.bits.T = BIT0(tmp); + cpu->R[15] = tmp & 0xFFFFFFFE; + cpu->next_instruction = cpu->R[15]; + return 3; +} + +#define SIGNEXTEND_24(i) (((s32)((i)<<8))>>8) + +TEMPLATE static u32 FASTCALL OP_B() +{ + u32 off = SIGNEXTEND_24(cpu->instruction); + if(CONDITION(cpu->instruction)==0xF) + { + cpu->R[14] = cpu->next_instruction; + cpu->CPSR.bits.T = 1; + } + cpu->R[15] += (off<<2); + cpu->next_instruction = cpu->R[15]; + + return 3; +} + +TEMPLATE static u32 FASTCALL OP_BL() +{ + u32 off = SIGNEXTEND_24(cpu->instruction); + if(CONDITION(cpu->instruction)==0xF) + { + cpu->CPSR.bits.T = 1; + cpu->R[15] += 2; + } + cpu->R[14] = cpu->next_instruction; + cpu->R[15] += (off<<2); + cpu->next_instruction = cpu->R[15]; + + return 3; +} + +//----------------CLZ------------------------------- + +u8 CLZ_TAB[16]= +{ + 0, // 0000 + 1, // 0001 + 2, 2, // 001X + 3, 3, 3, 3, // 01XX + 4, 4, 4, 4, 4, 4, 4, 4 // 1XXX +}; + +TEMPLATE static u32 FASTCALL OP_CLZ() +{ + const u32 &i = cpu->instruction; + u32 Rm = cpu->R[REG_POS(i,0)]; + u32 pos; + + if(Rm==0) + { + cpu->R[REG_POS(i,12)]=32; + return 2; + } + + Rm |= (Rm >>1); + Rm |= (Rm >>2); + Rm |= (Rm >>4); + Rm |= (Rm >>8); + Rm |= (Rm >>16); + + pos = + CLZ_TAB[Rm&0xF] + + CLZ_TAB[(Rm>>4)&0xF] + + CLZ_TAB[(Rm>>8)&0xF] + + CLZ_TAB[(Rm>>12)&0xF] + + CLZ_TAB[(Rm>>16)&0xF] + + CLZ_TAB[(Rm>>20)&0xF] + + CLZ_TAB[(Rm>>24)&0xF] + + CLZ_TAB[(Rm>>28)&0xF]; + + cpu->R[REG_POS(i,12)]=32 - pos; + + return 2; +} + +//--------------------QADD--QSUB------------------------------ + +TEMPLATE static u32 FASTCALL OP_QADD() +{ + const u32 &i = cpu->instruction; + u32 res = cpu->R[REG_POS(i,16)]+cpu->R[REG_POS(i,0)]; + + LOG("spe add\r\n"); + if(SIGNED_OVERFLOW(cpu->R[REG_POS(i,16)],cpu->R[REG_POS(i,0)], res)) + { + cpu->CPSR.bits.Q=1; + cpu->R[REG_POS(i,12)]=0x80000000-BIT31(res); + return 2; + } + cpu->R[REG_POS(i,12)]=res; + if(REG_POS(i,12)==15) + { + cpu->R[15] &= 0XFFFFFFFC; + cpu->next_instruction = cpu->R[15]; + return 3; + } + return 2; +} + +TEMPLATE static u32 FASTCALL OP_QSUB() +{ + const u32 &i = cpu->instruction; + u32 res = cpu->R[REG_POS(i,0)]-cpu->R[REG_POS(i,16)]; + + LOG("spe add\r\n"); + if(SIGNED_UNDERFLOW(cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,16)], res)) + { + cpu->CPSR.bits.Q=1; + cpu->R[REG_POS(i,12)]=0x80000000-BIT31(res); + return 2; + } + cpu->R[REG_POS(i,12)]=res; + if(REG_POS(i,12)==15) + { + cpu->R[15] &= 0XFFFFFFFC; + cpu->next_instruction = cpu->R[15]; + return 3; + } + return 2; +} + +TEMPLATE static u32 FASTCALL OP_QDADD() +{ + const u32 &i = cpu->instruction; + u32 mul = cpu->R[REG_POS(i,16)]<<1; + u32 res; + + + LOG("spe add\r\n"); + if(BIT31(cpu->R[REG_POS(i,16)])!=BIT31(mul)) + { + cpu->CPSR.bits.Q=1; + mul = 0x80000000-BIT31(mul); + } + + res = mul + cpu->R[REG_POS(i,0)]; + if(SIGNED_OVERFLOW(cpu->R[REG_POS(i,0)],mul, res)) + { + cpu->CPSR.bits.Q=1; + cpu->R[REG_POS(i,12)]=0x80000000-BIT31(res); + return 2; + } + cpu->R[REG_POS(i,12)]=res; + if(REG_POS(i,12)==15) + { + cpu->R[15] &= 0XFFFFFFFC; + cpu->next_instruction = cpu->R[15]; + return 3; + } + return 2; +} + +TEMPLATE static u32 FASTCALL OP_QDSUB() +{ + const u32 &i = cpu->instruction; + u32 mul = cpu->R[REG_POS(i,16)]<<1; + u32 res; + + + LOG("spe add\r\n"); + if(BIT31(cpu->R[REG_POS(i,16)])!=BIT31(mul)) + { + cpu->CPSR.bits.Q=1; + mul = 0x80000000-BIT31(mul); + } + + res = cpu->R[REG_POS(i,0)] - mul; + if(SIGNED_UNDERFLOW(cpu->R[REG_POS(i,0)], mul, res)) + { + cpu->CPSR.bits.Q=1; + cpu->R[REG_POS(i,12)]=0x80000000-BIT31(res); + return 2; + } + cpu->R[REG_POS(i,12)]=res; + if(REG_POS(i,12)==15) + { + cpu->R[15] &= 0XFFFFFFFC; + cpu->next_instruction = cpu->R[15]; + return 3; + } + return 2; +} + +//-----------------SMUL------------------------------- + +#define HWORD(i) ((s32)(((s32)(i))>>16)) +#define LWORD(i) (s32)(((s32)((i)<<16))>>16) + +TEMPLATE static u32 FASTCALL OP_SMUL_B_B() +{ + const u32 &i = cpu->instruction; + + cpu->R[REG_POS(i,16)] = (u32)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); + + return 2; +} + +TEMPLATE static u32 FASTCALL OP_SMUL_B_T() +{ + const u32 &i = cpu->instruction; + + cpu->R[REG_POS(i,16)] = (u32)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); + + return 2; +} + +TEMPLATE static u32 FASTCALL OP_SMUL_T_B() +{ + const u32 &i = cpu->instruction; + + cpu->R[REG_POS(i,16)] = (u32)(HWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); + + return 2; +} + +TEMPLATE static u32 FASTCALL OP_SMUL_T_T() +{ + const u32 &i = cpu->instruction; + + cpu->R[REG_POS(i,16)] = (u32)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); + + return 2; +} + +//-----------SMLA---------------------------- + +TEMPLATE static u32 FASTCALL OP_SMLA_B_B() +{ + const u32 &i = cpu->instruction; + u32 tmp = (u32)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); + u32 a = cpu->R[REG_POS(i,12)]; + + //LOG("SMLABB %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a); + cpu->R[REG_POS(i,16)] = tmp + a; + + if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)])) + cpu->CPSR.bits.Q = 1; + + return 2; +} + +TEMPLATE static u32 FASTCALL OP_SMLA_B_T() +{ + const u32 &i = cpu->instruction; + u32 tmp = (u32)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); + u32 a = cpu->R[REG_POS(i,12)]; + + //LOG("SMLABT %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a); + cpu->R[REG_POS(i,16)] = tmp + a; + + if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)])) + cpu->CPSR.bits.Q = 1; + + return 2; +} + +TEMPLATE static u32 FASTCALL OP_SMLA_T_B() +{ + const u32 &i = cpu->instruction; + u32 tmp = (u32)(HWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); + u32 a = cpu->R[REG_POS(i,12)]; + + //LOG("SMLATB %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a); + cpu->R[REG_POS(i,16)] = tmp + a; + + if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)])) + cpu->CPSR.bits.Q = 1; + + return 2; +} + +TEMPLATE static u32 FASTCALL OP_SMLA_T_T() +{ + const u32 &i = cpu->instruction; + u32 tmp = (u32)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); + u32 a = cpu->R[REG_POS(i,12)]; + + //LOG("SMLATT %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a); + cpu->R[REG_POS(i,16)] = tmp + a; + + if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)])) + cpu->CPSR.bits.Q = 1; + + return 2; +} + +//--------------SMLAL--------------------------------------- + +TEMPLATE static u32 FASTCALL OP_SMLAL_B_B() +{ + const u32 &i = cpu->instruction; + s64 tmp = (s64)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)])); + u64 res = (u64)tmp + cpu->R[REG_POS(i,12)]; + + LOG("SMLALBB %08X * %08X + %08X%08X = %08X%08X\r\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + (res + ((tmp<0)*0xFFFFFFFF))), (int)(u32) res); + + cpu->R[REG_POS(i,12)] = (u32) res; + cpu->R[REG_POS(i,16)] += (res + ((tmp<0)*0xFFFFFFFF)); + + return 2; +} + +TEMPLATE static u32 FASTCALL OP_SMLAL_B_T() +{ + const u32 &i = cpu->instruction; + s64 tmp = (s64)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); + u64 res = (u64)tmp + cpu->R[REG_POS(i,12)]; + + LOG("SMLALBT %08X * %08X + %08X%08X = %08X%08X\r\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(u32) res); + + cpu->R[REG_POS(i,12)] = (u32) res; + cpu->R[REG_POS(i,16)] += res + ((tmp<0)*0xFFFFFFFF); + + return 2; +} + +TEMPLATE static u32 FASTCALL OP_SMLAL_T_B() +{ + const u32 &i = cpu->instruction; + s64 tmp = (s64)(HWORD(cpu->R[REG_POS(i,0)])* (s64)LWORD(cpu->R[REG_POS(i,8)])); + u64 res = (u64)tmp + cpu->R[REG_POS(i,12)]; + + LOG("SMLALTB %08X * %08X + %08X%08X = %08X%08X\r\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(u32) res); + + cpu->R[REG_POS(i,12)] = (u32) res; + cpu->R[REG_POS(i,16)] += res + ((tmp<0)*0xFFFFFFFF); + + return 2; +} + +TEMPLATE static u32 FASTCALL OP_SMLAL_T_T() +{ + const u32 &i = cpu->instruction; + s64 tmp = (s64)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)])); + u64 res = (u64)tmp + cpu->R[REG_POS(i,12)]; + + LOG("SMLALTT %08X * %08X + %08X%08X = %08X%08X\r\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(u32) res); + + cpu->R[REG_POS(i,12)] = (u32) res; + cpu->R[REG_POS(i,16)] += res + ((tmp<0)*0xFFFFFFFF); + + return 2; +} + +//--------------SMULW-------------------- + +TEMPLATE static u32 FASTCALL OP_SMULW_B() +{ + const u32 &i = cpu->instruction; + s64 tmp = (s64)LWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); + + //LOG("SMULWB %08X * %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], ((tmp>>16)&0xFFFFFFFF); + + cpu->R[REG_POS(i,16)] = ((tmp>>16)&0xFFFFFFFF); + + return 2; +} + +TEMPLATE static u32 FASTCALL OP_SMULW_T() +{ + const u32 &i = cpu->instruction; + s64 tmp = (s64)HWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); + + //LOG("SMULWT %08X * %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], ((tmp>>16)&0xFFFFFFFF)); + + cpu->R[REG_POS(i,16)] = ((tmp>>16)&0xFFFFFFFF); + + return 2; +} + +//--------------SMLAW------------------- +TEMPLATE static u32 FASTCALL OP_SMLAW_B() +{ + const u32 &i = cpu->instruction; + s64 tmp = (s64)LWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); + u32 a = cpu->R[REG_POS(i,12)]; + + //LOG("SMLAWB %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, (tmp>>16) + a); + + tmp = (tmp>>16); + + cpu->R[REG_POS(i,16)] = tmp + a; + + if(SIGNED_OVERFLOW((u32)tmp, a, cpu->R[REG_POS(i,16)])) + cpu->CPSR.bits.Q = 1; + + return 2; +} + +TEMPLATE static u32 FASTCALL OP_SMLAW_T() +{ + const u32 &i = cpu->instruction; + s64 tmp = (s64)HWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]); + u32 a = cpu->R[REG_POS(i,12)]; + + //LOG("SMLAWT %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, ((tmp>>16)&0xFFFFFFFF) + a); + + tmp = ((tmp>>16)&0xFFFFFFFF); + cpu->R[REG_POS(i,16)] = tmp + a; + + if(SIGNED_OVERFLOW((u32)tmp, a, cpu->R[REG_POS(i,16)])) + cpu->CPSR.bits.Q = 1; + + return 2; +} + +//------------LDR--------------------------- + +TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; + u32 val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,12)] = val; + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; + u32 val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; + u32 val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; + u32 val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + u32 val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +//------------------------------------------------------------ +TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND2() +{ + const u32 &i = cpu->instruction; + + u32 adr = cpu->R[REG_POS(i,16)]; + u32 val = READ32(cpu->mem_if->data, adr); + u32 old; + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + old = armcpu_switchMode(cpu, USR); + cpu->R[REG_POS(i,12)] = val; + armcpu_switchMode(cpu, old); + + cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +//------------------------------------------------------------ + +TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + u32 val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr + shift_op; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr + shift_op; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr - shift_op; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr - shift_op; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr + shift_op; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr + shift_op; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr - shift_op; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr - shift_op; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr + shift_op; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr + shift_op; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr - shift_op; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr - shift_op; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr + shift_op; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr + shift_op; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ32(cpu->mem_if->data, adr); + + if(adr&3) + val = ROR(val, 8*(adr&3)); + + if(REG_POS(i,12)==15) + { + cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1)); + cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit; + cpu->next_instruction = cpu->R[15]; + cpu->R[REG_POS(i,16)] = adr - shift_op; + return 5 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; + } + + cpu->R[REG_POS(i,16)] = adr - shift_op; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +//-----------------LDRB------------------------------------------- + +TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; + u32 val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_M_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; + u32 val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; + u32 val = READ8(cpu->mem_if->data, adr); + + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_M_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; + u32 val = READ8(cpu->mem_if->data, adr); + + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + val = READ8(cpu->mem_if->data, adr); + + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + val = READ8(cpu->mem_if->data, adr); + + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] = adr; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_P_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + u32 val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_M_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + u32 val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] = adr + shift_op; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] = adr - shift_op; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] = adr + shift_op; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] = adr - shift_op; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] = adr + shift_op; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] = adr - shift_op; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] = adr + shift_op; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 val; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,16)] = adr - shift_op; + cpu->R[REG_POS(i,12)] = val; + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +//----------------------STR-------------------------------- + +TEMPLATE static u32 FASTCALL OP_STR_P_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + +// emu_halt(); + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_P_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_P_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr + shift_op; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr - shift_op; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr + shift_op; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr - shift_op; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr + shift_op; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr - shift_op; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr + shift_op; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr - shift_op; + + return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; +} + +//-----------------------STRB------------------------------------- + +TEMPLATE static u32 FASTCALL OP_STRB_P_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_M_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_P_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; + WRITE8(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_M_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)] + shift_op; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_PREIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)] - shift_op; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_P_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_M_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr + shift_op; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr - shift_op; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr + shift_op; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr - shift_op; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr + shift_op; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr - shift_op; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr + shift_op; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND() +{ + const u32 &i = cpu->instruction; + u32 adr; + u32 shift_op; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr - shift_op; + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +//-----------------------LDRBT------------------------------------- + +TEMPLATE static u32 FASTCALL OP_LDRBT_P_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 val; + + if(cpu->CPSR.bits.mode==USR) + return 2; + oldmode = armcpu_switchMode(cpu, SYS); + + i = cpu->instruction; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; + + armcpu_switchMode(cpu, oldmode); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRBT_M_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 val; + + if(cpu->CPSR.bits.mode==USR) + return 2; + oldmode = armcpu_switchMode(cpu, SYS); + + //emu_halt(); + LOG("Untested opcode: OP_LDRBT_M_IMM_OFF_POSTIND\n"); + + + i = cpu->instruction; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; + + armcpu_switchMode(cpu, oldmode); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRBT_P_REG_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 val; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + //emu_halt(); + LOG("Untested opcode: OP_LDRBT_P_REG_OFF_POSTIND\n"); + + + i = cpu->instruction; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr + cpu->R[REG_POS(i,0)]; + + armcpu_switchMode(cpu, oldmode); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRBT_P_LSL_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 val; + u32 shift_op; + + if(cpu->CPSR.bits.mode==USR) + return 2; + oldmode = armcpu_switchMode(cpu, SYS); + //emu_halt(); + LOG("Untested opcode: OP_LDRBT_P_LSL_IMM_OFF_POSTIND\n"); + + + i = cpu->instruction; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr + shift_op; + + armcpu_switchMode(cpu, oldmode); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRBT_M_LSL_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 val; + u32 shift_op; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + //emu_halt(); + LOG("Untested opcode: OP_LDRBT_M_LSL_IMM_OFF_POSTIND\n"); + + + i = cpu->instruction; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr - shift_op; + + armcpu_switchMode(cpu, oldmode); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRBT_P_LSR_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 val; + u32 shift_op; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + //emu_halt(); + LOG("Untested opcode: OP_LDRBT_P_LSR_IMM_OFF_POSTIND\n"); + + + i = cpu->instruction; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr + shift_op; + + armcpu_switchMode(cpu, oldmode); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRBT_M_LSR_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 val; + u32 shift_op; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + //emu_halt(); + LOG("Untested opcode: OP_LDRBT_M_LSR_IMM_OFF_POSTIND\n"); + + + i = cpu->instruction; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr - shift_op; + + armcpu_switchMode(cpu, oldmode); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRBT_P_ASR_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 val; + u32 shift_op; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + //emu_halt(); + LOG("Untested opcode: OP_LDRBT_P_ASR_IMM_OFF_POSTIND\n"); + + + i = cpu->instruction; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr + shift_op; + + armcpu_switchMode(cpu, oldmode); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRBT_M_ASR_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 val; + u32 shift_op; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + //emu_halt(); + LOG("Untested opcode: OP_LDRBT_M_ASR_IMM_OFF_POSTIND\n"); + + + i = cpu->instruction; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr - shift_op; + + armcpu_switchMode(cpu, oldmode); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRBT_P_ROR_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 val; + u32 shift_op; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + //emu_halt(); + LOG("Untested opcode: OP_LDRBT_P_ROR_IMM_OFF_POSTIND\n"); + + + i = cpu->instruction; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr + shift_op; + + armcpu_switchMode(cpu, oldmode); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_LDRBT_M_ROR_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 val; + u32 shift_op; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + //emu_halt(); + LOG("Untested opcode: OP_LDRBT_M_ROR_IMM_OFF_POSTIND\n"); + + + i = cpu->instruction; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)]; + val = READ8(cpu->mem_if->data, adr); + cpu->R[REG_POS(i,12)] = val; + cpu->R[REG_POS(i,16)] = adr - shift_op; + + armcpu_switchMode(cpu, oldmode); + + return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +//----------------------STRBT---------------------------- + +TEMPLATE static u32 FASTCALL OP_STRBT_P_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + + + i = cpu->instruction; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12; + + armcpu_switchMode(cpu, oldmode); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRBT_M_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + + + i = cpu->instruction; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12; + + armcpu_switchMode(cpu, oldmode); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRBT_P_REG_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + + + i = cpu->instruction; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr + cpu->R[REG_POS(i,0)]; + + armcpu_switchMode(cpu, oldmode); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRBT_M_REG_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + + + i = cpu->instruction; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr - cpu->R[REG_POS(i,0)]; + + armcpu_switchMode(cpu, oldmode); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRBT_P_LSL_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 shift_op; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + + + i = cpu->instruction; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr + shift_op; + + armcpu_switchMode(cpu, oldmode); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRBT_M_LSL_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 shift_op; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + + + i = cpu->instruction; + LSL_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr - shift_op; + + armcpu_switchMode(cpu, oldmode); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRBT_P_LSR_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 shift_op; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + + + i = cpu->instruction; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr + shift_op; + + armcpu_switchMode(cpu, oldmode); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRBT_M_LSR_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 shift_op; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + + + i = cpu->instruction; + LSR_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr - shift_op; + + armcpu_switchMode(cpu, oldmode); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRBT_P_ASR_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 shift_op; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + + + i = cpu->instruction; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr + shift_op; + + armcpu_switchMode(cpu, oldmode); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRBT_M_ASR_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 shift_op; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + + + i = cpu->instruction; + ASR_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr - shift_op; + + armcpu_switchMode(cpu, oldmode); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRBT_P_ROR_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 shift_op; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + + + i = cpu->instruction; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr + shift_op; + + armcpu_switchMode(cpu, oldmode); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +TEMPLATE static u32 FASTCALL OP_STRBT_M_ROR_IMM_OFF_POSTIND() +{ + u32 oldmode; + u32 i; + u32 adr; + u32 shift_op; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + oldmode = armcpu_switchMode(cpu, SYS); + + + i = cpu->instruction; + ROR_IMM; + adr = cpu->R[REG_POS(i,16)]; + WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]); + cpu->R[REG_POS(i,16)] = adr - shift_op; + + armcpu_switchMode(cpu, oldmode); + + return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF]; +} + +//---------------------LDM----------------------------- + +#define OP_L_IA(reg, adr) if(BIT##reg(i))\ + {\ + registres[reg] = READ32(cpu->mem_if->data, start);\ + c += waitState[(start>>24)&0xF];\ + adr += 4;\ + } + +#define OP_L_IB(reg, adr) if(BIT##reg(i))\ + {\ + adr += 4;\ + registres[reg] = READ32(cpu->mem_if->data, start);\ + c += waitState[(start>>24)&0xF];\ + } + +#define OP_L_DA(reg, adr) if(BIT##reg(i))\ + {\ + registres[reg] = READ32(cpu->mem_if->data, start);\ + c += waitState[(start>>24)&0xF];\ + adr -= 4;\ + } + +#define OP_L_DB(reg, adr) if(BIT##reg(i))\ + {\ + adr -= 4;\ + registres[reg] = READ32(cpu->mem_if->data, start);\ + c += waitState[(start>>24)&0xF];\ + } + +TEMPLATE static u32 FASTCALL OP_LDMIA() +{ + const u32 &i = cpu->instruction; + u32 c = 0; + u32 start = cpu->R[REG_POS(i,16)]; + + u32 * registres = cpu->R; + TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; + + OP_L_IA(0, start); + OP_L_IA(1, start); + OP_L_IA(2, start); + OP_L_IA(3, start); + OP_L_IA(4, start); + OP_L_IA(5, start); + OP_L_IA(6, start); + OP_L_IA(7, start); + OP_L_IA(8, start); + OP_L_IA(9, start); + OP_L_IA(10, start); + OP_L_IA(11, start); + OP_L_IA(12, start); + OP_L_IA(13, start); + OP_L_IA(14, start); + + if(BIT15(i)) + { + u32 tmp = READ32(cpu->mem_if->data, start); + registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); + cpu->CPSR.bits.T = BIT0(tmp); + //start += 4; + cpu->next_instruction = registres[15]; + c += waitState[(start>>24)&0xF]; + } + + return c + 2; +} + +TEMPLATE static u32 FASTCALL OP_LDMIB() +{ + const u32 &i = cpu->instruction; + u32 c = 0; + u32 start = cpu->R[REG_POS(i,16)]; + + u32 * registres = cpu->R; + TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; + + OP_L_IB(0, start); + OP_L_IB(1, start); + OP_L_IB(2, start); + OP_L_IB(3, start); + OP_L_IB(4, start); + OP_L_IB(5, start); + OP_L_IB(6, start); + OP_L_IB(7, start); + OP_L_IB(8, start); + OP_L_IB(9, start); + OP_L_IB(10, start); + OP_L_IB(11, start); + OP_L_IB(12, start); + OP_L_IB(13, start); + OP_L_IB(14, start); + + if(BIT15(i)) + { + u32 tmp; + start += 4; + c += waitState[(start>>24)&0xF]; + tmp = READ32(cpu->mem_if->data, start); + registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); + cpu->CPSR.bits.T = BIT0(tmp); + cpu->next_instruction = registres[15]; + c += 2 + (c==0); + } + + return c + 2; +} + +TEMPLATE static u32 FASTCALL OP_LDMDA() +{ + const u32 &i = cpu->instruction; + u32 c = 0; + u32 start = cpu->R[REG_POS(i,16)]; + + u32 * registres = cpu->R; + TWaitState * waitState = MMU.MMU_WAIT32[PROCNUM]; + + if(BIT15(i)) + { + u32 tmp = READ32(cpu->mem_if->data, start); + registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); + cpu->CPSR.bits.T = BIT0(tmp); + c += waitState[(start>>24)&0xF]; + start -= 4; + cpu->next_instruction = registres[15]; + } + + OP_L_DA(14, start); + OP_L_DA(13, start); + OP_L_DA(12, start); + OP_L_DA(11, start); + OP_L_DA(10, start); + OP_L_DA(9, start); + OP_L_DA(8, start); + OP_L_DA(7, start); + OP_L_DA(6, start); + OP_L_DA(5, start); + OP_L_DA(4, start); + OP_L_DA(3, start); + OP_L_DA(2, start); + OP_L_DA(1, start); + OP_L_DA(0, start); + + return c + 2; +} + +TEMPLATE static u32 FASTCALL OP_LDMDB() +{ + const u32 &i = cpu->instruction; + u32 c = 0; + u32 start = cpu->R[REG_POS(i,16)]; + + u32 * registres = cpu->R; + TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; + + if(BIT15(i)) + { + u32 tmp; + start -= 4; + tmp = READ32(cpu->mem_if->data, start); + registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); + cpu->CPSR.bits.T = BIT0(tmp); + cpu->next_instruction = registres[15]; + c += waitState[(start>>24)&0xF]; + } + + OP_L_DB(14, start); + OP_L_DB(13, start); + OP_L_DB(12, start); + OP_L_DB(11, start); + OP_L_DB(10, start); + OP_L_DB(9, start); + OP_L_DB(8, start); + OP_L_DB(7, start); + OP_L_DB(6, start); + OP_L_DB(5, start); + OP_L_DB(4, start); + OP_L_DB(3, start); + OP_L_DB(2, start); + OP_L_DB(1, start); + OP_L_DB(0, start); + + return c + 2; +} + +TEMPLATE static u32 FASTCALL OP_LDMIA_W() +{ + const u32 &i = cpu->instruction; + u32 c = 0; + u32 start = cpu->R[REG_POS(i,16)]; + u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF; + + u32 * registres = cpu->R; + TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; + + OP_L_IA(0, start); + OP_L_IA(1, start); + OP_L_IA(2, start); + OP_L_IA(3, start); + OP_L_IA(4, start); + OP_L_IA(5, start); + OP_L_IA(6, start); + OP_L_IA(7, start); + OP_L_IA(8, start); + OP_L_IA(9, start); + OP_L_IA(10, start); + OP_L_IA(11, start); + OP_L_IA(12, start); + OP_L_IA(13, start); + OP_L_IA(14, start); + + if(BIT15(i)) + { + u32 tmp = READ32(cpu->mem_if->data, start); + registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); + cpu->CPSR.bits.T = BIT0(tmp); + c += waitState[(start>>24)&0xF]; + start += 4; + cpu->next_instruction = registres[15]; + } + + if(i & (1 << REG_POS(i,16))) { + if(i & bitList) + cpu->R[REG_POS(i,16)] = start; + } + else + cpu->R[REG_POS(i,16)] = start; + + return c + 2; +} + +TEMPLATE static u32 FASTCALL OP_LDMIB_W() +{ + const u32 &i = cpu->instruction; + u32 c = 0; + u32 start = cpu->R[REG_POS(i,16)]; + u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF; + + u32 * registres = cpu->R; + TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; + + OP_L_IB(0, start); + OP_L_IB(1, start); + OP_L_IB(2, start); + OP_L_IB(3, start); + OP_L_IB(4, start); + OP_L_IB(5, start); + OP_L_IB(6, start); + OP_L_IB(7, start); + OP_L_IB(8, start); + OP_L_IB(9, start); + OP_L_IB(10, start); + OP_L_IB(11, start); + OP_L_IB(12, start); + OP_L_IB(13, start); + OP_L_IB(14, start); + + if(BIT15(i)) + { + u32 tmp; + start += 4; + c += waitState[(start>>24)&0xF]; + tmp = READ32(cpu->mem_if->data, start); + registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); + cpu->CPSR.bits.T = BIT0(tmp); + cpu->next_instruction = registres[15]; + c += 2 + (c==0); + } + + if(i & (1 << REG_POS(i,16))) { + if(i & bitList) + cpu->R[REG_POS(i,16)] = start; + } + else + cpu->R[REG_POS(i,16)] = start; + + return c + 2; +} + +TEMPLATE static u32 FASTCALL OP_LDMDA_W() +{ + const u32 &i = cpu->instruction; + u32 c = 0; + u32 start = cpu->R[REG_POS(i,16)]; + u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF; + + u32 * registres = cpu->R; + TWaitState * waitState = MMU.MMU_WAIT32[PROCNUM]; + + if(BIT15(i)) + { + u32 tmp = READ32(cpu->mem_if->data, start); + registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); + cpu->CPSR.bits.T = BIT0(tmp); + c += waitState[(start>>24)&0xF]; + start -= 4; + cpu->next_instruction = registres[15]; + } + + OP_L_DA(14, start); + OP_L_DA(13, start); + OP_L_DA(12, start); + OP_L_DA(11, start); + OP_L_DA(10, start); + OP_L_DA(9, start); + OP_L_DA(8, start); + OP_L_DA(7, start); + OP_L_DA(6, start); + OP_L_DA(5, start); + OP_L_DA(4, start); + OP_L_DA(3, start); + OP_L_DA(2, start); + OP_L_DA(1, start); + OP_L_DA(0, start); + + if(i & (1 << REG_POS(i,16))) { + if(i & bitList) + cpu->R[REG_POS(i,16)] = start; + } + else + cpu->R[REG_POS(i,16)] = start; + + return c + 2; +} + +TEMPLATE static u32 FASTCALL OP_LDMDB_W() +{ + const u32 &i = cpu->instruction; + u32 c = 0; + u32 start = cpu->R[REG_POS(i,16)]; + u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF; + u32 * registres = cpu->R; + TWaitState* waitState = MMU.MMU_WAIT32[PROCNUM]; + + if(BIT15(i)) + { + u32 tmp; + start -= 4; + tmp = READ32(cpu->mem_if->data, start); + registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); + cpu->CPSR.bits.T = BIT0(tmp); + cpu->next_instruction = registres[15]; + c += waitState[(start>>24)&0xF]; + } + + OP_L_DB(14, start); + OP_L_DB(13, start); + OP_L_DB(12, start); + OP_L_DB(11, start); + OP_L_DB(10, start); + OP_L_DB(9, start); + OP_L_DB(8, start); + OP_L_DB(7, start); + OP_L_DB(6, start); + OP_L_DB(5, start); + OP_L_DB(4, start); + OP_L_DB(3, start); + OP_L_DB(2, start); + OP_L_DB(1, start); + OP_L_DB(0, start); + + if(i & (1 << REG_POS(i,16))) { + if(i & bitList) + cpu->R[REG_POS(i,16)] = start; + } + else + cpu->R[REG_POS(i,16)] = start; + + return c + 2; +} + +TEMPLATE static u32 FASTCALL OP_LDMIA2() +{ + const u32 &i = cpu->instruction; + u32 oldmode = 0; + + u32 c = 0; + + u32 start = cpu->R[REG_POS(i,16)]; + u32 * registres; + TWaitState* waitState; + + if(BIT15(i)==0) + { + if(cpu->CPSR.bits.mode==USR) + return 1; + oldmode = armcpu_switchMode(cpu, SYS); + } + + registres = cpu->R; + waitState = MMU.MMU_WAIT32[PROCNUM]; + + OP_L_IA(0, start); + OP_L_IA(1, start); + OP_L_IA(2, start); + OP_L_IA(3, start); + OP_L_IA(4, start); + OP_L_IA(5, start); + OP_L_IA(6, start); + OP_L_IA(7, start); + OP_L_IA(8, start); + OP_L_IA(9, start); + OP_L_IA(10, start); + OP_L_IA(11, start); + OP_L_IA(12, start); + OP_L_IA(13, start); + OP_L_IA(14, start); + + if(BIT15(i) == 0) + { + armcpu_switchMode(cpu, oldmode); + } + else + { + + u32 tmp = READ32(cpu->mem_if->data, start); + Status_Reg SPSR; + cpu->R[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); + SPSR = cpu->SPSR; + armcpu_switchMode(cpu, SPSR.bits.mode); + cpu->CPSR=SPSR; + //start += 4; + cpu->next_instruction = cpu->R[15]; + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + } + return c + 2; +} + +TEMPLATE static u32 FASTCALL OP_LDMIB2() +{ + const u32 &i = cpu->instruction; + u32 oldmode = 0; + u32 c = 0; + + u32 start = cpu->R[REG_POS(i,16)]; + u32 * registres; + TWaitState* waitState; + //emu_halt(); + LOG("Untested opcode: OP_LDMIB2\n"); + + if(BIT15(i)==0) + { + if(cpu->CPSR.bits.mode==USR) + return 2; + oldmode = armcpu_switchMode(cpu, SYS); + } + + registres = cpu->R; + waitState = MMU.MMU_WAIT32[PROCNUM]; + + OP_L_IB(0, start); + OP_L_IB(1, start); + OP_L_IB(2, start); + OP_L_IB(3, start); + OP_L_IB(4, start); + OP_L_IB(5, start); + OP_L_IB(6, start); + OP_L_IB(7, start); + OP_L_IB(8, start); + OP_L_IB(9, start); + OP_L_IB(10, start); + OP_L_IB(11, start); + OP_L_IB(12, start); + OP_L_IB(13, start); + OP_L_IB(14, start); + + if(BIT15(i) == 0) + { + armcpu_switchMode(cpu, oldmode); + } + else + { + u32 tmp; + Status_Reg SPSR; + start += 4; + tmp = READ32(cpu->mem_if->data, start); + registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); + SPSR = cpu->SPSR; + armcpu_switchMode(cpu, SPSR.bits.mode); + cpu->CPSR=SPSR; + cpu->next_instruction = registres[15]; + c += waitState[(start>>24)&0xF]; + } + return c + 2; +} + +TEMPLATE static u32 FASTCALL OP_LDMDA2() +{ + const u32 &i = cpu->instruction; + + u32 oldmode = 0; + u32 c = 0; + u32 * registres; + TWaitState* waitState; + + u32 start = cpu->R[REG_POS(i,16)]; + //emu_halt(); + LOG("Untested opcode: OP_LDMDA2\n"); + + if(BIT15(i)==0) + { + if(cpu->CPSR.bits.mode==USR) + return 2; + oldmode = armcpu_switchMode(cpu, SYS); + } + + registres = cpu->R; + waitState = MMU.MMU_WAIT32[PROCNUM]; + + if(BIT15(i)) + { + u32 tmp = READ32(cpu->mem_if->data, start); + registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); + cpu->CPSR = cpu->SPSR; + c += waitState[(start>>24)&0xF]; + start -= 4; + cpu->next_instruction = registres[15]; + } + + OP_L_DA(14, start); + OP_L_DA(13, start); + OP_L_DA(12, start); + OP_L_DA(11, start); + OP_L_DA(10, start); + OP_L_DA(9, start); + OP_L_DA(8, start); + OP_L_DA(7, start); + OP_L_DA(6, start); + OP_L_DA(5, start); + OP_L_DA(4, start); + OP_L_DA(3, start); + OP_L_DA(2, start); + OP_L_DA(1, start); + OP_L_DA(0, start); + + if(BIT15(i)==0) + { + armcpu_switchMode(cpu, oldmode); + } + else + { + Status_Reg SPSR = cpu->SPSR; + armcpu_switchMode(cpu, SPSR.bits.mode); + cpu->CPSR=SPSR; + } + + return c + 2; +} + +TEMPLATE static u32 FASTCALL OP_LDMDB2() +{ + const u32 &i = cpu->instruction; + + u32 oldmode = 0; + u32 c = 0; + u32 * registres; + TWaitState* waitState; + + u32 start = cpu->R[REG_POS(i,16)]; + if(BIT15(i)==0) + { + if(cpu->CPSR.bits.mode==USR) + return 2; + oldmode = armcpu_switchMode(cpu, SYS); + } + + registres = cpu->R; + waitState = MMU.MMU_WAIT32[PROCNUM]; + + if(BIT15(i)) + { + u32 tmp; + start -= 4; + tmp = READ32(cpu->mem_if->data, start); + registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); + cpu->CPSR = cpu->SPSR; + cpu->next_instruction = registres[15]; + c += waitState[(start>>24)&0xF]; + } + + OP_L_DB(14, start); + OP_L_DB(13, start); + OP_L_DB(12, start); + OP_L_DB(11, start); + OP_L_DB(10, start); + OP_L_DB(9, start); + OP_L_DB(8, start); + OP_L_DB(7, start); + OP_L_DB(6, start); + OP_L_DB(5, start); + OP_L_DB(4, start); + OP_L_DB(3, start); + OP_L_DB(2, start); + OP_L_DB(1, start); + OP_L_DB(0, start); + + if(BIT15(i)==0) + { + armcpu_switchMode(cpu, oldmode); + } + else + { + Status_Reg SPSR = cpu->SPSR; + armcpu_switchMode(cpu, SPSR.bits.mode); + cpu->CPSR=SPSR; + } + + return 2 + c; +} + +TEMPLATE static u32 FASTCALL OP_LDMIA2_W() +{ + const u32 &i = cpu->instruction; + u32 c = 0; + + u32 oldmode = 0; + u32 start = cpu->R[REG_POS(i,16)]; + u32 * registres; + TWaitState* waitState; + u32 tmp; + Status_Reg SPSR; +// emu_halt(); + if(BIT15(i)==0) + { + if(cpu->CPSR.bits.mode==USR) + return 2; + oldmode = armcpu_switchMode(cpu, SYS); + } + + registres = cpu->R; + waitState = MMU.MMU_WAIT32[PROCNUM]; + + OP_L_IA(0, start); + OP_L_IA(1, start); + OP_L_IA(2, start); + OP_L_IA(3, start); + OP_L_IA(4, start); + OP_L_IA(5, start); + OP_L_IA(6, start); + OP_L_IA(7, start); + OP_L_IA(8, start); + OP_L_IA(9, start); + OP_L_IA(10, start); + OP_L_IA(11, start); + OP_L_IA(12, start); + OP_L_IA(13, start); + OP_L_IA(14, start); + + if(BIT15(i)==0) + { + registres[REG_POS(i,16)] = start; + armcpu_switchMode(cpu, oldmode); + return c + 2; + } + + registres[REG_POS(i,16)] = start + 4; + tmp = READ32(cpu->mem_if->data, start); + registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); + SPSR = cpu->SPSR; + armcpu_switchMode(cpu, SPSR.bits.mode); + cpu->CPSR=SPSR; + cpu->next_instruction = registres[15]; + c += waitState[(start>>24)&0xF]; + + return c + 2; +} + +TEMPLATE static u32 FASTCALL OP_LDMIB2_W() +{ + const u32 &i = cpu->instruction; + u32 c = 0; + + u32 oldmode = 0; + u32 start = cpu->R[REG_POS(i,16)]; + u32 * registres; + TWaitState* waitState; + u32 tmp; + Status_Reg SPSR; + + if(BIT15(i)==0) + { + if(cpu->CPSR.bits.mode==USR) + return 2; + oldmode = armcpu_switchMode(cpu, SYS); + } + + registres = cpu->R; + waitState = MMU.MMU_WAIT32[PROCNUM]; + + OP_L_IB(0, start); + OP_L_IB(1, start); + OP_L_IB(2, start); + OP_L_IB(3, start); + OP_L_IB(4, start); + OP_L_IB(5, start); + OP_L_IB(6, start); + OP_L_IB(7, start); + OP_L_IB(8, start); + OP_L_IB(9, start); + OP_L_IB(10, start); + OP_L_IB(11, start); + OP_L_IB(12, start); + OP_L_IB(13, start); + OP_L_IB(14, start); + + if(BIT15(i)==0) + { + armcpu_switchMode(cpu, oldmode); + registres[REG_POS(i,16)] = start; + + return c + 2; + } + + registres[REG_POS(i,16)] = start + 4; + tmp = READ32(cpu->mem_if->data, start + 4); + registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); + cpu->CPSR = cpu->SPSR; + cpu->next_instruction = registres[15]; + SPSR = cpu->SPSR; + armcpu_switchMode(cpu, SPSR.bits.mode); + cpu->CPSR=SPSR; + c += waitState[(start>>24)&0xF]; + + return c + 2; +} + +TEMPLATE static u32 FASTCALL OP_LDMDA2_W() +{ + const u32 &i = cpu->instruction; + u32 c = 0; + + u32 oldmode = 0; + u32 start = cpu->R[REG_POS(i,16)]; + u32 * registres; + TWaitState * waitState; + Status_Reg SPSR; +// emu_halt(); + if(BIT15(i)==0) + { + if(cpu->CPSR.bits.mode==USR) + return 2; + oldmode = armcpu_switchMode(cpu, SYS); + } + + registres = cpu->R; + waitState = MMU.MMU_WAIT32[PROCNUM]; + + if(BIT15(i)) + { + u32 tmp = READ32(cpu->mem_if->data, start); + registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); + c += waitState[(start>>24)&0xF]; + start -= 4; + cpu->next_instruction = registres[15]; + } + + OP_L_DA(14, start); + OP_L_DA(13, start); + OP_L_DA(12, start); + OP_L_DA(11, start); + OP_L_DA(10, start); + OP_L_DA(9, start); + OP_L_DA(8, start); + OP_L_DA(7, start); + OP_L_DA(6, start); + OP_L_DA(5, start); + OP_L_DA(4, start); + OP_L_DA(3, start); + OP_L_DA(2, start); + OP_L_DA(1, start); + OP_L_DA(0, start); + + registres[REG_POS(i,16)] = start; + + if(BIT15(i)==0) + { + armcpu_switchMode(cpu, oldmode); + return c + 2; + } + + SPSR = cpu->SPSR; + armcpu_switchMode(cpu, SPSR.bits.mode); + cpu->CPSR=SPSR; + return c + 2; +} + +TEMPLATE static u32 FASTCALL OP_LDMDB2_W() +{ + const u32 &i = cpu->instruction; + u32 c = 0; + + u32 oldmode = 0; + u32 start = cpu->R[REG_POS(i,16)]; + u32 * registres; + TWaitState* waitState; + Status_Reg SPSR; +// emu_halt(); + if(BIT15(i)==0) + { + if(cpu->CPSR.bits.mode==USR) + return 2; + oldmode = armcpu_switchMode(cpu, SYS); + } + + registres = cpu->R; + waitState = MMU.MMU_WAIT32[PROCNUM]; + + if(BIT15(i)) + { + u32 tmp; + start -= 4; + tmp = READ32(cpu->mem_if->data, start); + c += waitState[(start>>24)&0xF]; + registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); + cpu->CPSR = cpu->SPSR; + cpu->next_instruction = registres[15]; + } + + OP_L_DB(14, start); + OP_L_DB(13, start); + OP_L_DB(12, start); + OP_L_DB(11, start); + OP_L_DB(10, start); + OP_L_DB(9, start); + OP_L_DB(8, start); + OP_L_DB(7, start); + OP_L_DB(6, start); + OP_L_DB(5, start); + OP_L_DB(4, start); + OP_L_DB(3, start); + OP_L_DB(2, start); + OP_L_DB(1, start); + OP_L_DB(0, start); + + registres[REG_POS(i,16)] = start; + + if(BIT15(i)==0) + { + armcpu_switchMode(cpu, oldmode); + return c + 2; + } + + SPSR = cpu->SPSR; + armcpu_switchMode(cpu, SPSR.bits.mode); + cpu->CPSR=SPSR; + return c + 2; +} + +//------------------------------STM---------------------------------- + +TEMPLATE static u32 FASTCALL OP_STMIA() +{ + const u32 &i = cpu->instruction; + u32 c = 0, b; + u32 start = cpu->R[REG_POS(i,16)]; + + for(b=0; b<16; ++b) + { + if(BIT_N(i, b)) + { + WRITE32(cpu->mem_if->data, start, cpu->R[b]); + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + start += 4; + } + } + return c + 1; +} + +TEMPLATE static u32 FASTCALL OP_STMIB() +{ + const u32 &i = cpu->instruction; + u32 c = 0, b; + u32 start = cpu->R[REG_POS(i,16)]; + + for(b=0; b<16; ++b) + { + if(BIT_N(i, b)) + { + start += 4; + WRITE32(cpu->mem_if->data, start, cpu->R[b]); + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + } + } + return c + 1; +} + +TEMPLATE static u32 FASTCALL OP_STMDA() +{ + const u32 &i = cpu->instruction; + u32 c = 0, b; + u32 start = cpu->R[REG_POS(i,16)]; + + for(b=0; b<16; ++b) + { + if(BIT_N(i, 15-b)) + { + WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + start -= 4; + } + } + return c + 1; +} + +TEMPLATE static u32 FASTCALL OP_STMDB() +{ + const u32 &i = cpu->instruction; + u32 c = 0, b; + u32 start = cpu->R[REG_POS(i,16)]; + + for(b=0; b<16; ++b) + { + if(BIT_N(i, 15-b)) + { + start -= 4; + WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + } + } + return c + 1; +} + +TEMPLATE static u32 FASTCALL OP_STMIA_W() +{ + const u32 &i = cpu->instruction; + u32 c = 0, b; + u32 start = cpu->R[REG_POS(i,16)]; + + for(b=0; b<16; ++b) + { + if(BIT_N(i, b)) + { + WRITE32(cpu->mem_if->data, start, cpu->R[b]); + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + start += 4; + } + } + + cpu->R[REG_POS(i,16)] = start; + return c + 1; +} + +TEMPLATE static u32 FASTCALL OP_STMIB_W() +{ + const u32 &i = cpu->instruction; + u32 c = 0, b; + u32 start = cpu->R[REG_POS(i,16)]; + + for(b=0; b<16; ++b) + { + if(BIT_N(i, b)) + { + start += 4; + WRITE32(cpu->mem_if->data, start, cpu->R[b]); + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + } + } + cpu->R[REG_POS(i,16)] = start; + return c + 1; +} + +TEMPLATE static u32 FASTCALL OP_STMDA_W() +{ + const u32 &i = cpu->instruction; + u32 c = 0, b; + u32 start = cpu->R[REG_POS(i,16)]; + + for(b=0; b<16; ++b) + { + if(BIT_N(i, 15-b)) + { + WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + start -= 4; + } + } + + cpu->R[REG_POS(i,16)] = start; + return c + 1; +} + +TEMPLATE static u32 FASTCALL OP_STMDB_W() +{ + const u32 &i = cpu->instruction; + u32 c = 0, b; + u32 start = cpu->R[REG_POS(i,16)]; + + for(b=0; b<16; ++b) + { + if(BIT_N(i, 15-b)) + { + start -= 4; + WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + } + } + + cpu->R[REG_POS(i,16)] = start; + return c + 1; +} + +TEMPLATE static u32 FASTCALL OP_STMIA2() +{ + const u32 &i = cpu->instruction; + u32 c, b; + u32 start; + u32 oldmode; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + c = 0; + start = cpu->R[REG_POS(i,16)]; + oldmode = armcpu_switchMode(cpu, SYS); + + //emu_halt(); + LOG("Untested opcode: OP_STMIA2\n"); + + for(b=0; b<16; ++b) + { + if(BIT_N(i, b)) + { + WRITE32(cpu->mem_if->data, start, cpu->R[b]); + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + start += 4; + } + } + + armcpu_switchMode(cpu, oldmode); + return c + 1; +} + +TEMPLATE static u32 FASTCALL OP_STMIB2() +{ + const u32 &i = cpu->instruction; + u32 c, b; + u32 start; + u32 oldmode; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + c = 0; + start = cpu->R[REG_POS(i,16)]; + oldmode = armcpu_switchMode(cpu, SYS); + + //emu_halt(); + LOG("Untested opcode: OP_STMIB2\n"); + + for(b=0; b<16; ++b) + { + if(BIT_N(i, b)) + { + start += 4; + WRITE32(cpu->mem_if->data, start, cpu->R[b]); + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + } + } + + armcpu_switchMode(cpu, oldmode); + return c + 1; +} + +TEMPLATE static u32 FASTCALL OP_STMDA2() +{ + const u32 &i=cpu->instruction; + u32 c, b; + u32 start; + u32 oldmode; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + c = 0; + start = cpu->R[REG_POS(i,16)]; + oldmode = armcpu_switchMode(cpu, SYS); + + //emu_halt(); + LOG("Untested opcode: OP_STMDA2\n"); + + for(b=0; b<16; ++b) + { + if(BIT_N(i, 15-b)) + { + WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + start -= 4; + } + } + + armcpu_switchMode(cpu, oldmode); + return c + 1; +} + +TEMPLATE static u32 FASTCALL OP_STMDB2() +{ + const u32 &i = cpu->instruction; + u32 c, b; + u32 start; + u32 oldmode; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + c=0; + start = cpu->R[REG_POS(i,16)]; + oldmode = armcpu_switchMode(cpu, SYS); + + for(b=0; b<16; ++b) + { + if(BIT_N(i, 15-b)) + { + start -= 4; + WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + } + } + + armcpu_switchMode(cpu, oldmode); + return c + 1; +} + +TEMPLATE static u32 FASTCALL OP_STMIA2_W() +{ + u32 i, c, b; + u32 start; + u32 oldmode; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + i = cpu->instruction; + c=0; + start = cpu->R[REG_POS(i,16)]; + oldmode = armcpu_switchMode(cpu, SYS); + + //emu_halt(); + LOG("Untested opcode: OP_STMIA2_W\n"); + + for(b=0; b<16; ++b) + { + if(BIT_N(i, b)) + { + WRITE32(cpu->mem_if->data, start, cpu->R[b]); + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + start += 4; + } + } + + cpu->R[REG_POS(i,16)] = start; + + armcpu_switchMode(cpu, oldmode); + return c + 1; +} + +TEMPLATE static u32 FASTCALL OP_STMIB2_W() +{ + u32 i, c, b; + u32 start; + u32 oldmode; + + if(cpu->CPSR.bits.mode==USR) + return 2; + i = cpu->instruction; + c=0; + start = cpu->R[REG_POS(i,16)]; + oldmode = armcpu_switchMode(cpu, SYS); + + for(b=0; b<16; ++b) + { + if(BIT_N(i, b)) + { + start += 4; + WRITE32(cpu->mem_if->data, start, cpu->R[b]); + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + } + } + armcpu_switchMode(cpu, oldmode); + cpu->R[REG_POS(i,16)] = start; + + return c + 1; +} + +TEMPLATE static u32 FASTCALL OP_STMDA2_W() +{ + u32 i, c, b; + u32 start; + u32 oldmode; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + i = cpu->instruction; + c = 0; + start = cpu->R[REG_POS(i,16)]; + oldmode = armcpu_switchMode(cpu, SYS); + //emu_halt(); + LOG("Untested opcode: OP_STMDA2_W\n"); + + for(b=0; b<16; ++b) + { + if(BIT_N(i, 15-b)) + { + WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + start -= 4; + } + } + + cpu->R[REG_POS(i,16)] = start; + + armcpu_switchMode(cpu, oldmode); + return c + 1; +} + +TEMPLATE static u32 FASTCALL OP_STMDB2_W() +{ + u32 i, c, b; + u32 start; + u32 oldmode; + + if(cpu->CPSR.bits.mode==USR) + return 2; + + i = cpu->instruction; + c = 0; + + start = cpu->R[REG_POS(i,16)]; + oldmode = armcpu_switchMode(cpu, SYS); + + //emu_halt(); + LOG("Untested opcode: OP_STMDB2_W\n"); + + for(b=0; b<16; ++b) + { + if(BIT_N(i, 15-b)) + { + start -= 4; + WRITE32(cpu->mem_if->data, start, cpu->R[15-b]); + c += MMU.MMU_WAIT32[PROCNUM][(start>>24)&0xF]; + } + } + + cpu->R[REG_POS(i,16)] = start; + + armcpu_switchMode(cpu, oldmode); + return c + 1; +} + +/* + * + * The Enhanced DSP Extension LDRD and STRD instructions. + * + */ +TEMPLATE static u32 FASTCALL +OP_LDRD_STRD_POST_INDEX( ) { + const u32 &i = cpu->instruction; + u32 Rd_num = REG_POS( i, 12); + u32 addr = cpu->R[REG_POS(i,16)]; + u32 index; + + /* I bit - immediate or register */ + if ( BIT22(i)) + index = IMM_OFF; + else + index = cpu->R[REG_POS(i,0)]; + + /* U bit - add or subtract */ + if ( BIT23(i)) + cpu->R[REG_POS(i,16)] += index; + else + cpu->R[REG_POS(i,16)] -= index; + + if ( !(Rd_num & 0x1)) { + /* Store/Load */ + if ( BIT5(i)) { + WRITE32(cpu->mem_if->data, addr, cpu->R[Rd_num]); + WRITE32(cpu->mem_if->data, addr + 4, cpu->R[Rd_num + 1]); + } + else { + cpu->R[Rd_num] = READ32(cpu->mem_if->data, addr); + cpu->R[Rd_num + 1] = READ32(cpu->mem_if->data, addr + 4); + } + } + + return 3 + (MMU.MMU_WAIT32[PROCNUM][(addr>>24)&0xF] * 2); +} + +TEMPLATE static u32 FASTCALL +OP_LDRD_STRD_OFFSET_PRE_INDEX( ) { + const u32 &i = cpu->instruction; + u32 Rd_num = REG_POS( i, 12); + u32 addr = cpu->R[REG_POS(i,16)]; + u32 index; + + /* I bit - immediate or register */ + if ( BIT22(i)) + index = IMM_OFF; + else + index = cpu->R[REG_POS(i,0)]; + + /* U bit - add or subtract */ + if ( BIT23(i)) { + addr += index; + + /* W bit - writeback */ + if ( BIT21(i)) + cpu->R[REG_POS(i,16)] = addr; + } + else { + addr -= index; + + /* W bit - writeback */ + if ( BIT21(i)) + cpu->R[REG_POS(i,16)] = addr; + } + + if ( !(Rd_num & 0x1)) { + /* Store/Load */ + if ( BIT5(i)) { + WRITE32(cpu->mem_if->data, addr, cpu->R[Rd_num]); + WRITE32(cpu->mem_if->data, addr + 4, cpu->R[Rd_num + 1]); + } + else { + cpu->R[Rd_num] = READ32(cpu->mem_if->data, addr); + cpu->R[Rd_num + 1] = READ32(cpu->mem_if->data, addr + 4); + } + } + + return 3 + (MMU.MMU_WAIT32[PROCNUM][(addr>>24)&0xF] * 2); +} + + + +//---------------------STC---------------------------------- +/* the NDS has no coproc that responses to a STC, no feedback is given to the arm */ + +TEMPLATE static u32 FASTCALL OP_STC_P_IMM_OFF() +{ + TRAPUNDEF(); +} + +TEMPLATE static u32 FASTCALL OP_STC_M_IMM_OFF() +{ + TRAPUNDEF(); +} + +TEMPLATE static u32 FASTCALL OP_STC_P_PREIND() +{ + TRAPUNDEF(); +} + +TEMPLATE static u32 FASTCALL OP_STC_M_PREIND() +{ + TRAPUNDEF(); +} + +TEMPLATE static u32 FASTCALL OP_STC_P_POSTIND() +{ + TRAPUNDEF(); +} + +TEMPLATE static u32 FASTCALL OP_STC_M_POSTIND() +{ + TRAPUNDEF(); +} + +TEMPLATE static u32 FASTCALL OP_STC_OPTION() +{ + TRAPUNDEF(); +} + +//---------------------LDC---------------------------------- +/* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */ + +TEMPLATE static u32 FASTCALL OP_LDC_P_IMM_OFF() +{ + TRAPUNDEF(); +} + +TEMPLATE static u32 FASTCALL OP_LDC_M_IMM_OFF() +{ + TRAPUNDEF(); +} + +TEMPLATE static u32 FASTCALL OP_LDC_P_PREIND() +{ + TRAPUNDEF(); +} + +TEMPLATE static u32 FASTCALL OP_LDC_M_PREIND() +{ + TRAPUNDEF(); +} + +TEMPLATE static u32 FASTCALL OP_LDC_P_POSTIND() +{ + TRAPUNDEF(); +} + +TEMPLATE static u32 FASTCALL OP_LDC_M_POSTIND() +{ + TRAPUNDEF(); +} + +TEMPLATE static u32 FASTCALL OP_LDC_OPTION() +{ + TRAPUNDEF(); + return 2; +} + +//----------------MCR----------------------- + +TEMPLATE static u32 FASTCALL OP_MCR() +{ + const u32 &i = cpu->instruction; + u32 cpnum = REG_POS(i, 8); + + if(!cpu->coproc[cpnum]) + { + emu_halt(); + LOG("Stopped (OP_MCR)\n"); + return 2; + } + + armcp15_moveARM2CP((armcp15_t*)cpu->coproc[cpnum], cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7); + //cpu->coproc[cpnum]->moveARM2CP(cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7); + return 2; +} + +//----------------MRC----------------------- + +TEMPLATE static u32 FASTCALL OP_MRC() +{ + const u32 &i = cpu->instruction; + u32 cpnum = REG_POS(i, 8); + + if(!cpu->coproc[cpnum]) + { + emu_halt(); + LOG("Stopped (OP_MRC)\n"); + return 2; + } + + armcp15_moveCP2ARM((armcp15_t*)cpu->coproc[cpnum], &cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7); + //cpu->coproc[cpnum]->moveCP2ARM(&cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7); + return 4; +} + +//--------------SWI------------------------------- +TEMPLATE static u32 FASTCALL OP_SWI() +{ + if(cpu->swi_tab) { + u32 swinum = (cpu->instruction>>16)&0x1F; + return cpu->swi_tab[swinum]() + 3; + } else { + /* TODO (#1#): translocated SWI vectors */ + /* we use an irq thats not in the irq tab, as + it was replaced duie to a changed intVector */ + Status_Reg tmp = cpu->CPSR; + armcpu_switchMode(cpu, SVC); /* enter svc mode */ + cpu->R[14] = cpu->next_instruction; + cpu->SPSR = tmp; /* save old CPSR as new SPSR */ + cpu->CPSR.bits.T = 0; /* handle as ARM32 code */ + cpu->CPSR.bits.I = 1; + cpu->R[15] = cpu->intVector + 0x08; + cpu->next_instruction = cpu->R[15]; + return 4; + } +} + +//----------------BKPT------------------------- +TEMPLATE static u32 FASTCALL OP_BKPT() +{ + LOG("Stopped (OP_BKPT)\n"); + TRAPUNDEF(); +} + +//----------------CDP----------------------- + +TEMPLATE static u32 FASTCALL OP_CDP() +{ + LOG("Stopped (OP_CDP)\n"); + TRAPUNDEF(); +} + +#define TYPE_RETOUR u32 +#define PARAMETRES +#define CALLTYPE FASTCALL +#define NOM_TAB arm_instructions_set_0 +#define TABDECL(x) x<0> + +#include "instruction_tabdef.inc" + +#undef TYPE_RETOUR +#undef PARAMETRES +#undef CALLTYPE +#undef NOM_TAB +#undef TABDECL + +#define TYPE_RETOUR u32 +#define PARAMETRES +#define CALLTYPE FASTCALL +#define NOM_TAB arm_instructions_set_1 +#define TABDECL(x) x<1> + +#include "instruction_tabdef.inc" diff --git a/desmume/src/arm_instructions.h b/src/arm_instructions.h similarity index 100% rename from desmume/src/arm_instructions.h rename to src/arm_instructions.h diff --git a/desmume/src/armcpu.cpp b/src/armcpu.cpp similarity index 100% rename from desmume/src/armcpu.cpp rename to src/armcpu.cpp diff --git a/desmume/src/armcpu.h b/src/armcpu.h similarity index 100% rename from desmume/src/armcpu.h rename to src/armcpu.h diff --git a/desmume/src/bios.cpp b/src/bios.cpp similarity index 100% rename from desmume/src/bios.cpp rename to src/bios.cpp diff --git a/desmume/src/bios.h b/src/bios.h similarity index 100% rename from desmume/src/bios.h rename to src/bios.h diff --git a/desmume/src/bits.h b/src/bits.h similarity index 100% rename from desmume/src/bits.h rename to src/bits.h diff --git a/desmume/src/build.bat b/src/build.bat similarity index 100% rename from desmume/src/build.bat rename to src/build.bat diff --git a/desmume/src/cflash.cpp b/src/cflash.cpp similarity index 100% rename from desmume/src/cflash.cpp rename to src/cflash.cpp diff --git a/desmume/src/cflash.h b/src/cflash.h similarity index 100% rename from desmume/src/cflash.h rename to src/cflash.h diff --git a/desmume/src/cli/Makefile.am b/src/cli/Makefile.am similarity index 100% rename from desmume/src/cli/Makefile.am rename to src/cli/Makefile.am diff --git a/desmume/src/cli/doc/Makefile.am b/src/cli/doc/Makefile.am similarity index 100% rename from desmume/src/cli/doc/Makefile.am rename to src/cli/doc/Makefile.am diff --git a/desmume/src/cli/doc/desmume-cli.1 b/src/cli/doc/desmume-cli.1 similarity index 100% rename from desmume/src/cli/doc/desmume-cli.1 rename to src/cli/doc/desmume-cli.1 diff --git a/desmume/src/cli/main.cpp b/src/cli/main.cpp similarity index 100% rename from desmume/src/cli/main.cpp rename to src/cli/main.cpp diff --git a/desmume/src/cocoa/DeSmuME.cbp b/src/cocoa/DeSmuME.cbp similarity index 100% rename from desmume/src/cocoa/DeSmuME.cbp rename to src/cocoa/DeSmuME.cbp diff --git a/desmume/src/cocoa/DeSmuME.icns b/src/cocoa/DeSmuME.icns similarity index 100% rename from desmume/src/cocoa/DeSmuME.icns rename to src/cocoa/DeSmuME.icns diff --git a/desmume/src/cocoa/DeSmuME.xcodeproj/project.pbxproj b/src/cocoa/DeSmuME.xcodeproj/project.pbxproj similarity index 100% rename from desmume/src/cocoa/DeSmuME.xcodeproj/project.pbxproj rename to src/cocoa/DeSmuME.xcodeproj/project.pbxproj diff --git a/desmume/src/cocoa/English.nib/classes.nib b/src/cocoa/English.nib/classes.nib similarity index 100% rename from desmume/src/cocoa/English.nib/classes.nib rename to src/cocoa/English.nib/classes.nib diff --git a/desmume/src/cocoa/English.nib/info.nib b/src/cocoa/English.nib/info.nib similarity index 100% rename from desmume/src/cocoa/English.nib/info.nib rename to src/cocoa/English.nib/info.nib diff --git a/desmume/src/cocoa/English.nib/keyedobjects.nib b/src/cocoa/English.nib/keyedobjects.nib similarity index 100% rename from desmume/src/cocoa/English.nib/keyedobjects.nib rename to src/cocoa/English.nib/keyedobjects.nib diff --git a/desmume/src/cocoa/English.strings b/src/cocoa/English.strings similarity index 100% rename from desmume/src/cocoa/English.strings rename to src/cocoa/English.strings diff --git a/desmume/src/cocoa/French.nib/classes.nib b/src/cocoa/French.nib/classes.nib similarity index 100% rename from desmume/src/cocoa/French.nib/classes.nib rename to src/cocoa/French.nib/classes.nib diff --git a/desmume/src/cocoa/French.nib/info.nib b/src/cocoa/French.nib/info.nib similarity index 100% rename from desmume/src/cocoa/French.nib/info.nib rename to src/cocoa/French.nib/info.nib diff --git a/desmume/src/cocoa/French.nib/keyedobjects.nib b/src/cocoa/French.nib/keyedobjects.nib similarity index 100% rename from desmume/src/cocoa/French.nib/keyedobjects.nib rename to src/cocoa/French.nib/keyedobjects.nib diff --git a/desmume/src/cocoa/French.strings b/src/cocoa/French.strings similarity index 100% rename from desmume/src/cocoa/French.strings rename to src/cocoa/French.strings diff --git a/desmume/src/cocoa/Info.plist b/src/cocoa/Info.plist similarity index 96% rename from desmume/src/cocoa/Info.plist rename to src/cocoa/Info.plist index b7ed86ca9..e798b2160 100644 --- a/desmume/src/cocoa/Info.plist +++ b/src/cocoa/Info.plist @@ -32,11 +32,11 @@ CFBundlePackageType APPL CFBundleShortVersionString - 0.8 + 0.9 CFBundleSignature ???? CFBundleVersion - 0.8 + 0.9 NSMainNibFile MainMenu NSPrincipalClass diff --git a/desmume/src/cocoa/InfoPlist.strings b/src/cocoa/InfoPlist.strings similarity index 100% rename from desmume/src/cocoa/InfoPlist.strings rename to src/cocoa/InfoPlist.strings diff --git a/desmume/src/cocoa/Japanese.nib/classes.nib b/src/cocoa/Japanese.nib/classes.nib similarity index 100% rename from desmume/src/cocoa/Japanese.nib/classes.nib rename to src/cocoa/Japanese.nib/classes.nib diff --git a/desmume/src/cocoa/Japanese.nib/info.nib b/src/cocoa/Japanese.nib/info.nib similarity index 100% rename from desmume/src/cocoa/Japanese.nib/info.nib rename to src/cocoa/Japanese.nib/info.nib diff --git a/desmume/src/cocoa/Japanese.nib/keyedobjects.nib b/src/cocoa/Japanese.nib/keyedobjects.nib similarity index 100% rename from desmume/src/cocoa/Japanese.nib/keyedobjects.nib rename to src/cocoa/Japanese.nib/keyedobjects.nib diff --git a/desmume/src/cocoa/Japanese.strings b/src/cocoa/Japanese.strings similarity index 100% rename from desmume/src/cocoa/Japanese.strings rename to src/cocoa/Japanese.strings diff --git a/desmume/src/cocoa/Makefile.am b/src/cocoa/Makefile.am similarity index 100% rename from desmume/src/cocoa/Makefile.am rename to src/cocoa/Makefile.am diff --git a/desmume/src/cocoa/PkgInfo b/src/cocoa/PkgInfo similarity index 100% rename from desmume/src/cocoa/PkgInfo rename to src/cocoa/PkgInfo diff --git a/desmume/src/cocoa/Rakefile b/src/cocoa/Rakefile similarity index 100% rename from desmume/src/cocoa/Rakefile rename to src/cocoa/Rakefile diff --git a/desmume/src/cocoa/about.m b/src/cocoa/about.m similarity index 100% rename from desmume/src/cocoa/about.m rename to src/cocoa/about.m diff --git a/desmume/src/cocoa/cocoa_util.m b/src/cocoa/cocoa_util.m similarity index 100% rename from desmume/src/cocoa/cocoa_util.m rename to src/cocoa/cocoa_util.m diff --git a/desmume/src/cocoa/dialogs/rom_info.h b/src/cocoa/dialogs/rom_info.h similarity index 100% rename from desmume/src/cocoa/dialogs/rom_info.h rename to src/cocoa/dialogs/rom_info.h diff --git a/desmume/src/cocoa/dialogs/rom_info.m b/src/cocoa/dialogs/rom_info.m similarity index 100% rename from desmume/src/cocoa/dialogs/rom_info.m rename to src/cocoa/dialogs/rom_info.m diff --git a/desmume/src/cocoa/dialogs/speed_limit_selection_window.h b/src/cocoa/dialogs/speed_limit_selection_window.h similarity index 100% rename from desmume/src/cocoa/dialogs/speed_limit_selection_window.h rename to src/cocoa/dialogs/speed_limit_selection_window.h diff --git a/desmume/src/cocoa/dialogs/speed_limit_selection_window.m b/src/cocoa/dialogs/speed_limit_selection_window.m similarity index 100% rename from desmume/src/cocoa/dialogs/speed_limit_selection_window.m rename to src/cocoa/dialogs/speed_limit_selection_window.m diff --git a/desmume/src/cocoa/globals.h b/src/cocoa/globals.h similarity index 100% rename from desmume/src/cocoa/globals.h rename to src/cocoa/globals.h diff --git a/desmume/src/cocoa/input.h b/src/cocoa/input.h similarity index 100% rename from desmume/src/cocoa/input.h rename to src/cocoa/input.h diff --git a/desmume/src/cocoa/input.m b/src/cocoa/input.m similarity index 100% rename from desmume/src/cocoa/input.m rename to src/cocoa/input.m diff --git a/desmume/src/cocoa/main.m b/src/cocoa/main.m similarity index 100% rename from desmume/src/cocoa/main.m rename to src/cocoa/main.m diff --git a/desmume/src/cocoa/main_window.h b/src/cocoa/main_window.h similarity index 100% rename from desmume/src/cocoa/main_window.h rename to src/cocoa/main_window.h diff --git a/desmume/src/cocoa/main_window.m b/src/cocoa/main_window.m similarity index 100% rename from desmume/src/cocoa/main_window.m rename to src/cocoa/main_window.m diff --git a/desmume/src/cocoa/makeapp.sh b/src/cocoa/makeapp.sh similarity index 100% rename from desmume/src/cocoa/makeapp.sh rename to src/cocoa/makeapp.sh diff --git a/desmume/src/cocoa/nds_control.h b/src/cocoa/nds_control.h similarity index 100% rename from desmume/src/cocoa/nds_control.h rename to src/cocoa/nds_control.h diff --git a/desmume/src/cocoa/nds_control.mm b/src/cocoa/nds_control.mm similarity index 100% rename from desmume/src/cocoa/nds_control.mm rename to src/cocoa/nds_control.mm diff --git a/desmume/src/cocoa/preferences.h b/src/cocoa/preferences.h similarity index 100% rename from desmume/src/cocoa/preferences.h rename to src/cocoa/preferences.h diff --git a/desmume/src/cocoa/preferences.m b/src/cocoa/preferences.m similarity index 100% rename from desmume/src/cocoa/preferences.m rename to src/cocoa/preferences.m diff --git a/desmume/src/cocoa/screen_state.h b/src/cocoa/screen_state.h similarity index 100% rename from desmume/src/cocoa/screen_state.h rename to src/cocoa/screen_state.h diff --git a/desmume/src/cocoa/screen_state.m b/src/cocoa/screen_state.m similarity index 100% rename from desmume/src/cocoa/screen_state.m rename to src/cocoa/screen_state.m diff --git a/desmume/src/cocoa/screenshot.h b/src/cocoa/screenshot.h similarity index 100% rename from desmume/src/cocoa/screenshot.h rename to src/cocoa/screenshot.h diff --git a/desmume/src/cocoa/screenshot.m b/src/cocoa/screenshot.m similarity index 100% rename from desmume/src/cocoa/screenshot.m rename to src/cocoa/screenshot.m diff --git a/desmume/src/cocoa/sndOSX.h b/src/cocoa/sndOSX.h similarity index 100% rename from desmume/src/cocoa/sndOSX.h rename to src/cocoa/sndOSX.h diff --git a/desmume/src/cocoa/sndOSX.mm b/src/cocoa/sndOSX.mm similarity index 100% rename from desmume/src/cocoa/sndOSX.mm rename to src/cocoa/sndOSX.mm diff --git a/desmume/src/cocoa/video_output_view.h b/src/cocoa/video_output_view.h similarity index 100% rename from desmume/src/cocoa/video_output_view.h rename to src/cocoa/video_output_view.h diff --git a/desmume/src/cocoa/video_output_view.m b/src/cocoa/video_output_view.m similarity index 100% rename from desmume/src/cocoa/video_output_view.m rename to src/cocoa/video_output_view.m diff --git a/desmume/src/common.cpp b/src/common.cpp similarity index 100% rename from desmume/src/common.cpp rename to src/common.cpp diff --git a/desmume/src/common.h b/src/common.h similarity index 100% rename from desmume/src/common.h rename to src/common.h diff --git a/desmume/src/cp15.cpp b/src/cp15.cpp similarity index 100% rename from desmume/src/cp15.cpp rename to src/cp15.cpp diff --git a/desmume/src/cp15.h b/src/cp15.h similarity index 100% rename from desmume/src/cp15.h rename to src/cp15.h diff --git a/desmume/src/ctrlssdl.cpp b/src/ctrlssdl.cpp similarity index 100% rename from desmume/src/ctrlssdl.cpp rename to src/ctrlssdl.cpp diff --git a/desmume/src/ctrlssdl.h b/src/ctrlssdl.h similarity index 100% rename from desmume/src/ctrlssdl.h rename to src/ctrlssdl.h diff --git a/desmume/src/debug.cpp b/src/debug.cpp similarity index 100% rename from desmume/src/debug.cpp rename to src/debug.cpp diff --git a/desmume/src/debug.h b/src/debug.h similarity index 100% rename from desmume/src/debug.h rename to src/debug.h diff --git a/desmume/src/desmume.mk b/src/desmume.mk similarity index 100% rename from desmume/src/desmume.mk rename to src/desmume.mk diff --git a/desmume/src/dscard.h b/src/dscard.h similarity index 100% rename from desmume/src/dscard.h rename to src/dscard.h diff --git a/desmume/src/fat.h b/src/fat.h similarity index 100% rename from desmume/src/fat.h rename to src/fat.h diff --git a/desmume/src/fs-linux.cpp b/src/fs-linux.cpp similarity index 100% rename from desmume/src/fs-linux.cpp rename to src/fs-linux.cpp diff --git a/desmume/src/fs-windows.cpp b/src/fs-windows.cpp similarity index 100% rename from desmume/src/fs-windows.cpp rename to src/fs-windows.cpp diff --git a/desmume/src/fs.h b/src/fs.h similarity index 100% rename from desmume/src/fs.h rename to src/fs.h diff --git a/desmume/src/gdbstub.h b/src/gdbstub.h similarity index 100% rename from desmume/src/gdbstub.h rename to src/gdbstub.h diff --git a/desmume/src/gdbstub/Makefile.am b/src/gdbstub/Makefile.am similarity index 100% rename from desmume/src/gdbstub/Makefile.am rename to src/gdbstub/Makefile.am diff --git a/desmume/src/gdbstub/gdbstub.cpp b/src/gdbstub/gdbstub.cpp similarity index 100% rename from desmume/src/gdbstub/gdbstub.cpp rename to src/gdbstub/gdbstub.cpp diff --git a/desmume/src/gdbstub/gdbstub_internal.h b/src/gdbstub/gdbstub_internal.h similarity index 100% rename from desmume/src/gdbstub/gdbstub_internal.h rename to src/gdbstub/gdbstub_internal.h diff --git a/desmume/src/gfx3d.cpp b/src/gfx3d.cpp similarity index 100% rename from desmume/src/gfx3d.cpp rename to src/gfx3d.cpp diff --git a/desmume/src/gfx3d.h b/src/gfx3d.h similarity index 100% rename from desmume/src/gfx3d.h rename to src/gfx3d.h diff --git a/desmume/src/gtk-glade/Makefile.am b/src/gtk-glade/Makefile.am similarity index 100% rename from desmume/src/gtk-glade/Makefile.am rename to src/gtk-glade/Makefile.am diff --git a/desmume/src/gtk-glade/callbacks.cpp b/src/gtk-glade/callbacks.cpp similarity index 100% rename from desmume/src/gtk-glade/callbacks.cpp rename to src/gtk-glade/callbacks.cpp diff --git a/desmume/src/gtk-glade/callbacks.h b/src/gtk-glade/callbacks.h similarity index 100% rename from desmume/src/gtk-glade/callbacks.h rename to src/gtk-glade/callbacks.h diff --git a/desmume/src/gtk-glade/callbacks_IO.cpp b/src/gtk-glade/callbacks_IO.cpp similarity index 99% rename from desmume/src/gtk-glade/callbacks_IO.cpp rename to src/gtk-glade/callbacks_IO.cpp index cd473f5dd..aced287b1 100755 --- a/desmume/src/gtk-glade/callbacks_IO.cpp +++ b/src/gtk-glade/callbacks_IO.cpp @@ -21,7 +21,6 @@ */ #include "callbacks_IO.h" -#include "keyval_names.h" static u16 Cur_Keypad = 0; float ScreenCoeff_Size[2]={1.0,1.0}; diff --git a/desmume/src/gtk-glade/callbacks_IO.h b/src/gtk-glade/callbacks_IO.h similarity index 100% rename from desmume/src/gtk-glade/callbacks_IO.h rename to src/gtk-glade/callbacks_IO.h diff --git a/desmume/src/gtk-glade/dTools/callbacks_1_ioregs.cpp b/src/gtk-glade/dTools/callbacks_1_ioregs.cpp similarity index 98% rename from desmume/src/gtk-glade/dTools/callbacks_1_ioregs.cpp rename to src/gtk-glade/dTools/callbacks_1_ioregs.cpp index 48384cd5b..09ccbd72e 100755 --- a/desmume/src/gtk-glade/dTools/callbacks_1_ioregs.cpp +++ b/src/gtk-glade/dTools/callbacks_1_ioregs.cpp @@ -1,4 +1,4 @@ -/* callbacks_1_ioregs.cpp - this file is part of DeSmuME +/* callbacks_1_ioregs.c - this file is part of DeSmuME * * Copyright (C) 2007 Damien Nozay (damdoum) * Copyright (C) 2007 Pascal Giard (evilynux) diff --git a/desmume/src/gtk-glade/dTools/callbacks_2_memview.cpp b/src/gtk-glade/dTools/callbacks_2_memview.cpp similarity index 99% rename from desmume/src/gtk-glade/dTools/callbacks_2_memview.cpp rename to src/gtk-glade/dTools/callbacks_2_memview.cpp index 82a5b6ae6..fd44e6a22 100755 --- a/desmume/src/gtk-glade/dTools/callbacks_2_memview.cpp +++ b/src/gtk-glade/dTools/callbacks_2_memview.cpp @@ -1,4 +1,4 @@ -/* callbacks_2_memview.cpp - this file is part of DeSmuME +/* callbacks_2_memview.c - this file is part of DeSmuME * * Copyright (C) 2007 Damien Nozay (damdoum) * Author: damdoum at users.sourceforge.net diff --git a/desmume/src/gtk-glade/dTools/callbacks_3_palview.cpp b/src/gtk-glade/dTools/callbacks_3_palview.cpp similarity index 98% rename from desmume/src/gtk-glade/dTools/callbacks_3_palview.cpp rename to src/gtk-glade/dTools/callbacks_3_palview.cpp index 4905094c8..0b7097474 100755 --- a/desmume/src/gtk-glade/dTools/callbacks_3_palview.cpp +++ b/src/gtk-glade/dTools/callbacks_3_palview.cpp @@ -1,4 +1,4 @@ -/* callbacks_3_palview.cpp - this file is part of DeSmuME +/* callbacks_3_palview.c - this file is part of DeSmuME * * Copyright (C) 2007 Damien Nozay (damdoum) * Author: damdoum at users.sourceforge.net diff --git a/desmume/src/gtk-glade/dTools/callbacks_4_tileview.cpp b/src/gtk-glade/dTools/callbacks_4_tileview.cpp similarity index 99% rename from desmume/src/gtk-glade/dTools/callbacks_4_tileview.cpp rename to src/gtk-glade/dTools/callbacks_4_tileview.cpp index 0a4b4f719..7fee86b19 100755 --- a/desmume/src/gtk-glade/dTools/callbacks_4_tileview.cpp +++ b/src/gtk-glade/dTools/callbacks_4_tileview.cpp @@ -1,4 +1,4 @@ -/* callbacks_3_palview.cpp - this file is part of DeSmuME +/* callbacks_3_palview.c - this file is part of DeSmuME * * Copyright (C) 2007 Damien Nozay (damdoum) * Author: damdoum at users.sourceforge.net diff --git a/desmume/src/gtk-glade/dTools/callbacks_dtools.h b/src/gtk-glade/dTools/callbacks_dtools.h similarity index 100% rename from desmume/src/gtk-glade/dTools/callbacks_dtools.h rename to src/gtk-glade/dTools/callbacks_dtools.h diff --git a/desmume/src/gtk-glade/dTools/dTools_display.h b/src/gtk-glade/dTools/dTools_display.h similarity index 100% rename from desmume/src/gtk-glade/dTools/dTools_display.h rename to src/gtk-glade/dTools/dTools_display.h diff --git a/desmume/src/gtk-glade/desmume-glade.desktop b/src/gtk-glade/desmume-glade.desktop similarity index 100% rename from desmume/src/gtk-glade/desmume-glade.desktop rename to src/gtk-glade/desmume-glade.desktop diff --git a/desmume/src/gtk-glade/desmume.cpp b/src/gtk-glade/desmume.cpp similarity index 100% rename from desmume/src/gtk-glade/desmume.cpp rename to src/gtk-glade/desmume.cpp diff --git a/desmume/src/gtk-glade/desmume.h b/src/gtk-glade/desmume.h similarity index 100% rename from desmume/src/gtk-glade/desmume.h rename to src/gtk-glade/desmume.h diff --git a/desmume/src/gtk-glade/doc/Makefile.am b/src/gtk-glade/doc/Makefile.am similarity index 100% rename from desmume/src/gtk-glade/doc/Makefile.am rename to src/gtk-glade/doc/Makefile.am diff --git a/desmume/src/gtk-glade/doc/desmume-glade.1 b/src/gtk-glade/doc/desmume-glade.1 similarity index 100% rename from desmume/src/gtk-glade/doc/desmume-glade.1 rename to src/gtk-glade/doc/desmume-glade.1 diff --git a/desmume/src/gtk-glade/gdk_3Demu.cpp b/src/gtk-glade/gdk_3Demu.cpp similarity index 100% rename from desmume/src/gtk-glade/gdk_3Demu.cpp rename to src/gtk-glade/gdk_3Demu.cpp diff --git a/desmume/src/gtk-glade/gdk_3Demu.h b/src/gtk-glade/gdk_3Demu.h similarity index 100% rename from desmume/src/gtk-glade/gdk_3Demu.h rename to src/gtk-glade/gdk_3Demu.h diff --git a/desmume/src/gtk-glade/gdk_gl.cpp b/src/gtk-glade/gdk_gl.cpp similarity index 99% rename from desmume/src/gtk-glade/gdk_gl.cpp rename to src/gtk-glade/gdk_gl.cpp index 34803742e..2e3633146 100755 --- a/desmume/src/gtk-glade/gdk_gl.cpp +++ b/src/gtk-glade/gdk_gl.cpp @@ -1,4 +1,4 @@ -/* gdk_gl.cpp - this file is part of DeSmuME +/* gdk_gl.c - this file is part of DeSmuME * * Copyright (C) 2007 Damien Nozay (damdoum) * Author: damdoum at users.sourceforge.net diff --git a/desmume/src/gtk-glade/gdk_gl.h b/src/gtk-glade/gdk_gl.h similarity index 100% rename from desmume/src/gtk-glade/gdk_gl.h rename to src/gtk-glade/gdk_gl.h diff --git a/desmume/src/gtk-glade/glade-xml.cpp b/src/gtk-glade/glade-xml.cpp similarity index 100% rename from desmume/src/gtk-glade/glade-xml.cpp rename to src/gtk-glade/glade-xml.cpp diff --git a/desmume/src/gtk-glade/glade/DeSmuME.xpm b/src/gtk-glade/glade/DeSmuME.xpm similarity index 100% rename from desmume/src/gtk-glade/glade/DeSmuME.xpm rename to src/gtk-glade/glade/DeSmuME.xpm diff --git a/desmume/src/gtk-glade/glade/DeSmuMe.glade b/src/gtk-glade/glade/DeSmuMe.glade similarity index 100% rename from desmume/src/gtk-glade/glade/DeSmuMe.glade rename to src/gtk-glade/glade/DeSmuMe.glade diff --git a/desmume/src/gtk-glade/glade/DeSmuMe_Dtools.glade b/src/gtk-glade/glade/DeSmuMe_Dtools.glade similarity index 100% rename from desmume/src/gtk-glade/glade/DeSmuMe_Dtools.glade rename to src/gtk-glade/glade/DeSmuMe_Dtools.glade diff --git a/desmume/src/gtk-glade/globals.h b/src/gtk-glade/globals.h similarity index 93% rename from desmume/src/gtk-glade/globals.h rename to src/gtk-glade/globals.h index 658c409d0..873d2b3ce 100755 --- a/desmume/src/gtk-glade/globals.h +++ b/src/gtk-glade/globals.h @@ -29,12 +29,15 @@ #include #include #include +//#include #include // Localization #include #define _(String) gettext (String) +//#include +// more portable #include "SDL.h" // fix gtk-glade on windows with no configure @@ -103,7 +106,7 @@ glade_xml_signal_autoconnect_StringObject (GladeXML *self); extern int Frameskip; -/* main.cpp */ +/* main.c */ extern GtkWidget * pWindow; extern GtkWidget * pDrawingArea, * pDrawingArea2; extern GladeXML * xml, * xml_tools; @@ -114,13 +117,13 @@ void register_Tool(VoidFunPtr fun); void unregister_Tool(VoidFunPtr fun); gchar * get_ui_file (const char *filename); -/* callbacks.cpp */ +/* callbacks.c */ void enable_rom_features(); void resize (float Size1, float Size2); void rotate(float angle); extern gboolean ScreenInvert; -/* callbacks_IO.cpp */ +/* callbacks_IO.c */ extern float ScreenCoeff_Size[2]; extern float ScreenRotate; @@ -128,4 +131,8 @@ void black_screen (); void edit_controls(); void init_joy_labels(); +/* keyvalnames.c -see - */ +const char * KEYNAME(int k); +void init_keyvals(); + #endif /* __GLOBALS_H__ */ diff --git a/desmume/src/gtk-glade/keyval_names.h b/src/gtk-glade/keyval_names.cpp similarity index 68% rename from desmume/src/gtk-glade/keyval_names.h rename to src/gtk-glade/keyval_names.cpp index d6bebf976..d60118470 100755 --- a/desmume/src/gtk-glade/keyval_names.h +++ b/src/gtk-glade/keyval_names.cpp @@ -1,4 +1,4 @@ -/* keyval_names.h - this file is part of DeSmuME +/* keyval_names.c - this file is part of DeSmuME * * Copyright (C) 2007 Damien Nozay (damdoum) * Author: damdoum at users.sourceforge.net @@ -19,5 +19,19 @@ * Boston, MA 02111-1307, USA. */ -const char * KEYNAME(int k); -void init_keyvals(); +#include "keyval_names.h" +/* see */ + +const char * unknown="(unknown)"; +const char * KEYVAL_NAMES[0x10000]; + +const char * KEYNAME(int k) { + const char * s = unknown; + s = KEYVAL_NAMES[k & 0xFFFF]; + return s; +} + +void KEYVAL(int k, const char * name) { + if (KEYVAL_NAMES[k] == unknown) + KEYVAL_NAMES[k] = name; +} diff --git a/desmume/src/gtk-glade/keyval_names.cpp b/src/gtk-glade/keyval_names.h similarity index 99% rename from desmume/src/gtk-glade/keyval_names.cpp rename to src/gtk-glade/keyval_names.h index 65c94f12e..d2ec5b1dc 100755 --- a/desmume/src/gtk-glade/keyval_names.cpp +++ b/src/gtk-glade/keyval_names.h @@ -1,4 +1,4 @@ -/* keyval_names.cpp - this file is part of DeSmuME +/* keyval_names.c - this file is part of DeSmuME * * Copyright (C) 2007 Damien Nozay (damdoum) * Author: damdoum at users.sourceforge.net @@ -19,24 +19,13 @@ * Boston, MA 02111-1307, USA. */ -#include "keyval_names.h" -/* see */ +#include "globals.h" -const char * unknown="(unknown)"; -const char * KEYVAL_NAMES[0x10000]; +extern const char * unknown; +extern const char * KEYVAL_NAMES[0x10000]; +void KEYVAL(int k, const char * name); -const char * KEYNAME(int k) { - const char * s = unknown; - s = KEYVAL_NAMES[k & 0xFFFF]; - return s; -} - -static void KEYVAL(int k, const char * name) { - if (KEYVAL_NAMES[k] == unknown) - KEYVAL_NAMES[k] = name; -} - -void init_keyvals() { +void inline init_keyvals() { int i; for (i=0; i<0x10000; i++) KEYVAL_NAMES[i]=unknown; @@ -1382,3 +1371,4 @@ void init_keyvals() { /* 0xFFFFFF "VoidSymbol" */ } + diff --git a/desmume/src/gtk-glade/main.cpp b/src/gtk-glade/main.cpp similarity index 100% rename from desmume/src/gtk-glade/main.cpp rename to src/gtk-glade/main.cpp diff --git a/desmume/src/gtk/DeSmuME.xpm b/src/gtk/DeSmuME.xpm similarity index 100% rename from desmume/src/gtk/DeSmuME.xpm rename to src/gtk/DeSmuME.xpm diff --git a/desmume/src/gtk/Makefile.am b/src/gtk/Makefile.am similarity index 100% rename from desmume/src/gtk/Makefile.am rename to src/gtk/Makefile.am diff --git a/desmume/src/gtk/dTool.h b/src/gtk/dTool.h similarity index 100% rename from desmume/src/gtk/dTool.h rename to src/gtk/dTool.h diff --git a/desmume/src/gtk/dToolsList.cpp b/src/gtk/dToolsList.cpp similarity index 100% rename from desmume/src/gtk/dToolsList.cpp rename to src/gtk/dToolsList.cpp diff --git a/desmume/src/gtk/desmume.cpp b/src/gtk/desmume.cpp similarity index 100% rename from desmume/src/gtk/desmume.cpp rename to src/gtk/desmume.cpp diff --git a/desmume/src/gtk/desmume.desktop b/src/gtk/desmume.desktop similarity index 100% rename from desmume/src/gtk/desmume.desktop rename to src/gtk/desmume.desktop diff --git a/desmume/src/gtk/desmume.h b/src/gtk/desmume.h similarity index 100% rename from desmume/src/gtk/desmume.h rename to src/gtk/desmume.h diff --git a/desmume/src/gtk/doc/Makefile.am b/src/gtk/doc/Makefile.am similarity index 100% rename from desmume/src/gtk/doc/Makefile.am rename to src/gtk/doc/Makefile.am diff --git a/desmume/src/gtk/doc/desmume.1 b/src/gtk/doc/desmume.1 similarity index 100% rename from desmume/src/gtk/doc/desmume.1 rename to src/gtk/doc/desmume.1 diff --git a/desmume/src/gtk/gdk_3Demu.cpp b/src/gtk/gdk_3Demu.cpp similarity index 100% rename from desmume/src/gtk/gdk_3Demu.cpp rename to src/gtk/gdk_3Demu.cpp diff --git a/desmume/src/gtk/gdk_3Demu.h b/src/gtk/gdk_3Demu.h similarity index 100% rename from desmume/src/gtk/gdk_3Demu.h rename to src/gtk/gdk_3Demu.h diff --git a/desmume/src/gtk/main.cpp b/src/gtk/main.cpp similarity index 100% rename from desmume/src/gtk/main.cpp rename to src/gtk/main.cpp diff --git a/desmume/src/gtk/tools/ioregsView.cpp b/src/gtk/tools/ioregsView.cpp similarity index 100% rename from desmume/src/gtk/tools/ioregsView.cpp rename to src/gtk/tools/ioregsView.cpp diff --git a/desmume/src/gtk/tools/ioregsView.h b/src/gtk/tools/ioregsView.h similarity index 100% rename from desmume/src/gtk/tools/ioregsView.h rename to src/gtk/tools/ioregsView.h diff --git a/desmume/src/instruction_tabdef.inc b/src/instruction_tabdef.inc similarity index 100% rename from desmume/src/instruction_tabdef.inc rename to src/instruction_tabdef.inc diff --git a/desmume/src/matrix.cpp b/src/matrix.cpp similarity index 100% rename from desmume/src/matrix.cpp rename to src/matrix.cpp diff --git a/desmume/src/matrix.h b/src/matrix.h similarity index 100% rename from desmume/src/matrix.h rename to src/matrix.h diff --git a/desmume/src/matrix_sse2-x64.asm b/src/matrix_sse2-x64.asm similarity index 100% rename from desmume/src/matrix_sse2-x64.asm rename to src/matrix_sse2-x64.asm diff --git a/desmume/src/matrix_sse2-x86.asm b/src/matrix_sse2-x86.asm similarity index 100% rename from desmume/src/matrix_sse2-x86.asm rename to src/matrix_sse2-x86.asm diff --git a/desmume/src/mc.cpp b/src/mc.cpp similarity index 100% rename from desmume/src/mc.cpp rename to src/mc.cpp diff --git a/desmume/src/mc.h b/src/mc.h similarity index 100% rename from desmume/src/mc.h rename to src/mc.h diff --git a/desmume/src/mem.h b/src/mem.h similarity index 100% rename from desmume/src/mem.h rename to src/mem.h diff --git a/desmume/src/memorystream.h b/src/memorystream.h similarity index 100% rename from desmume/src/memorystream.h rename to src/memorystream.h diff --git a/desmume/src/movie.cpp b/src/movie.cpp similarity index 100% rename from desmume/src/movie.cpp rename to src/movie.cpp diff --git a/desmume/src/movie.h b/src/movie.h similarity index 100% rename from desmume/src/movie.h rename to src/movie.h diff --git a/desmume/src/readwrite.cpp b/src/readwrite.cpp similarity index 100% rename from desmume/src/readwrite.cpp rename to src/readwrite.cpp diff --git a/desmume/src/readwrite.h b/src/readwrite.h similarity index 100% rename from desmume/src/readwrite.h rename to src/readwrite.h diff --git a/desmume/src/registers.h b/src/registers.h similarity index 100% rename from desmume/src/registers.h rename to src/registers.h diff --git a/desmume/src/render3D.cpp b/src/render3D.cpp similarity index 95% rename from desmume/src/render3D.cpp rename to src/render3D.cpp index aa77ef16c..40a0df55b 100644 --- a/desmume/src/render3D.cpp +++ b/src/render3D.cpp @@ -25,7 +25,7 @@ int cur3DCore = GPU3D_NULL; static void NDS_nullFunc1 (void){} static char NDS_nullFunc2 (void){ return 1; } static void NDS_nullFunc3 (int,unsigned short*) {} -static void NDS_nullFunc4 (int,int,int,unsigned short*,unsigned char*) {} +static void NDS_nullFunc4 (int,int,int,unsigned short*) {} GPU3DInterface gpu3DNull = { "None", diff --git a/desmume/src/render3D.h b/src/render3D.h similarity index 96% rename from desmume/src/render3D.h rename to src/render3D.h index ef5693011..8c3b19f0b 100644 --- a/desmume/src/render3D.h +++ b/src/render3D.h @@ -45,7 +45,7 @@ typedef struct Render3DInterface void (CALL_CONVENTION* NDS_3D_VramReconfigureSignal) (); //Retrieves a line of color buffer data - void (CALL_CONVENTION* NDS_3D_GetLine) (int line, int start, int end_inclusive, unsigned short* dst, unsigned char* dstAlpha); + void (CALL_CONVENTION* NDS_3D_GetLine) (int line, int start, int end_inclusive, unsigned short* dst); //Retrieves a line of color buffer data for capture void (CALL_CONVENTION* NDS_3D_GetLineCaptured) (int line, unsigned short* dst); diff --git a/desmume/src/rtc.cpp b/src/rtc.cpp similarity index 100% rename from desmume/src/rtc.cpp rename to src/rtc.cpp diff --git a/desmume/src/rtc.h b/src/rtc.h similarity index 100% rename from desmume/src/rtc.h rename to src/rtc.h diff --git a/desmume/src/saves.cpp b/src/saves.cpp similarity index 100% rename from desmume/src/saves.cpp rename to src/saves.cpp diff --git a/desmume/src/saves.h b/src/saves.h similarity index 100% rename from desmume/src/saves.h rename to src/saves.h diff --git a/desmume/src/shaders.h b/src/shaders.h similarity index 100% rename from desmume/src/shaders.h rename to src/shaders.h diff --git a/desmume/src/sndsdl.cpp b/src/sndsdl.cpp similarity index 100% rename from desmume/src/sndsdl.cpp rename to src/sndsdl.cpp diff --git a/desmume/src/sndsdl.h b/src/sndsdl.h similarity index 100% rename from desmume/src/sndsdl.h rename to src/sndsdl.h diff --git a/desmume/src/softrender.cpp b/src/softrender.cpp similarity index 100% rename from desmume/src/softrender.cpp rename to src/softrender.cpp diff --git a/desmume/src/softrender.h b/src/softrender.h similarity index 100% rename from desmume/src/softrender.h rename to src/softrender.h diff --git a/desmume/src/softrender_config.h b/src/softrender_config.h similarity index 100% rename from desmume/src/softrender_config.h rename to src/softrender_config.h diff --git a/desmume/src/softrender_desmumefont.h b/src/softrender_desmumefont.h similarity index 100% rename from desmume/src/softrender_desmumefont.h rename to src/softrender_desmumefont.h diff --git a/desmume/src/softrender_v3sysfont.h b/src/softrender_v3sysfont.h similarity index 100% rename from desmume/src/softrender_v3sysfont.h rename to src/softrender_v3sysfont.h diff --git a/desmume/src/thumb_instructions.cpp b/src/thumb_instructions.cpp similarity index 95% rename from desmume/src/thumb_instructions.cpp rename to src/thumb_instructions.cpp index e6efdc87b..9b365b14e 100644 --- a/desmume/src/thumb_instructions.cpp +++ b/src/thumb_instructions.cpp @@ -334,8 +334,8 @@ TEMPLATE static u32 FASTCALL OP_ADC_REG() cpu->CPSR.bits.N = BIT31(res); cpu->CPSR.bits.Z = res == 0; - cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(a, b, res); - cpu->CPSR.bits.V = SIGNED_UNDERFLOW(a, b, res); + cpu->CPSR.bits.C = UNSIGNED_OVERFLOW(b, (u32) cpu->CPSR.bits.C, tmp) | UNSIGNED_OVERFLOW(tmp, a, res); + cpu->CPSR.bits.V = SIGNED_OVERFLOW(b, (u32) cpu->CPSR.bits.C, tmp) | SIGNED_OVERFLOW(tmp, a, res); return 3; } diff --git a/desmume/src/thumb_instructions.h b/src/thumb_instructions.h similarity index 100% rename from desmume/src/thumb_instructions.h rename to src/thumb_instructions.h diff --git a/desmume/src/thumb_tabdef.inc b/src/thumb_tabdef.inc similarity index 100% rename from desmume/src/thumb_tabdef.inc rename to src/thumb_tabdef.inc diff --git a/desmume/src/types.h b/src/types.h similarity index 95% rename from desmume/src/types.h rename to src/types.h index c8042cf38..8221ab097 100644 --- a/desmume/src/types.h +++ b/src/types.h @@ -21,7 +21,7 @@ #define TYPES_HPP #define DESMUME_NAME "DeSmuME" -#define DESMUME_VERSION_STRING "0.9-interim" +#define DESMUME_VERSION_STRING "0.9" #define DESMUME_VERSION_NUMERIC 90000 #define DESMUME_NAME_AND_VERSION DESMUME_NAME " " DESMUME_VERSION_STRING " " VERSION diff --git a/desmume/src/utils/ConvertUTF.c b/src/utils/ConvertUTF.c similarity index 100% rename from desmume/src/utils/ConvertUTF.c rename to src/utils/ConvertUTF.c diff --git a/desmume/src/utils/ConvertUTF.h b/src/utils/ConvertUTF.h similarity index 100% rename from desmume/src/utils/ConvertUTF.h rename to src/utils/ConvertUTF.h diff --git a/desmume/src/utils/decrypt/crc.cpp b/src/utils/decrypt/crc.cpp similarity index 100% rename from desmume/src/utils/decrypt/crc.cpp rename to src/utils/decrypt/crc.cpp diff --git a/desmume/src/utils/decrypt/crc.h b/src/utils/decrypt/crc.h similarity index 100% rename from desmume/src/utils/decrypt/crc.h rename to src/utils/decrypt/crc.h diff --git a/desmume/src/utils/decrypt/decrypt.cpp b/src/utils/decrypt/decrypt.cpp similarity index 100% rename from desmume/src/utils/decrypt/decrypt.cpp rename to src/utils/decrypt/decrypt.cpp diff --git a/desmume/src/utils/decrypt/decrypt.h b/src/utils/decrypt/decrypt.h similarity index 100% rename from desmume/src/utils/decrypt/decrypt.h rename to src/utils/decrypt/decrypt.h diff --git a/desmume/src/utils/decrypt/header.cpp b/src/utils/decrypt/header.cpp similarity index 100% rename from desmume/src/utils/decrypt/header.cpp rename to src/utils/decrypt/header.cpp diff --git a/desmume/src/utils/decrypt/header.h b/src/utils/decrypt/header.h similarity index 100% rename from desmume/src/utils/decrypt/header.h rename to src/utils/decrypt/header.h diff --git a/desmume/src/utils/guid.cpp b/src/utils/guid.cpp similarity index 100% rename from desmume/src/utils/guid.cpp rename to src/utils/guid.cpp diff --git a/desmume/src/utils/guid.h b/src/utils/guid.h similarity index 100% rename from desmume/src/utils/guid.h rename to src/utils/guid.h diff --git a/desmume/src/utils/md5.cpp b/src/utils/md5.cpp similarity index 100% rename from desmume/src/utils/md5.cpp rename to src/utils/md5.cpp diff --git a/desmume/src/utils/md5.h b/src/utils/md5.h similarity index 100% rename from desmume/src/utils/md5.h rename to src/utils/md5.h diff --git a/desmume/src/utils/valuearray.h b/src/utils/valuearray.h similarity index 100% rename from desmume/src/utils/valuearray.h rename to src/utils/valuearray.h diff --git a/desmume/src/utils/xstring.cpp b/src/utils/xstring.cpp similarity index 100% rename from desmume/src/utils/xstring.cpp rename to src/utils/xstring.cpp diff --git a/desmume/src/utils/xstring.h b/src/utils/xstring.h similarity index 100% rename from desmume/src/utils/xstring.h rename to src/utils/xstring.h diff --git a/desmume/src/wifi.cpp b/src/wifi.cpp similarity index 84% rename from desmume/src/wifi.cpp rename to src/wifi.cpp index e3090284e..bca3ee391 100644 --- a/desmume/src/wifi.cpp +++ b/src/wifi.cpp @@ -192,578 +192,476 @@ FW_WFCProfile FW_WFCProfile3 = {"", #ifdef EXPERIMENTAL_WIFI -/******************************************************************************* - - RF-Chip - - *******************************************************************************/ - -void WIFI_resetRF(rffilter_t *rf) { - /* reinitialize RF chip with the default values refer RF2958 docs */ - /* CFG1 */ - rf->CFG1.bits.IF_VGA_REG_EN = 1 ; - rf->CFG1.bits.IF_VCO_REG_EN = 1 ; - rf->CFG1.bits.RF_VCO_REG_EN = 1 ; - rf->CFG1.bits.HYBERNATE = 0 ; - rf->CFG1.bits.REF_SEL = 0 ; - /* IFPLL1 */ - rf->IFPLL1.bits.DAC = 3 ; - rf->IFPLL1.bits.P1 = 0 ; - rf->IFPLL1.bits.LD_EN1 = 0 ; - rf->IFPLL1.bits.AUTOCAL_EN1 = 0 ; - rf->IFPLL1.bits.PDP1 = 1 ; - rf->IFPLL1.bits.CPL1 = 0 ; - rf->IFPLL1.bits.LPF1 = 0 ; - rf->IFPLL1.bits.VTC_EN1 = 1 ; - rf->IFPLL1.bits.KV_EN1 = 0 ; - rf->IFPLL1.bits.PLL_EN1 = 0 ; - /* IFPLL2 */ - rf->IFPLL2.bits.IF_N = 0x22 ; - /* IFPLL3 */ - rf->IFPLL3.bits.KV_DEF1 = 8 ; - rf->IFPLL3.bits.CT_DEF1 = 7 ; - rf->IFPLL3.bits.DN1 = 0x1FF ; - /* RFPLL1 */ - rf->RFPLL1.bits.DAC = 3 ; - rf->RFPLL1.bits.P = 0 ; - rf->RFPLL1.bits.LD_EN = 0 ; - rf->RFPLL1.bits.AUTOCAL_EN = 0 ; - rf->RFPLL1.bits.PDP = 1 ; - rf->RFPLL1.bits.CPL = 0 ; - rf->RFPLL1.bits.LPF = 0 ; - rf->RFPLL1.bits.VTC_EN = 0 ; - rf->RFPLL1.bits.KV_EN = 0 ; - rf->RFPLL1.bits.PLL_EN = 0 ; - /* RFPLL2 */ - rf->RFPLL2.bits.NUM2 = 0 ; - rf->RFPLL2.bits.N2 = 0x5E ; - /* RFPLL3 */ - rf->RFPLL3.bits.NUM2 = 0 ; - /* RFPLL4 */ - rf->RFPLL4.bits.KV_DEF = 8 ; - rf->RFPLL4.bits.CT_DEF = 7 ; - rf->RFPLL4.bits.DN = 0x145 ; - /* CAL1 */ - rf->CAL1.bits.LD_WINDOW = 2 ; - rf->CAL1.bits.M_CT_VALUE = 8 ; - rf->CAL1.bits.TLOCK = 7 ; - rf->CAL1.bits.TVCO = 0x0F ; - /* TXRX1 */ - rf->TXRX1.bits.TXBYPASS = 0 ; - rf->TXRX1.bits.INTBIASEN = 0 ; - rf->TXRX1.bits.TXENMODE = 0 ; - rf->TXRX1.bits.TXDIFFMODE = 0 ; - rf->TXRX1.bits.TXLPFBW = 2 ; - rf->TXRX1.bits.RXLPFBW = 2 ; - rf->TXRX1.bits.TXVGC = 0 ; - rf->TXRX1.bits.PCONTROL = 0 ; - rf->TXRX1.bits.RXDCFBBYPS = 0 ; - /* PCNT1 */ - rf->PCNT1.bits.TX_DELAY = 0 ; - rf->PCNT1.bits.PC_OFFSET = 0 ; - rf->PCNT1.bits.P_DESIRED = 0 ; - rf->PCNT1.bits.MID_BIAS = 0 ; - /* PCNT2 */ - rf->PCNT2.bits.MIN_POWER = 0 ; - rf->PCNT2.bits.MID_POWER = 0 ; - rf->PCNT2.bits.MAX_POWER = 0 ; - /* VCOT1 */ - rf->VCOT1.bits.AUX1 = 0 ; - rf->VCOT1.bits.AUX = 0 ; -} ; - - -void WIFI_setRF_CNT(wifimac_t *wifi, u16 val) -{ - if (!wifi->rfIOStatus.bits.busy) - wifi->rfIOCnt.val = val ; -} - -void WIFI_setRF_DATA(wifimac_t *wifi, u16 val, u8 part) -{ - if (!wifi->rfIOStatus.bits.busy) - { - rfIOData_t *rfreg = (rfIOData_t *)&wifi->RF; - switch (wifi->rfIOCnt.bits.readOperation) - { - case 1: /* read from RF chip */ - /* low part of data is ignored on reads */ - /* on high part, the address is read, and the data at this is written back */ - if (part==1) - { - wifi->rfIOData.array16[part] = val ; - if (wifi->rfIOData.bits.address > (sizeof(wifi->RF) / 4)) return ; /* out of bound */ - /* get content of the addressed register */ - wifi->rfIOData.bits.content = rfreg[wifi->rfIOData.bits.address].bits.content ; - } - break ; - case 0: /* write to RF chip */ - wifi->rfIOData.array16[part] = val ; - if (wifi->rfIOData.bits.address > (sizeof(wifi->RF) / 4)) return ; /* out of bound */ - /* the actual transfer is done on high part write */ - if (part==1) - { - switch (wifi->rfIOData.bits.address) - { - case 5: /* write to upper part of the frequency filter */ - case 6: /* write to lower part of the frequency filter */ - { - u32 channelFreqN ; - rfreg[wifi->rfIOData.bits.address].bits.content = wifi->rfIOData.bits.content ; - /* get the complete rfpll.n */ - channelFreqN = (u32)wifi->RF.RFPLL3.bits.NUM2 + ((u32)wifi->RF.RFPLL2.bits.NUM2) << 18 + ((u32)wifi->RF.RFPLL2.bits.N2) << 24 ; - /* frequency setting is out of range */ - if (channelFreqN<0x00A2E8BA) return ; - /* substract base frequency (channel 1) */ - channelFreqN -= 0x00A2E8BA ; - /* every channel is now ~3813000 steps further */ - WIFI_Host_CloseChannel(wifi->udpSocket) ; - wifi->channel = (wifi->udpSocket,channelFreqN / 3813000)+1 ; - WIFI_Host_OpenChannel(wifi->channel) ; - } - return ; - case 13: - /* special purpose register: TEST1, on write, the RF chip resets */ - WIFI_resetRF(&wifi->RF) ; - return ; - } - /* set content of the addressed register */ - rfreg[wifi->rfIOData.bits.address].bits.content = wifi->rfIOData.bits.content ; - } - break ; - } - } -} - -u16 WIFI_getRF_DATA(wifimac_t *wifi, u8 part) -{ - if (!wifi->rfIOStatus.bits.busy) - { - return wifi->rfIOData.array16[part] ; - } else - { /* data is not (yet) available */ - return 0 ; - } - } - -u16 WIFI_getRF_STATUS(wifimac_t *wifi) -{ - return wifi->rfIOStatus.val ; -} - -/******************************************************************************* - - BB-Chip - - *******************************************************************************/ - -void WIFI_setBB_CNT(wifimac_t *wifi,u16 val) -{ - wifi->bbIOCnt.val = val ; -} - -u8 WIFI_getBB_DATA(wifimac_t *wifi) -{ - if ((wifi->bbIOCnt.bits.mode != 2) || !(wifi->bbIOCnt.bits.enable)) return 0 ; /* not for read or disabled */ - return wifi->BB.data[wifi->bbIOCnt.bits.address] ; -} - -void WIFI_setBB_DATA(wifimac_t *wifi, u8 val) -{ - if ((wifi->bbIOCnt.bits.mode != 1) || !(wifi->bbIOCnt.bits.enable)) return ; /* not for write or disabled */ - wifi->BB.data[wifi->bbIOCnt.bits.address] = val ; -} - -/******************************************************************************* - - wifimac IO: a lot of the wifi regs are action registers, that are mirrored - without action, so the default IO via MMU.c does not seem to - be very suitable - - all registers are 16 bit - - *******************************************************************************/ - -void WIFI_triggerIRQMask(wifimac_t *wifi, u16 mask) -{ - u16 oResult,nResult ; - oResult = wifi->IE.val & wifi->IF.val ; - wifi->IF.val = wifi->IF.val | (mask & ~0x0400) ; - nResult = wifi->IE.val & wifi->IF.val ; - if (!oResult && nResult) - { - NDS_makeARM7Int(24) ; /* cascade it via arm7 wifi irq */ - } -} - -void WIFI_triggerIRQ(wifimac_t *wifi, u8 irq) -{ - WIFI_triggerIRQMask(wifi,1<RF) ; - WIFI_Host_InitSystem() ; - wifi->udpSocket = WIFI_Host_OpenChannel(1) ; -} - -void WIFI_RXPutWord(wifimac_t *wifi,u16 val) -{ - /* abort when RX data queuing is not enabled */ - if (!(wifi->RXCnt & 0x8000)) return ; - /* abort when ringbuffer is full */ - if (wifi->RXReadCursor == wifi->RXHWWriteCursor) return ; - /* write the data to cursor position */ - wifi->circularBuffer[wifi->RXHWWriteCursor & 0xFFF] ; - /* move cursor by one */ - wifi->RXHWWriteCursor++ ; - /* wrap around */ - wifi->RXHWWriteCursor %= (wifi->RXRangeEnd - wifi->RXRangeBegin) >> 1 ; -} - -void WIFI_TXStart(wifimac_t *wifi,u8 slot) -{ - if (wifi->TXSlot[slot] & 0x8000) /* is slot enabled? */ - { - u16 txLen ; - /* the address has to be somewhere in the circular buffer, so drop the other bits */ - u16 address = (wifi->TXSlot[slot] & 0x7FFF) ; - /* is there even enough space for the header (6 hwords) in the tx buffer? */ - if (address > 0x1000-6) return ; - - /* 12 byte header TX Header: http://www.akkit.org/info/dswifi.htm#FmtTx */ - txLen = ntohs(wifi->circularBuffer[address+5]) ; - /* zero length */ - if (txLen==0) return ; - /* unsupported txRate */ - switch (ntohs(wifi->circularBuffer[address+4])) - { - case 10: /* 1 mbit */ - case 20: /* 2 mbit */ - break ; - default: /* other rates */ - return ; - } - - /* FIXME: calculate FCS */ - - WIFI_triggerIRQ(wifi,WIFI_IRQ_SENDSTART) ; - WIFI_Host_SendData(wifi->udpSocket,wifi->channel,(u8 *)&wifi->circularBuffer[address],txLen) ; - WIFI_triggerIRQ(wifi,WIFI_IRQ_SENDCOMPLETE) ; - } -} - -void WIFI_write16(wifimac_t *wifi,u32 address, u16 val) -{ - BOOL action = FALSE ; - if (!(MMU_read32(ARMCPU_ARM7,REG_PWRCNT) & 0x0002)) return ; /* access to wifi hardware was disabled */ - if ((address & 0xFF800000) != 0x04800000) return ; /* error: the address does not describe a wiifi register */ - - /* the first 0x1000 bytes are mirrored at +0x1000,+0x2000,+0x3000,+06000,+0x7000 */ - /* only the first mirror causes an special action */ - /* the gap at +0x4000 is filled with the circular bufferspace */ - /* the so created 0x8000 byte block is then mirrored till 0x04FFFFFF */ - /* see: http://www.akkit.org/info/dswifi.htm#Wifihwcap */ - if (((address & 0x00007000) >= 0x00004000) && ((address & 0x00007000) < 0x00006000)) - { - /* access to the circular buffer */ - address &= 0x1FFF ; - wifi->circularBuffer[address >> 1] = val ; - return ; - } - if (!(address & 0x00007000)) action = TRUE ; - /* mirrors => register address */ - address &= 0x00000FFF ; - switch (address) - { - case REG_WIFI_ID: - break ; - case REG_WIFI_MODE: - if (val & 0x4000) - { - /* does some resets */ - wifi->RXRangeBegin = 0x4000 ; - /* this bit does not save */ - val &= ~0x4000 ; - } - wifi->macMode = val ; - break ; - case REG_WIFI_WEP: - wifi->wepMode = val ; - break ; - case REG_WIFI_IE: - wifi->IE.val = val ; - break ; - case REG_WIFI_IF: - wifi->IF.val &= ~val ; /* clear flagging bits */ - break ; - case REG_WIFI_MAC0: - case REG_WIFI_MAC1: - case REG_WIFI_MAC2: - wifi->mac.words[(address - REG_WIFI_MAC0) >> 1] = val ; - break ; - case REG_WIFI_BSS0: - case REG_WIFI_BSS1: - case REG_WIFI_BSS2: - wifi->bss.words[(address - REG_WIFI_BSS0) >> 1] = val ; - break ; - case REG_WIFI_RETRYLIMIT: - wifi->retryLimit = val ; - break ; - case REG_WIFI_WEPCNT: - wifi->WEP_enable = (val & 0x8000) != 0 ; - break ; - case REG_WIFI_RXRANGEBEGIN: - wifi->RXRangeBegin = val ; - break ; - case REG_WIFI_RXRANGEEND: - wifi->RXRangeEnd = val ; - break ; - case REG_WIFI_WRITECSRLATCH: - if ((action) && (wifi->RXCnt & 1)) /* only when action register and CSR change enabled */ - { - wifi->RXHWWriteCursor = val ; - } - break ; - case REG_WIFI_CIRCBUFRADR: - wifi->CircBufReadAddress = (val & 0x1FFE); - break ; - case REG_WIFI_RXREADCSR: - wifi->RXReadCursor = val ; - break ; - case REG_WIFI_CIRCBUFWADR: - wifi->CircBufWriteAddress = val ; - break ; - case REG_WIFI_CIRCBUFWRITE: - /* set value into the circ buffer, and move cursor to the next hword on action */ - wifi->circularBuffer[(wifi->CircBufWriteAddress >> 1) & 0xFFF] = val ; - if (action) - { - /* move to next hword */ - wifi->CircBufWriteAddress+=2 ; - if (wifi->CircBufWriteAddress == wifi->CircBufWrEnd) - { - /* on end of buffer, add skip hwords to it */ - wifi->CircBufWrEnd += wifi->CircBufWrSkip * 2 ; - } - } - break ; - case REG_WIFI_CIRCBUFWR_SKIP: - wifi->CircBufWrSkip = val ; - break ; - case REG_WIFI_BEACONTRANS: - wifi->BEACONSlot = val & 0x7FFF ; - wifi->BEACON_enable = (val & 0x8000) != 0 ; - break ; - case REG_WIFI_TXLOC1: - case REG_WIFI_TXLOC2: - case REG_WIFI_TXLOC3: - wifi->TXSlot[(address - REG_WIFI_TXLOC1) >> 2] = val ; - break ; - case REG_WIFI_TXOPT: - if (val == 0xFFFF) - { - /* reset TX logic */ - /* CHECKME */ - wifi->TXSlot[0] = 0 ; wifi->TXSlot[1] = 0 ; wifi->TXSlot[2] = 0 ; - wifi->TXOpt = 0 ; - wifi->TXCnt = 0 ; - } else - { - wifi->TXOpt = val ; - } - break ; - case REG_WIFI_TXCNT: - wifi->TXCnt = val ; - if (val & 0x01) WIFI_TXStart(wifi,0) ; - if (val & 0x04) WIFI_TXStart(wifi,1) ; - if (val & 0x08) WIFI_TXStart(wifi,2) ; - break ; - case REG_WIFI_RFIOCNT: - WIFI_setRF_CNT(wifi,val) ; - break ; - case REG_WIFI_RFIOBSY: - /* CHECKME: read only? */ - break ; - case REG_WIFI_RFIODATA1: - WIFI_setRF_DATA(wifi,val,0) ; - break ; - case REG_WIFI_RFIODATA2: - WIFI_setRF_DATA(wifi,val,1) ; - break ; - case REG_WIFI_USCOUNTERCNT: - wifi->usecEnable = (val & 1)==1 ; - break ; - case REG_WIFI_USCOMPARECNT: - wifi->ucmpEnable = (val & 1)==1 ; - break ; - case REG_WIFI_BBSIOCNT: - WIFI_setBB_CNT(wifi,val) ; - break ; - case REG_WIFI_BBSIOWRITE: - WIFI_setBB_DATA(wifi,val) ; - break ; - case REG_WIFI_RXBUF_COUNT: - wifi->RXBufCount = val & 0x0FFF ; - break ; - case REG_WIFI_EXTRACOUNTCNT: - wifi->eCountEnable = (val & 0x0001) ; - break ; - case REG_WIFI_EXTRACOUNT: - wifi->eCount = val ; - break ; - case REG_WIFI_POWER_US: - wifi->crystalEnabled = !(val & 0x0001) ; - break ; - case REG_WIFI_IF_SET: - WIFI_triggerIRQMask(wifi,val) ; - break ; - case REG_WIFI_CIRCBUFRD_END: - wifi->CircBufRdEnd = (val & 0x1FFE) ; - break ; - case REG_WIFI_CIRCBUFRD_SKIP: - wifi->CircBufRdSkip = val & 0xFFF ; - break ; - case REG_WIFI_AID_LOW: - wifi->pid = val & 0x0F ; - break ; - case REG_WIFI_AID_HIGH: - wifi->aid = val & 0x07FF ; - break ; - default: - val = 0 ; /* not handled yet */ - break ; - } -} - -u16 WIFI_read16(wifimac_t *wifi,u32 address) -{ - BOOL action = FALSE ; - u16 temp ; - if (!(MMU_read32(ARMCPU_ARM7,REG_PWRCNT) & 0x0002)) return 0 ; /* access to wifi hardware was disabled */ - if ((address & 0xFF800000) != 0x04800000) return 0 ; /* error: the address does not describe a wiifi register */ - - /* the first 0x1000 bytes are mirrored at +0x1000,+0x2000,+0x3000,+06000,+0x7000 */ - /* only the first mirror causes an special action */ - /* the gap at +0x4000 is filled with the circular bufferspace */ - /* the so created 0x8000 byte block is then mirrored till 0x04FFFFFF */ - /* see: http://www.akkit.org/info/dswifi.htm#Wifihwcap */ - if (((address & 0x00007000) >= 0x00004000) && ((address & 0x00007000) < 0x00006000)) - { - /* access to the circular buffer */ - return wifi->circularBuffer[(address & 0x1FFF) >> 1] ; - } - if (!(address & 0x00007000)) action = TRUE ; - /* mirrors => register address */ - address &= 0x00000FFF ; - switch (address) - { - case REG_WIFI_ID: - return WIFI_CHIPID ; - case REG_WIFI_MODE: - return wifi->macMode ; - case REG_WIFI_WEP: - return wifi->wepMode ; - case REG_WIFI_IE: - return wifi->IE.val ; - case REG_WIFI_IF: - return wifi->IF.val ; - case REG_WIFI_RFIODATA1: - return WIFI_getRF_DATA(wifi,0) ; - case REG_WIFI_RFIODATA2: - return WIFI_getRF_DATA(wifi,1) ; - case REG_WIFI_RFIOBSY: - case REG_WIFI_BBSIOBUSY: - return 0 ; /* we are never busy :p */ - case REG_WIFI_BBSIOREAD: - return WIFI_getBB_DATA(wifi) ; - case REG_WIFI_RANDOM: - /* FIXME: random generator */ - return 0 ; - case REG_WIFI_MAC0: - case REG_WIFI_MAC1: - case REG_WIFI_MAC2: - return wifi->mac.words[(address - REG_WIFI_MAC0) >> 1] ; - case REG_WIFI_BSS0: - case REG_WIFI_BSS1: - case REG_WIFI_BSS2: - return wifi->bss.words[(address - REG_WIFI_BSS0) >> 1] ; - case REG_WIFI_RXRANGEBEGIN: - return wifi->RXRangeBegin ; - case REG_WIFI_CIRCBUFREAD: - temp = wifi->circularBuffer[((wifi->RXRangeBegin + wifi->CircBufReadAddress) >> 1) & 0x0FFF] ; - if (action) - { - wifi->CircBufReadAddress += 2 ; - wifi->CircBufReadAddress &= 0x1FFE ; - if (wifi->CircBufReadAddress + wifi->RXRangeBegin == wifi->RXRangeEnd) - { - wifi->CircBufReadAddress = 0 ; - } else - { - /* skip does not fire after a reset */ - if (wifi->CircBufReadAddress == wifi->CircBufRdEnd) - { - wifi->CircBufReadAddress += wifi->CircBufRdSkip * 2 ; - wifi->CircBufReadAddress &= 0x1FFE ; - if (wifi->CircBufReadAddress + wifi->RXRangeBegin == wifi->RXRangeEnd) wifi->CircBufReadAddress = 0 ; - } - } - if (wifi->RXBufCount > 0) - { - if (wifi->RXBufCount == 1) - { - WIFI_triggerIRQ(wifi,9) ; - } - wifi->RXBufCount-- ; - } - } - return temp; - case REG_WIFI_CIRCBUFRADR: - return wifi->CircBufReadAddress ; - case REG_WIFI_RXBUF_COUNT: - return wifi->RXBufCount ; - case REG_WIFI_EXTRACOUNTCNT: - return wifi->eCountEnable?1:0 ; - case REG_WIFI_EXTRACOUNT: - return wifi->eCount ; - case REG_WIFI_POWER_US: - return wifi->crystalEnabled?0:1 ; - case REG_WIFI_CIRCBUFRD_END: - return wifi->CircBufRdEnd ; - case REG_WIFI_CIRCBUFRD_SKIP: - return wifi->CircBufRdSkip ; - case REG_WIFI_AID_LOW: - return wifi->pid ; - case REG_WIFI_AID_HIGH: - return wifi->aid ; - default: - return 0 ; - } -} - - -void WIFI_usTrigger(wifimac_t *wifi) -{ - u8 dataBuffer[0x2000] ; - u16 rcvSize ; - if (wifi->crystalEnabled) - { - /* a usec (=3F03 cycles) has passed */ - if (wifi->usecEnable) - wifi->usec++ ; - if (wifi->eCountEnable) - { - if (wifi->eCount > 0) - { - wifi->eCount-- ; - } - } - } - if ((wifi->ucmpEnable) && (wifi->ucmp == wifi->usec)) - { - WIFI_triggerIRQ(wifi,WIFI_IRQ_TIMEBEACON) ; +/******************************************************************************* + + RF-Chip + + *******************************************************************************/ + +void WIFI_resetRF(rffilter_t *rf) { + /* reinitialize RF chip with the default values refer RF2958 docs */ + /* CFG1 */ + rf->CFG1.bits.IF_VGA_REG_EN = 1 ; + rf->CFG1.bits.IF_VCO_REG_EN = 1 ; + rf->CFG1.bits.RF_VCO_REG_EN = 1 ; + rf->CFG1.bits.HYBERNATE = 0 ; + rf->CFG1.bits.REF_SEL = 0 ; + /* IFPLL1 */ + rf->IFPLL1.bits.DAC = 3 ; + rf->IFPLL1.bits.P1 = 0 ; + rf->IFPLL1.bits.LD_EN1 = 0 ; + rf->IFPLL1.bits.AUTOCAL_EN1 = 0 ; + rf->IFPLL1.bits.PDP1 = 1 ; + rf->IFPLL1.bits.CPL1 = 0 ; + rf->IFPLL1.bits.LPF1 = 0 ; + rf->IFPLL1.bits.VTC_EN1 = 1 ; + rf->IFPLL1.bits.KV_EN1 = 0 ; + rf->IFPLL1.bits.PLL_EN1 = 0 ; + /* IFPLL2 */ + rf->IFPLL2.bits.IF_N = 0x22 ; + /* IFPLL3 */ + rf->IFPLL3.bits.KV_DEF1 = 8 ; + rf->IFPLL3.bits.CT_DEF1 = 7 ; + rf->IFPLL3.bits.DN1 = 0x1FF ; + /* RFPLL1 */ + rf->RFPLL1.bits.DAC = 3 ; + rf->RFPLL1.bits.P = 0 ; + rf->RFPLL1.bits.LD_EN = 0 ; + rf->RFPLL1.bits.AUTOCAL_EN = 0 ; + rf->RFPLL1.bits.PDP = 1 ; + rf->RFPLL1.bits.CPL = 0 ; + rf->RFPLL1.bits.LPF = 0 ; + rf->RFPLL1.bits.VTC_EN = 0 ; + rf->RFPLL1.bits.KV_EN = 0 ; + rf->RFPLL1.bits.PLL_EN = 0 ; + /* RFPLL2 */ + rf->RFPLL2.bits.NUM2 = 0 ; + rf->RFPLL2.bits.N2 = 0x5E ; + /* RFPLL3 */ + rf->RFPLL3.bits.NUM2 = 0 ; + /* RFPLL4 */ + rf->RFPLL4.bits.KV_DEF = 8 ; + rf->RFPLL4.bits.CT_DEF = 7 ; + rf->RFPLL4.bits.DN = 0x145 ; + /* CAL1 */ + rf->CAL1.bits.LD_WINDOW = 2 ; + rf->CAL1.bits.M_CT_VALUE = 8 ; + rf->CAL1.bits.TLOCK = 7 ; + rf->CAL1.bits.TVCO = 0x0F ; + /* TXRX1 */ + rf->TXRX1.bits.TXBYPASS = 0 ; + rf->TXRX1.bits.INTBIASEN = 0 ; + rf->TXRX1.bits.TXENMODE = 0 ; + rf->TXRX1.bits.TXDIFFMODE = 0 ; + rf->TXRX1.bits.TXLPFBW = 2 ; + rf->TXRX1.bits.RXLPFBW = 2 ; + rf->TXRX1.bits.TXVGC = 0 ; + rf->TXRX1.bits.PCONTROL = 0 ; + rf->TXRX1.bits.RXDCFBBYPS = 0 ; + /* PCNT1 */ + rf->PCNT1.bits.TX_DELAY = 0 ; + rf->PCNT1.bits.PC_OFFSET = 0 ; + rf->PCNT1.bits.P_DESIRED = 0 ; + rf->PCNT1.bits.MID_BIAS = 0 ; + /* PCNT2 */ + rf->PCNT2.bits.MIN_POWER = 0 ; + rf->PCNT2.bits.MID_POWER = 0 ; + rf->PCNT2.bits.MAX_POWER = 0 ; + /* VCOT1 */ + rf->VCOT1.bits.AUX1 = 0 ; + rf->VCOT1.bits.AUX = 0 ; +} ; + + +void WIFI_setRF_CNT(wifimac_t *wifi, u16 val) +{ + if (!wifi->rfIOStatus.bits.busy) + wifi->rfIOCnt.val = val ; +} + +void WIFI_setRF_DATA(wifimac_t *wifi, u16 val, u8 part) +{ + if (!wifi->rfIOStatus.bits.busy) + { + rfIOData_t *rfreg = (rfIOData_t *)&wifi->RF; + switch (wifi->rfIOCnt.bits.readOperation) + { + case 1: /* read from RF chip */ + /* low part of data is ignored on reads */ + /* on high part, the address is read, and the data at this is written back */ + if (part==1) + { + wifi->rfIOData.array16[part] = val ; + if (wifi->rfIOData.bits.address > (sizeof(wifi->RF) / 4)) return ; /* out of bound */ + /* get content of the addressed register */ + wifi->rfIOData.bits.content = rfreg[wifi->rfIOData.bits.address].bits.content ; + } + break ; + case 0: /* write to RF chip */ + wifi->rfIOData.array16[part] = val ; + if (wifi->rfIOData.bits.address > (sizeof(wifi->RF) / 4)) return ; /* out of bound */ + /* the actual transfer is done on high part write */ + if (part==1) + { + switch (wifi->rfIOData.bits.address) + { + case 5: /* write to upper part of the frequency filter */ + case 6: /* write to lower part of the frequency filter */ + { + u32 channelFreqN ; + rfreg[wifi->rfIOData.bits.address].bits.content = wifi->rfIOData.bits.content ; + /* get the complete rfpll.n */ + channelFreqN = (u32)wifi->RF.RFPLL3.bits.NUM2 + ((u32)wifi->RF.RFPLL2.bits.NUM2) << 18 + ((u32)wifi->RF.RFPLL2.bits.N2) << 24 ; + /* frequency setting is out of range */ + if (channelFreqN<0x00A2E8BA) return ; + /* substract base frequency (channel 1) */ + channelFreqN -= 0x00A2E8BA ; + /* every channel is now ~3813000 steps further */ + WIFI_Host_CloseChannel(wifi->udpSocket) ; + wifi->channel = (wifi->udpSocket,channelFreqN / 3813000)+1 ; + WIFI_Host_OpenChannel(wifi->channel) ; + } + return ; + case 13: + /* special purpose register: TEST1, on write, the RF chip resets */ + WIFI_resetRF(&wifi->RF) ; + return ; + } + /* set content of the addressed register */ + rfreg[wifi->rfIOData.bits.address].bits.content = wifi->rfIOData.bits.content ; + } + break ; + } + } +} + +u16 WIFI_getRF_DATA(wifimac_t *wifi, u8 part) +{ + if (!wifi->rfIOStatus.bits.busy) + { + return wifi->rfIOData.array16[part] ; + } else + { /* data is not (yet) available */ + return 0 ; + } + } + +u16 WIFI_getRF_STATUS(wifimac_t *wifi) +{ + return wifi->rfIOStatus.val ; +} + +/******************************************************************************* + + BB-Chip + + *******************************************************************************/ + +void WIFI_setBB_CNT(wifimac_t *wifi,u16 val) +{ + wifi->bbIOCnt.val = val ; +} + +u8 WIFI_getBB_DATA(wifimac_t *wifi) +{ + if ((wifi->bbIOCnt.bits.mode != 2) || !(wifi->bbIOCnt.bits.enable)) return 0 ; /* not for read or disabled */ + return wifi->BB.data[wifi->bbIOCnt.bits.address] ; +} + +void WIFI_setBB_DATA(wifimac_t *wifi, u8 val) +{ + if ((wifi->bbIOCnt.bits.mode != 1) || !(wifi->bbIOCnt.bits.enable)) return ; /* not for write or disabled */ + wifi->BB.data[wifi->bbIOCnt.bits.address] = val ; +} + +/******************************************************************************* + + wifimac IO: a lot of the wifi regs are action registers, that are mirrored + without action, so the default IO via MMU.c does not seem to + be very suitable + + all registers are 16 bit + + *******************************************************************************/ + +void WIFI_triggerIRQ(wifimac_t *wifi, u8 irq) +{ + /* trigger an irq */ + u16 irqBit = 1 << irq ; + if (wifi->IE.val & irqBit) + { + wifi->IF.val |= irqBit ; + NDS_makeARM7Int(24) ; /* cascade it via arm7 wifi irq */ + } +} + +void WIFI_Init(wifimac_t *wifi) +{ + WIFI_resetRF(&wifi->RF) ; + WIFI_Host_InitSystem() ; + wifi->udpSocket = WIFI_Host_OpenChannel(1) ; +} + +void WIFI_RXPutWord(wifimac_t *wifi,u16 val) +{ + /* abort when RX data queuing is not enabled */ + if (!(wifi->RXCnt & 0x8000)) return ; + /* abort when ringbuffer is full */ + if (wifi->RXReadCursor == wifi->RXHWWriteCursor) return ; + /* write the data to cursor position */ + wifi->circularBuffer[wifi->RXHWWriteCursor & 0xFFF] ; + /* move cursor by one */ + wifi->RXHWWriteCursor++ ; + /* wrap around */ + wifi->RXHWWriteCursor %= (wifi->RXRangeEnd - wifi->RXRangeBegin) >> 1 ; +} + +void WIFI_TXStart(wifimac_t *wifi,u8 slot) +{ + if (wifi->TXSlot[slot] & 0x8000) /* is slot enabled? */ + { + u16 txLen ; + /* the address has to be somewhere in the circular buffer, so drop the other bits */ + u16 address = (wifi->TXSlot[slot] & 0x7FFF) ; + /* is there even enough space for the header (6 hwords) in the tx buffer? */ + if (address > 0x1000-6) return ; + + /* 12 byte header TX Header: http://www.akkit.org/info/dswifi.htm#FmtTx */ + txLen = ntohs(wifi->circularBuffer[address+5]) ; + /* zero length */ + if (txLen==0) return ; + /* unsupported txRate */ + switch (ntohs(wifi->circularBuffer[address+4])) + { + case 10: /* 1 mbit */ + case 20: /* 2 mbit */ + break ; + default: /* other rates */ + return ; + } + + /* FIXME: calculate FCS */ + + WIFI_triggerIRQ(wifi,WIFI_IRQ_SENDSTART) ; + WIFI_Host_SendData(wifi->udpSocket,wifi->channel,(u8 *)&wifi->circularBuffer[address],txLen) ; + WIFI_triggerIRQ(wifi,WIFI_IRQ_SENDCOMPLETE) ; + } +} + +void WIFI_write16(wifimac_t *wifi,u32 address, u16 val) +{ + BOOL action = FALSE ; + if ((address & 0xFF800000) != 0x04800000) return ; /* error: the address does not describe a wiifi register */ + + /* the first 0x1000 bytes are mirrored at +0x1000,+0x2000,+0x3000,+06000,+0x7000 */ + /* only the first mirror causes an special action */ + /* the gap at +0x4000 is filled with the circular bufferspace */ + /* the so created 0x8000 byte block is then mirrored till 0x04FFFFFF */ + /* see: http://www.akkit.org/info/dswifi.htm#Wifihwcap */ + if (((address & 0x00007000) >= 0x00004000) && ((address & 0x00007000) < 0x00006000)) + { + /* access to the circular buffer */ + address &= 0x1FFFF ; + wifi->circularBuffer[address >> 1] = val ; + return ; + } + if (!(address & 0x00007000)) action = TRUE ; + /* mirrors => register address */ + address &= 0x00000FFF ; + switch (address) + { + case REG_WIFI_MODE: + wifi->macMode = val ; + break ; + case REG_WIFI_WEP: + wifi->wepMode = val ; + break ; + case REG_WIFI_IE: + wifi->IE.val = val ; + break ; + case REG_WIFI_IF: + wifi->IF.val &= ~val ; /* clear flagging bits */ + break ; + case REG_WIFI_MAC0: + case REG_WIFI_MAC1: + case REG_WIFI_MAC2: + wifi->mac.words[(address - REG_WIFI_MAC0) >> 1] = val ; + break ; + case REG_WIFI_BSS0: + case REG_WIFI_BSS1: + case REG_WIFI_BSS2: + wifi->bss.words[(address - REG_WIFI_BSS0) >> 1] = val ; + break ; + case REG_WIFI_AID: /* CHECKME: are those two really the same? */ + case REG_WIFI_AIDCPY: + wifi->aid = val ; + break ; + case REG_WIFI_RETRYLIMIT: + wifi->retryLimit = val ; + break ; + case REG_WIFI_WEPCNT: + wifi->WEP_enable = (val & 0x8000) != 0 ; + break ; + case REG_WIFI_RXRANGEBEGIN: + wifi->RXRangeBegin = val ; + break ; + case REG_WIFI_RXRANGEEND: + wifi->RXRangeEnd = val ; + break ; + case REG_WIFI_WRITECSRLATCH: + if ((action) && (wifi->RXCnt & 1)) /* only when action register and CSR change enabled */ + { + wifi->RXHWWriteCursor = val ; + } + break ; + case REG_WIFI_CIRCBUFRADR: + wifi->CircBufReadAddress = val ; + break ; + case REG_WIFI_RXREADCSR: + wifi->RXReadCursor = val ; + break ; + case REG_WIFI_CIRCBUFWADR: + wifi->CircBufWriteAddress = val ; + break ; + case REG_WIFI_CIRCBUFWRITE: + /* set value into the circ buffer, and move cursor to the next hword on action */ + wifi->circularBuffer[(wifi->CircBufWriteAddress >> 1) & 0xFFF] = val ; + if (action) + { + /* move to next hword */ + wifi->CircBufWriteAddress+=2 ; + if (wifi->CircBufWriteAddress == wifi->CircBufEnd) + { + /* on end of buffer, add skip hwords to it */ + wifi->CircBufEnd += wifi->CircBufSkip * 2 ; + } + } + break ; + case REG_WIFI_CIRCBUFWR_SKIP: + wifi->CircBufSkip = val ; + break ; + case REG_WIFI_BEACONTRANS: + wifi->BEACONSlot = val & 0x7FFF ; + wifi->BEACON_enable = (val & 0x8000) != 0 ; + break ; + case REG_WIFI_TXLOC1: + case REG_WIFI_TXLOC2: + case REG_WIFI_TXLOC3: + wifi->TXSlot[(address - REG_WIFI_TXLOC1) >> 2] = val ; + break ; + case REG_WIFI_TXOPT: + if (val == 0xFFFF) + { + /* reset TX logic */ + /* CHECKME */ + wifi->TXSlot[0] = 0 ; wifi->TXSlot[1] = 0 ; wifi->TXSlot[2] = 0 ; + wifi->TXOpt = 0 ; + wifi->TXCnt = 0 ; + } else + { + wifi->TXOpt = val ; + } + break ; + case REG_WIFI_TXCNT: + wifi->TXCnt = val ; + if (val & 0x01) WIFI_TXStart(wifi,0) ; + if (val & 0x04) WIFI_TXStart(wifi,1) ; + if (val & 0x08) WIFI_TXStart(wifi,2) ; + break ; + case REG_WIFI_RFIOCNT: + WIFI_setRF_CNT(wifi,val) ; + break ; + case REG_WIFI_RFIOBSY: + /* CHECKME: read only? */ + break ; + case REG_WIFI_RFIODATA1: + WIFI_setRF_DATA(wifi,val,0) ; + break ; + case REG_WIFI_RFIODATA2: + WIFI_setRF_DATA(wifi,val,1) ; + break ; + case REG_WIFI_USCOUNTERCNT: + wifi->usecEnable = (val & 1)==1 ; + break ; + case REG_WIFI_USCOMPARECNT: + wifi->ucmpEnable = (val & 1)==1 ; + break ; + case REG_WIFI_BBSIOCNT: + WIFI_setBB_CNT(wifi,val) ; + break ; + case REG_WIFI_BBSIOWRITE: + WIFI_setBB_DATA(wifi,val) ; + break ; + default: + val = 0 ; /* not handled yet */ + break ; + } +} + +u16 WIFI_read16(wifimac_t *wifi,u32 address) +{ + BOOL action = FALSE ; + if ((address & 0xFF800000) != 0x04800000) return 0 ; /* error: the address does not describe a wiifi register */ + + /* the first 0x1000 bytes are mirrored at +0x1000,+0x2000,+0x3000,+06000,+0x7000 */ + /* only the first mirror causes an special action */ + /* the gap at +0x4000 is filled with the circular bufferspace */ + /* the so created 0x8000 byte block is then mirrored till 0x04FFFFFF */ + /* see: http://www.akkit.org/info/dswifi.htm#Wifihwcap */ + if (((address & 0x00007000) >= 0x00004000) && ((address & 0x00007000) < 0x00006000)) + { + /* access to the circular buffer */ + return wifi->circularBuffer[(address & 0x1FFF) >> 1] ; + } + if (!(address & 0x00007000)) action = TRUE ; + /* mirrors => register address */ + address &= 0x00000FFF ; + switch (address) + { + case REG_WIFI_MODE: + return wifi->macMode ; + case REG_WIFI_WEP: + return wifi->wepMode ; + case REG_WIFI_IE: + return wifi->IE.val ; + case REG_WIFI_IF: + return wifi->IF.val ; + case REG_WIFI_RFIODATA1: + return WIFI_getRF_DATA(wifi,0) ; + case REG_WIFI_RFIODATA2: + return WIFI_getRF_DATA(wifi,1) ; + case REG_WIFI_RFIOBSY: + case REG_WIFI_BBSIOBUSY: + return 0 ; /* we are never busy :p */ + case REG_WIFI_BBSIOREAD: + return WIFI_getBB_DATA(wifi) ; + case REG_WIFI_RANDOM: + /* FIXME: random generator */ + return 0 ; + case REG_WIFI_MAC0: + case REG_WIFI_MAC1: + case REG_WIFI_MAC2: + return wifi->mac.words[(address - REG_WIFI_MAC0) >> 1] ; + case REG_WIFI_BSS0: + case REG_WIFI_BSS1: + case REG_WIFI_BSS2: + return wifi->bss.words[(address - REG_WIFI_BSS0) >> 1] ; + default: + return 0 ; + } +} + + +void WIFI_usTrigger(wifimac_t *wifi) +{ + u8 dataBuffer[0x2000] ; + u16 rcvSize ; + /* a usec (=3F03 cycles) has passed */ + if (wifi->usecEnable) + wifi->usec++ ; + if ((wifi->ucmpEnable) && (wifi->ucmp == wifi->usec)) + { + WIFI_triggerIRQ(wifi,WIFI_IRQ_TIMEBEACON) ; } /* receive check, given a 2 mbit connection, 2 bits per usec can be transfered. */ /* for a packet of 32 Bytes, at least 128 usec passed, we will use the 32 byte accuracy to reduce load */ diff --git a/desmume/src/wifi.h b/src/wifi.h similarity index 90% rename from desmume/src/wifi.h rename to src/wifi.h index b25305e8a..bab54f47f 100644 --- a/desmume/src/wifi.h +++ b/src/wifi.h @@ -26,7 +26,7 @@ /* standardize socket interface for linux and windows */ #ifdef WIN32 - #include + #include #define socket_t SOCKET #define sockaddr_t SOCKADDR #else @@ -40,409 +40,390 @@ #define BASEPORT 7000 /* channel 1: 7000 ... channel 13: 7012 */ /* FIXME: make it configureable */ -#define REG_WIFI_ID 0x000 -#define REG_WIFI_MODE 0x004 -#define REG_WIFI_WEP 0x006 -#define REG_WIFI_IF 0x010 -#define REG_WIFI_IE 0x012 -#define REG_WIFI_MAC0 0x018 -#define REG_WIFI_MAC1 0x01A -#define REG_WIFI_MAC2 0x01C -#define REG_WIFI_BSS0 0x020 -#define REG_WIFI_BSS1 0x022 -#define REG_WIFI_BSS2 0x024 -#define REG_WIFI_AID_LOW 0x028 -#define REG_WIFI_AID_HIGH 0x02A -#define REG_WIFI_RETRYLIMIT 0x02C -#define REG_WIFI_WEPCNT 0x032 -#define REG_WIFI_POWER_US 0x036 -#define REG_WIFI_POWERSTATE 0x03C -#define REG_WIFI_FORCEPS 0x040 -#define REG_WIFI_RANDOM 0x044 -#define REG_WIFI_RXRANGEBEGIN 0x050 -#define REG_WIFI_RXRANGEEND 0x052 -#define REG_WIFI_RXHWWRITECSR 0x054 -#define REG_WIFI_WRITECSRLATCH 0x056 -#define REG_WIFI_CIRCBUFRADR 0x058 -#define REG_WIFI_RXREADCSR 0x05A -#define REG_WIFI_RXBUF_COUNT 0x05C -#define REG_WIFI_CIRCBUFREAD 0x060 -#define REG_WIFI_CIRCBUFRD_END 0x062 -#define REG_WIFI_CIRCBUFRD_SKIP 0x064 -#define REG_WIFI_CIRCBUFWADR 0x068 -#define REG_WIFI_CIRCBUFWRITE 0x070 -#define REG_WIFI_CIRCBUFWR_END 0x074 -#define REG_WIFI_CIRCBUFWR_SKIP 0x076 -#define REG_WIFI_BEACONTRANS 0x080 -#define REG_WIFI_LISTENCOUNT 0x088 -#define REG_WIFI_BEACONPERIOD 0x08C -#define REG_WIFI_LISTENINT 0x08E -#define REG_WIFI_TXLOC1 0x0A0 -#define REG_WIFI_TXLOC2 0x0A4 -#define REG_WIFI_TXLOC3 0x0A8 -#define REG_WIFI_TXOPT 0x0AC -#define REG_WIFI_TXCNT 0x0AE -#define REG_WIFI_TXSTAT 0x0B8 -#define REG_WIFI_RXFILTER 0x0D0 -#define REG_WIFI_USCOUNTERCNT 0x0E8 -#define REG_WIFI_USCOMPARECNT 0x0EA -#define REG_WIFI_EXTRACOUNTCNT 0x0EE -#define REG_WIFI_USCOMPARE0 0x0F0 -#define REG_WIFI_USCOMPARE1 0x0F2 -#define REG_WIFI_USCOMPARE2 0x0F4 -#define REG_WIFI_USCOMPARE3 0x0F6 -#define REG_WIFI_USCOUNTER0 0x0F8 -#define REG_WIFI_USCOUNTER1 0x0FA -#define REG_WIFI_USCOUNTER2 0x0FC -#define REG_WIFI_USCOUNTER3 0x0FE -#define REG_WIFI_EXTRACOUNT 0x118 -#define REG_WIFI_BBSIOCNT 0x158 -#define REG_WIFI_BBSIOWRITE 0x15A -#define REG_WIFI_BBSIOREAD 0x15C -#define REG_WIFI_BBSIOBUSY 0x15E -#define REG_WIFI_RFIODATA2 0x17C -#define REG_WIFI_RFIODATA1 0x17E -#define REG_WIFI_RFIOBSY 0x180 -#define REG_WIFI_RFIOCNT 0x184 -#define REG_WIFI_IF_SET 0x21C - -/* WIFI misc constants */ -#define WIFI_CHIPID 0x1440 /* emulates "old" wifi chip, new is 0xC340 */ -#define REG_PWRCNT 0x04000304 - -/* Referenced as RF_ in dswifi: rffilter_t */ -/* based on the documentation for the RF2958 chip of RF Micro Devices */ -/* using the register names as in docs ( http://www.rfmd.com/pdfs/2958.pdf )*/ -/* even tho every register only has 18 bits we are using u32 */ -typedef struct rffilter_t -{ - union CFG1 - { - struct - { -/* 0*/ unsigned IF_VGA_REG_EN:1; -/* 1*/ unsigned IF_VCO_REG_EN:1; -/* 2*/ unsigned RF_VCO_REG_EN:1; -/* 3*/ unsigned HYBERNATE:1; -/* 4*/ unsigned :10; -/*14*/ unsigned REF_SEL:2; -/*16*/ unsigned :2 ; - } bits ; - u32 val ; - } CFG1 ; - union IFPLL1 - { - struct - { -/* 0*/ unsigned DAC:4; -/* 4*/ unsigned :5; -/* 9*/ unsigned P1:1; -/*10*/ unsigned LD_EN1:1; -/*11*/ unsigned AUTOCAL_EN1:1; -/*12*/ unsigned PDP1:1; -/*13*/ unsigned CPL1:1; -/*14*/ unsigned LPF1:1; -/*15*/ unsigned VTC_EN1:1; -/*16*/ unsigned KV_EN1:1; -/*17*/ unsigned PLL_EN1:1; - } bits ; - u32 val ; - } IFPLL1 ; - union IFPLL2 - { - struct - { -/* 0*/ unsigned IF_N:16; -/*16*/ unsigned :2; - } bits ; - u32 val ; - } IFPLL2 ; - union IFPLL3 - { - struct - { -/* 0*/ unsigned KV_DEF1:4; -/* 4*/ unsigned CT_DEF1:4; -/* 8*/ unsigned DN1:9; -/*17*/ unsigned :1; - } bits ; - u32 val ; - } IFPLL3 ; - union RFPLL1 - { - struct - { -/* 0*/ unsigned DAC:4; -/* 4*/ unsigned :5; -/* 9*/ unsigned P:1; -/*10*/ unsigned LD_EN:1; -/*11*/ unsigned AUTOCAL_EN:1; -/*12*/ unsigned PDP:1; -/*13*/ unsigned CPL:1; -/*14*/ unsigned LPF:1; -/*15*/ unsigned VTC_EN:1; -/*16*/ unsigned KV_EN:1; -/*17*/ unsigned PLL_EN:1; - } bits ; - u32 val ; - } RFPLL1 ; - union RFPLL2 - { - struct - { -/* 0*/ unsigned NUM2:6; -/* 6*/ unsigned N2:12; - } bits ; - u32 val ; - } RFPLL2 ; - union RFPLL3 - { - struct - { -/* 0*/ unsigned NUM2:18; - } bits ; - u32 val ; - } RFPLL3 ; - union RFPLL4 - { - struct - { -/* 0*/ unsigned KV_DEF:4; -/* 4*/ unsigned CT_DEF:4; -/* 8*/ unsigned DN:9; -/*17*/ unsigned :1; - } bits ; - u32 val ; - } RFPLL4 ; - union CAL1 - { - struct - { -/* 0*/ unsigned LD_WINDOW:3; -/* 3*/ unsigned M_CT_VALUE:5; -/* 8*/ unsigned TLOCK:5; -/*13*/ unsigned TVCO:5; - } bits ; - u32 val ; - } CAL1 ; - union TXRX1 - { - struct - { -/* 0*/ unsigned TXBYPASS:1; -/* 1*/ unsigned INTBIASEN:1; -/* 2*/ unsigned TXENMODE:1; -/* 3*/ unsigned TXDIFFMODE:1; -/* 4*/ unsigned TXLPFBW:3; -/* 7*/ unsigned RXLPFBW:3; -/*10*/ unsigned TXVGC:5; -/*15*/ unsigned PCONTROL:2; -/*17*/ unsigned RXDCFBBYPS:1; - } bits ; - u32 val ; - } TXRX1 ; - union PCNT1 - { - struct - { -/* 0*/ unsigned TX_DELAY:3; -/* 3*/ unsigned PC_OFFSET:6; -/* 9*/ unsigned P_DESIRED:6; -/*15*/ unsigned MID_BIAS:3; - } bits ; - u32 val ; - } PCNT1 ; - union PCNT2 - { - struct - { -/* 0*/ unsigned MIN_POWER:6; -/* 6*/ unsigned MID_POWER:6; -/*12*/ unsigned MAX_POWER:6; - } bits ; - } PCNT2 ; - union VCOT1 - { - struct - { -/* 0*/ unsigned :16; -/*16*/ unsigned AUX1:1; -/*17*/ unsigned AUX:1; - } bits ; - u32 val ; - } VCOT1 ; -} rffilter_t ; - -/* baseband chip refered as BB_, dataformat is unknown yet */ -/* it has at least 105 bytes of functional data */ -typedef struct -{ - u8 data[105] ; -} bb_t ; - -/* communication interface between RF,BB and the mac */ -typedef union -{ - struct { -/* 0*/ unsigned wordsize:5; -/* 5*/ unsigned :2; -/* 7*/ unsigned readOperation:1; -/* 8*/ unsigned :8; - } bits ; - u16 val ; -} rfIOCnt_t ; - -typedef union -{ - struct { -/* 0*/ unsigned busy:1; -/* 1*/ unsigned :15; - } bits ; - u16 val ; -} rfIOStat_t ; - -typedef union -{ - struct { -/* 0*/ unsigned content:18 ; -/*18*/ unsigned address:5; -/*23*/ unsigned :9; - } bits ; - struct { -/* 0*/ unsigned low:16 ; -/*16*/ unsigned high:16 ; - } val16 ; - u16 array16[2] ; - u32 val ; -} rfIOData_t ; - -typedef union -{ - struct { -/* 0*/ unsigned address:7; -/* 7*/ unsigned :5; -/*12*/ unsigned mode:2; -/*14*/ unsigned enable:1; -/*15*/ unsigned :1; - } bits ; - u16 val ; -} bbIOCnt_t ; - -#define WIFI_IRQ_RECVCOMPLETE 0x0001 -#define WIFI_IRQ_SENDCOMPLETE 0x0002 -#define WIFI_IRQ_COUNTUP 0x0004 -#define WIFI_IRQ_SENDERROR 0x0008 -#define WIFI_IRQ_STATCOUNTUP 0x0010 -#define WIFI_IRQ_STATACKUP 0x0020 -#define WIFI_IRQ_RECVSTART 0x0040 -#define WIFI_IRQ_SENDSTART 0x0080 -#define WIFI_IRQ_RFWAKEUP 0x0800 -#define WIFI_IRQ_TIMEBEACON 0x4000 -#define WIFI_IRQ_TIMEPREBEACON 0x8000 - -/* definition of the irq bitfields for wifi irq's (cascaded at arm7 irq #24) */ -typedef union -{ - struct - { -/* 0*/ unsigned recv_complete:1; -/* 1*/ unsigned send_complete:1; -/* 2*/ unsigned recv_countup:1; -/* 3*/ unsigned send_error:1; -/* 4*/ unsigned stat_countup:1; -/* 5*/ unsigned stat_ackup:1; -/* 6*/ unsigned recv_start:1; -/* 7*/ unsigned send_start:1; -/* 8*/ unsigned :3; -/*11*/ unsigned rf_wakeup:1; -/*12*/ unsigned :2; -/*14*/ unsigned time_beacon:1; -/*15*/ unsigned time_prebeacon:1; - } bits ; - u16 val ; -} wifiirq_t ; - -/* wifimac_t: the buildin mac (arm7 addressrange: 0x04800000-0x04FFFFFF )*/ -/* http://www.akkit.org/info/dswifi.htm#WifiIOMap */ -typedef struct -{ - /* wifi interrupt handling */ - wifiirq_t IE ; - wifiirq_t IF ; - - /* modes */ - u16 macMode ; - u16 wepMode ; - BOOL WEP_enable ; - - /* sending */ - u16 TXSlot[3] ; - u16 TXCnt ; - u16 TXOpt ; - u16 BEACONSlot ; - BOOL BEACON_enable ; - - /* receiving */ - u16 RXCnt ; - u16 RXCheckCounter ; - - /* addressing/handshaking */ - union - { - u16 words[3] ; - u8 bytes[6] ; - } mac ; - union - { - u16 words[3] ; - u8 bytes[6] ; - } bss ; - u16 aid ; - u16 pid ; /* player ID or aid_low */ - u16 retryLimit ; - - /* timing */ - BOOL crystalEnabled ; - u64 usec ; - BOOL usecEnable ; - u64 ucmp ; - BOOL ucmpEnable ; - u16 eCount ; - BOOL eCountEnable ; - - /* subchips */ - rffilter_t RF ; - bb_t BB ; - - /* subchip communications */ - rfIOCnt_t rfIOCnt ; - rfIOStat_t rfIOStatus ; - rfIOData_t rfIOData ; - bbIOCnt_t bbIOCnt ; - - /* buffers */ - u16 circularBuffer[0x1000] ; - u16 RXRangeBegin ; - u16 RXRangeEnd ; - u16 RXHWWriteCursor ; - u16 RXReadCursor ; - u16 RXUnits ; - u16 RXBufCount ; - u16 CircBufReadAddress ; - u16 CircBufWriteAddress ; - u16 CircBufRdEnd ; - u16 CircBufRdSkip ; - u16 CircBufWrEnd ; - u16 CircBufWrSkip ; - - /* others */ - u16 randomSeed ; - - /* desmume host communication */ - socket_t udpSocket ; - u8 channel ; - -} wifimac_t ; +#define REG_WIFI_MODE 0x004 +#define REG_WIFI_WEP 0x006 +#define REG_WIFI_IF 0x010 +#define REG_WIFI_IE 0x012 +#define REG_WIFI_MAC0 0x018 +#define REG_WIFI_MAC1 0x01A +#define REG_WIFI_MAC2 0x01C +#define REG_WIFI_BSS0 0x020 +#define REG_WIFI_BSS1 0x022 +#define REG_WIFI_BSS2 0x024 +#define REG_WIFI_AID 0x028 +#define REG_WIFI_AIDCPY 0x02A +#define REG_WIFI_RETRYLIMIT 0x02C +#define REG_WIFI_WEPCNT 0x032 +#define REG_WIFI_POWERSTATE 0x03C +#define REG_WIFI_FORCEPS 0x040 +#define REG_WIFI_RANDOM 0x044 +#define REG_WIFI_RXRANGEBEGIN 0x050 +#define REG_WIFI_RXRANGEEND 0x052 +#define REG_WIFI_RXHWWRITECSR 0x054 +#define REG_WIFI_WRITECSRLATCH 0x056 +#define REG_WIFI_CIRCBUFRADR 0x058 +#define REG_WIFI_RXREADCSR 0x05A +#define REG_WIFI_CIRCBUFREAD 0x060 +#define REG_WIFI_CIRCBUFWADR 0x068 +#define REG_WIFI_CIRCBUFWRITE 0x070 +#define REG_WIFI_CIRCBUFWR_END 0x074 +#define REG_WIFI_CIRCBUFWR_SKIP 0x076 +#define REG_WIFI_BEACONTRANS 0x080 +#define REG_WIFI_LISTENCOUNT 0x088 +#define REG_WIFI_BEACONPERIOD 0x08C +#define REG_WIFI_LISTENINT 0x08E +#define REG_WIFI_TXLOC1 0x0A0 +#define REG_WIFI_TXLOC2 0x0A4 +#define REG_WIFI_TXLOC3 0x0A8 +#define REG_WIFI_TXOPT 0x0AC +#define REG_WIFI_TXCNT 0x0AE +#define REG_WIFI_TXSTAT 0x0B8 +#define REG_WIFI_RXFILTER 0x0D0 +#define REG_WIFI_USCOUNTERCNT 0x0E8 +#define REG_WIFI_USCOMPARECNT 0x0EA +#define REG_WIFI_USCOMPARE0 0x0F0 +#define REG_WIFI_USCOMPARE1 0x0F2 +#define REG_WIFI_USCOMPARE2 0x0F4 +#define REG_WIFI_USCOMPARE3 0x0F6 +#define REG_WIFI_USCOUNTER0 0x0F8 +#define REG_WIFI_USCOUNTER1 0x0FA +#define REG_WIFI_USCOUNTER2 0x0FC +#define REG_WIFI_USCOUNTER3 0x0FE +#define REG_WIFI_BBSIOCNT 0x158 +#define REG_WIFI_BBSIOWRITE 0x15A +#define REG_WIFI_BBSIOREAD 0x15C +#define REG_WIFI_BBSIOBUSY 0x15E +#define REG_WIFI_RFIODATA2 0x17C +#define REG_WIFI_RFIODATA1 0x17E +#define REG_WIFI_RFIOBSY 0x180 +#define REG_WIFI_RFIOCNT 0x184 + +/* Referenced as RF_ in dswifi: rffilter_t */ +/* based on the documentation for the RF2958 chip of RF Micro Devices */ +/* using the register names as in docs ( http://www.rfmd.com/pdfs/2958.pdf )*/ +/* even tho every register only has 18 bits we are using u32 */ +typedef struct rffilter_t +{ + union CFG1 + { + struct + { +/* 0*/ unsigned IF_VGA_REG_EN:1; +/* 1*/ unsigned IF_VCO_REG_EN:1; +/* 2*/ unsigned RF_VCO_REG_EN:1; +/* 3*/ unsigned HYBERNATE:1; +/* 4*/ unsigned :10; +/*14*/ unsigned REF_SEL:2; +/*16*/ unsigned :2 ; + } bits ; + u32 val ; + } CFG1 ; + union IFPLL1 + { + struct + { +/* 0*/ unsigned DAC:4; +/* 4*/ unsigned :5; +/* 9*/ unsigned P1:1; +/*10*/ unsigned LD_EN1:1; +/*11*/ unsigned AUTOCAL_EN1:1; +/*12*/ unsigned PDP1:1; +/*13*/ unsigned CPL1:1; +/*14*/ unsigned LPF1:1; +/*15*/ unsigned VTC_EN1:1; +/*16*/ unsigned KV_EN1:1; +/*17*/ unsigned PLL_EN1:1; + } bits ; + u32 val ; + } IFPLL1 ; + union IFPLL2 + { + struct + { +/* 0*/ unsigned IF_N:16; +/*16*/ unsigned :2; + } bits ; + u32 val ; + } IFPLL2 ; + union IFPLL3 + { + struct + { +/* 0*/ unsigned KV_DEF1:4; +/* 4*/ unsigned CT_DEF1:4; +/* 8*/ unsigned DN1:9; +/*17*/ unsigned :1; + } bits ; + u32 val ; + } IFPLL3 ; + union RFPLL1 + { + struct + { +/* 0*/ unsigned DAC:4; +/* 4*/ unsigned :5; +/* 9*/ unsigned P:1; +/*10*/ unsigned LD_EN:1; +/*11*/ unsigned AUTOCAL_EN:1; +/*12*/ unsigned PDP:1; +/*13*/ unsigned CPL:1; +/*14*/ unsigned LPF:1; +/*15*/ unsigned VTC_EN:1; +/*16*/ unsigned KV_EN:1; +/*17*/ unsigned PLL_EN:1; + } bits ; + u32 val ; + } RFPLL1 ; + union RFPLL2 + { + struct + { +/* 0*/ unsigned NUM2:6; +/* 6*/ unsigned N2:12; + } bits ; + u32 val ; + } RFPLL2 ; + union RFPLL3 + { + struct + { +/* 0*/ unsigned NUM2:18; + } bits ; + u32 val ; + } RFPLL3 ; + union RFPLL4 + { + struct + { +/* 0*/ unsigned KV_DEF:4; +/* 4*/ unsigned CT_DEF:4; +/* 8*/ unsigned DN:9; +/*17*/ unsigned :1; + } bits ; + u32 val ; + } RFPLL4 ; + union CAL1 + { + struct + { +/* 0*/ unsigned LD_WINDOW:3; +/* 3*/ unsigned M_CT_VALUE:5; +/* 8*/ unsigned TLOCK:5; +/*13*/ unsigned TVCO:5; + } bits ; + u32 val ; + } CAL1 ; + union TXRX1 + { + struct + { +/* 0*/ unsigned TXBYPASS:1; +/* 1*/ unsigned INTBIASEN:1; +/* 2*/ unsigned TXENMODE:1; +/* 3*/ unsigned TXDIFFMODE:1; +/* 4*/ unsigned TXLPFBW:3; +/* 7*/ unsigned RXLPFBW:3; +/*10*/ unsigned TXVGC:5; +/*15*/ unsigned PCONTROL:2; +/*17*/ unsigned RXDCFBBYPS:1; + } bits ; + u32 val ; + } TXRX1 ; + union PCNT1 + { + struct + { +/* 0*/ unsigned TX_DELAY:3; +/* 3*/ unsigned PC_OFFSET:6; +/* 9*/ unsigned P_DESIRED:6; +/*15*/ unsigned MID_BIAS:3; + } bits ; + u32 val ; + } PCNT1 ; + union PCNT2 + { + struct + { +/* 0*/ unsigned MIN_POWER:6; +/* 6*/ unsigned MID_POWER:6; +/*12*/ unsigned MAX_POWER:6; + } bits ; + } PCNT2 ; + union VCOT1 + { + struct + { +/* 0*/ unsigned :16; +/*16*/ unsigned AUX1:1; +/*17*/ unsigned AUX:1; + } bits ; + u32 val ; + } VCOT1 ; +} rffilter_t ; + +/* baseband chip refered as BB_, dataformat is unknown yet */ +/* it has at least 105 bytes of functional data */ +typedef struct +{ + u8 data[105] ; +} bb_t ; + +/* communication interface between RF,BB and the mac */ +typedef union +{ + struct { +/* 0*/ unsigned wordsize:5; +/* 5*/ unsigned :2; +/* 7*/ unsigned readOperation:1; +/* 8*/ unsigned :8; + } bits ; + u16 val ; +} rfIOCnt_t ; + +typedef union +{ + struct { +/* 0*/ unsigned busy:1; +/* 1*/ unsigned :15; + } bits ; + u16 val ; +} rfIOStat_t ; + +typedef union +{ + struct { +/* 0*/ unsigned content:18 ; +/*18*/ unsigned address:5; +/*23*/ unsigned :9; + } bits ; + struct { +/* 0*/ unsigned low:16 ; +/*16*/ unsigned high:16 ; + } val16 ; + u16 array16[2] ; + u32 val ; +} rfIOData_t ; + +typedef union +{ + struct { +/* 0*/ unsigned address:7; +/* 7*/ unsigned :5; +/*12*/ unsigned mode:2; +/*14*/ unsigned enable:1; +/*15*/ unsigned :1; + } bits ; + u16 val ; +} bbIOCnt_t ; + +#define WIFI_IRQ_RECVCOMPLETE 0x0001 +#define WIFI_IRQ_SENDCOMPLETE 0x0002 +#define WIFI_IRQ_COUNTUP 0x0004 +#define WIFI_IRQ_SENDERROR 0x0008 +#define WIFI_IRQ_STATCOUNTUP 0x0010 +#define WIFI_IRQ_STATACKUP 0x0020 +#define WIFI_IRQ_RECVSTART 0x0040 +#define WIFI_IRQ_SENDSTART 0x0080 +#define WIFI_IRQ_RFWAKEUP 0x0800 +#define WIFI_IRQ_TIMEBEACON 0x4000 +#define WIFI_IRQ_TIMEPREBEACON 0x8000 + +/* definition of the irq bitfields for wifi irq's (cascaded at arm7 irq #24) */ +typedef union +{ + struct + { +/* 0*/ unsigned recv_complete:1; +/* 1*/ unsigned send_complete:1; +/* 2*/ unsigned recv_countup:1; +/* 3*/ unsigned send_error:1; +/* 4*/ unsigned stat_countup:1; +/* 5*/ unsigned stat_ackup:1; +/* 6*/ unsigned recv_start:1; +/* 7*/ unsigned send_start:1; +/* 8*/ unsigned :3; +/*11*/ unsigned rf_wakeup:1; +/*12*/ unsigned :2; +/*14*/ unsigned time_beacon:1; +/*15*/ unsigned time_prebeacon:1; + } bits ; + u16 val ; +} wifiirq_t ; + +/* wifimac_t: the buildin mac (arm7 addressrange: 0x04800000-0x04FFFFFF )*/ +/* http://www.akkit.org/info/dswifi.htm#WifiIOMap */ +typedef struct +{ + /* wifi interrupt handling */ + wifiirq_t IE ; + wifiirq_t IF ; + + /* modes */ + u16 macMode ; + u16 wepMode ; + BOOL WEP_enable ; + + /* sending */ + u16 TXSlot[3] ; + u16 TXCnt ; + u16 TXOpt ; + u16 BEACONSlot ; + BOOL BEACON_enable ; + + /* receiving */ + u16 RXCnt ; + u16 RXCheckCounter ; + + /* addressing/handshaking */ + union + { + u16 words[3] ; + u8 bytes[6] ; + } mac ; + union + { + u16 words[3] ; + u8 bytes[6] ; + } bss ; + u16 aid ; + u16 retryLimit ; + + /* timing */ + u64 usec ; + BOOL usecEnable ; + u64 ucmp ; + BOOL ucmpEnable ; + + /* subchips */ + rffilter_t RF ; + bb_t BB ; + + /* subchip communications */ + rfIOCnt_t rfIOCnt ; + rfIOStat_t rfIOStatus ; + rfIOData_t rfIOData ; + bbIOCnt_t bbIOCnt ; + + /* buffers */ + u16 circularBuffer[0x1000] ; + u16 RXRangeBegin ; + u16 RXRangeEnd ; + u16 RXHWWriteCursor ; + u16 RXReadCursor ; + u16 RXUnits ; + u16 CircBufReadAddress ; + u16 CircBufWriteAddress ; + u16 CircBufEnd ; + u16 CircBufSkip ; + + /* others */ + u16 randomSeed ; + + /* desmume host communication */ + socket_t udpSocket ; + u8 channel ; + +} wifimac_t ; extern wifimac_t wifiMac ; diff --git a/desmume/src/windows/AboutBox.cpp b/src/windows/AboutBox.cpp similarity index 100% rename from desmume/src/windows/AboutBox.cpp rename to src/windows/AboutBox.cpp diff --git a/desmume/src/windows/AboutBox.h b/src/windows/AboutBox.h similarity index 100% rename from desmume/src/windows/AboutBox.h rename to src/windows/AboutBox.h diff --git a/desmume/src/windows/CWindow.cpp b/src/windows/CWindow.cpp similarity index 100% rename from desmume/src/windows/CWindow.cpp rename to src/windows/CWindow.cpp diff --git a/desmume/src/windows/CWindow.h b/src/windows/CWindow.h similarity index 100% rename from desmume/src/windows/CWindow.h rename to src/windows/CWindow.h diff --git a/desmume/src/windows/DeSmuME.ico b/src/windows/DeSmuME.ico similarity index 100% rename from desmume/src/windows/DeSmuME.ico rename to src/windows/DeSmuME.ico diff --git a/desmume/src/windows/DeSmuME.layout b/src/windows/DeSmuME.layout similarity index 100% rename from desmume/src/windows/DeSmuME.layout rename to src/windows/DeSmuME.layout diff --git a/desmume/src/windows/DeSmuME_2005.vcproj b/src/windows/DeSmuME_2005.vcproj similarity index 100% rename from desmume/src/windows/DeSmuME_2005.vcproj rename to src/windows/DeSmuME_2005.vcproj diff --git a/desmume/src/windows/DeSmuME_2008.vcproj b/src/windows/DeSmuME_2008.vcproj similarity index 94% rename from desmume/src/windows/DeSmuME_2008.vcproj rename to src/windows/DeSmuME_2008.vcproj index d4eb073f5..328f52c65 100644 --- a/desmume/src/windows/DeSmuME_2008.vcproj +++ b/src/windows/DeSmuME_2008.vcproj @@ -231,7 +231,7 @@ EnableFiberSafeOptimizations="true" WholeProgramOptimization="true" AdditionalIncludeDirectories=".;..;.\zlib123;.\zziplib" - PreprocessorDefinitions="_CRT_SECURE_NO_DEPRECATE;VERSION=\"0.8.0b2\";WIN32;HAVE_LIBZ;HAVE_LIBZZIP;BETA_VERSION;SPU_INTERPOLATE;NOMINMAX" + PreprocessorDefinitions="_CRT_SECURE_NO_DEPRECATE;VERSION=\"0.9\";WIN32;HAVE_LIBZ;HAVE_LIBZZIP;BETA_VERSION;SPU_INTERPOLATE;NOMINMAX" StringPooling="true" ExceptionHandling="1" BufferSecurityCheck="false" @@ -498,7 +498,7 @@ EnableFiberSafeOptimizations="true" WholeProgramOptimization="true" AdditionalIncludeDirectories=".;..;.\zlib123;.\zziplib" - PreprocessorDefinitions="_CRT_SECURE_NO_DEPRECATE;VERSION=\"0.8.0b2\";WIN32;HAVE_LIBZ;HAVE_LIBZZIP;BETA_VERSION;SPU_INTERPOLATE;NOMINMAX" + PreprocessorDefinitions="_CRT_SECURE_NO_DEPRECATE;VERSION=\"0.9\";WIN32;HAVE_LIBZ;HAVE_LIBZZIP;BETA_VERSION;SPU_INTERPOLATE;NOMINMAX" StringPooling="true" ExceptionHandling="1" BufferSecurityCheck="false" diff --git a/desmume/src/windows/DeSmuME_Intel.icproj b/src/windows/DeSmuME_Intel.icproj similarity index 100% rename from desmume/src/windows/DeSmuME_Intel.icproj rename to src/windows/DeSmuME_Intel.icproj diff --git a/desmume/src/windows/DeSmuME_Intel.vcproj b/src/windows/DeSmuME_Intel.vcproj similarity index 100% rename from desmume/src/windows/DeSmuME_Intel.vcproj rename to src/windows/DeSmuME_Intel.vcproj diff --git a/desmume/src/windows/DeSmuME_x64.manifest b/src/windows/DeSmuME_x64.manifest similarity index 100% rename from desmume/src/windows/DeSmuME_x64.manifest rename to src/windows/DeSmuME_x64.manifest diff --git a/desmume/src/windows/DeSmuME_x86.manifest b/src/windows/DeSmuME_x86.manifest similarity index 100% rename from desmume/src/windows/DeSmuME_x86.manifest rename to src/windows/DeSmuME_x86.manifest diff --git a/desmume/src/windows/FirmConfig.cpp b/src/windows/FirmConfig.cpp similarity index 100% rename from desmume/src/windows/FirmConfig.cpp rename to src/windows/FirmConfig.cpp diff --git a/desmume/src/windows/FirmConfig.h b/src/windows/FirmConfig.h similarity index 100% rename from desmume/src/windows/FirmConfig.h rename to src/windows/FirmConfig.h diff --git a/desmume/src/windows/GL/glext.h b/src/windows/GL/glext.h similarity index 100% rename from desmume/src/windows/GL/glext.h rename to src/windows/GL/glext.h diff --git a/desmume/src/windows/IORegView.cpp b/src/windows/IORegView.cpp similarity index 100% rename from desmume/src/windows/IORegView.cpp rename to src/windows/IORegView.cpp diff --git a/desmume/src/windows/IORegView.h b/src/windows/IORegView.h similarity index 100% rename from desmume/src/windows/IORegView.h rename to src/windows/IORegView.h diff --git a/desmume/src/windows/Makefile.am b/src/windows/Makefile.am similarity index 100% rename from desmume/src/windows/Makefile.am rename to src/windows/Makefile.am diff --git a/desmume/src/windows/Makefile.win b/src/windows/Makefile.win similarity index 100% rename from desmume/src/windows/Makefile.win rename to src/windows/Makefile.win diff --git a/desmume/src/windows/afxres.h b/src/windows/afxres.h similarity index 100% rename from desmume/src/windows/afxres.h rename to src/windows/afxres.h diff --git a/desmume/src/windows/aviout.cpp b/src/windows/aviout.cpp similarity index 100% rename from desmume/src/windows/aviout.cpp rename to src/windows/aviout.cpp diff --git a/desmume/src/windows/colorctrl.cpp b/src/windows/colorctrl.cpp similarity index 100% rename from desmume/src/windows/colorctrl.cpp rename to src/windows/colorctrl.cpp diff --git a/desmume/src/windows/colorctrl.h b/src/windows/colorctrl.h similarity index 100% rename from desmume/src/windows/colorctrl.h rename to src/windows/colorctrl.h diff --git a/desmume/src/windows/console.cpp b/src/windows/console.cpp similarity index 100% rename from desmume/src/windows/console.cpp rename to src/windows/console.cpp diff --git a/desmume/src/windows/console.h b/src/windows/console.h similarity index 100% rename from desmume/src/windows/console.h rename to src/windows/console.h diff --git a/desmume/src/windows/directx/DxErr8.lib b/src/windows/directx/DxErr8.lib similarity index 100% rename from desmume/src/windows/directx/DxErr8.lib rename to src/windows/directx/DxErr8.lib diff --git a/desmume/src/windows/directx/ddraw.h b/src/windows/directx/ddraw.h similarity index 100% rename from desmume/src/windows/directx/ddraw.h rename to src/windows/directx/ddraw.h diff --git a/desmume/src/windows/directx/ddraw.lib b/src/windows/directx/ddraw.lib similarity index 100% rename from desmume/src/windows/directx/ddraw.lib rename to src/windows/directx/ddraw.lib diff --git a/desmume/src/windows/directx/dinput.h b/src/windows/directx/dinput.h similarity index 100% rename from desmume/src/windows/directx/dinput.h rename to src/windows/directx/dinput.h diff --git a/desmume/src/windows/directx/dinput8.lib b/src/windows/directx/dinput8.lib similarity index 100% rename from desmume/src/windows/directx/dinput8.lib rename to src/windows/directx/dinput8.lib diff --git a/desmume/src/windows/directx/dsound.h b/src/windows/directx/dsound.h similarity index 100% rename from desmume/src/windows/directx/dsound.h rename to src/windows/directx/dsound.h diff --git a/desmume/src/windows/directx/dsound.lib b/src/windows/directx/dsound.lib similarity index 100% rename from desmume/src/windows/directx/dsound.lib rename to src/windows/directx/dsound.lib diff --git a/desmume/src/windows/directx/dxerr8.h b/src/windows/directx/dxerr8.h similarity index 100% rename from desmume/src/windows/directx/dxerr8.h rename to src/windows/directx/dxerr8.h diff --git a/desmume/src/windows/directx/dxguid.lib b/src/windows/directx/dxguid.lib similarity index 100% rename from desmume/src/windows/directx/dxguid.lib rename to src/windows/directx/dxguid.lib diff --git a/desmume/src/windows/disView.cpp b/src/windows/disView.cpp similarity index 100% rename from desmume/src/windows/disView.cpp rename to src/windows/disView.cpp diff --git a/desmume/src/windows/disView.h b/src/windows/disView.h similarity index 100% rename from desmume/src/windows/disView.h rename to src/windows/disView.h diff --git a/desmume/src/windows/ginfo.cpp b/src/windows/ginfo.cpp similarity index 100% rename from desmume/src/windows/ginfo.cpp rename to src/windows/ginfo.cpp diff --git a/desmume/src/windows/ginfo.h b/src/windows/ginfo.h similarity index 100% rename from desmume/src/windows/ginfo.h rename to src/windows/ginfo.h diff --git a/desmume/src/windows/inputdx.cpp b/src/windows/inputdx.cpp similarity index 96% rename from desmume/src/windows/inputdx.cpp rename to src/windows/inputdx.cpp index 75a2cce1c..3166d9772 100644 --- a/desmume/src/windows/inputdx.cpp +++ b/src/windows/inputdx.cpp @@ -33,8 +33,8 @@ // ==================================================== emu input // ======================================================================= -#define IDD_INPUT_TIMER 1000000 - +#define IDD_INPUT_TIMER 1000000 + const char *DIkeysNames[0xEF] = { "N/A", @@ -172,9 +172,9 @@ const char *DIkeysNames[0xEF] = "Web Search", "Web Favorites", "Web Refresh", "Web Stop", "Web Forward", "Web Back", "My Computer", "Mail", "Media Select" // 0xEE -}; -const char *DIJoyNames[0x04] = { "JUp", "JDown", "JLeft", "JRight" }; - +}; +const char *DIJoyNames[0x04] = { "JUp", "JDown", "JLeft", "JRight" }; + #define KEY_A 0 #define KEY_B 1 #define KEY_SELECT 2 @@ -190,115 +190,115 @@ const char *DIJoyNames[0x04] = { "JUp", "JDown", "JLeft", "JRight" }; #define KEY_DEBUG 12 #define KEY_FOLD 13 #define KEY_POWER 14 - - -char *keyPadNames [MAXKEYPAD] = { "A", "B", "SELECT", "START", - "RIGHT", "LEFT", "UP", "DOWN", - "R", "L", "X", "Y", "DEBUG", "FOLD", "POWER" }; - + + +char *keyPadNames [MAXKEYPAD] = { "A", "B", "SELECT", "START", + "RIGHT", "LEFT", "UP", "DOWN", + "R", "L", "X", "Y", "DEBUG", "FOLD", "POWER" }; + u16 keyPadDefs[MAXKEYPAD] = {DIK_X, DIK_Z, DIK_RSHIFT, DIK_RETURN, DIK_RIGHT, DIK_LEFT, DIK_UP, DIK_DOWN, DIK_W, DIK_Q, - DIK_S, DIK_A, 0x00, DIK_BACKSPACE, DIK_PAUSE}; - -const int inputIDs[15]={ IDC_EDIT06, IDC_EDIT05, IDC_EDIT11, IDC_EDIT12, IDC_EDIT03, IDC_EDIT02, IDC_EDIT01, - IDC_EDIT04, IDC_EDIT10, IDC_EDIT09, IDC_EDIT08, IDC_EDIT07, IDC_EDIT14, IDC_EDIT13, - IDC_EDIT15}; - - + DIK_S, DIK_A, 0x00, DIK_BACKSPACE, DIK_PAUSE}; + +const int inputIDs[15]={ IDC_EDIT06, IDC_EDIT05, IDC_EDIT11, IDC_EDIT12, IDC_EDIT03, IDC_EDIT02, IDC_EDIT01, + IDC_EDIT04, IDC_EDIT10, IDC_EDIT09, IDC_EDIT08, IDC_EDIT07, IDC_EDIT14, IDC_EDIT13, + IDC_EDIT15}; + + u16 keyPad[15]; extern INPUTCLASS *input; - -// ==================================================== Config Input -INPUTCLASS *inputCfg = NULL; -HWND g_hWnd = NULL; -static int pressed; -static bool tab; -u16 tempKeyPad[MAXKEYPAD]; - -void InputConfigDIProc(BOOL paused, LPSTR buf) -{ - int t; - int i; - - if (pressed == 0) - { - for (t=0; t<512; t++) - { - if (t == DIK_ESCAPE) continue; - if (t == DIK_TAB) continue; - if (t == DIK_LMENU) continue; - if (t == DIK_F1) continue; - if (t == DIK_F2) continue; - if (t == DIK_F3) continue; - if (t == DIK_F4) continue; - if (t == DIK_F5) continue; - if (t == DIK_F6) continue; - if (t == DIK_F7) continue; - if (t == DIK_F8) continue; - if (t == DIK_F9) continue; - if (t == DIK_F10) continue; - if (t == DIK_F11) continue; - if (t == DIK_F12) continue; - if (t == DIK_NUMLOCK) continue; - - if (buf[t] & 0x80) - { - pressed = t; - break; - } - } - } - else - { - if ((pressed == DIK_LSHIFT) && ((buf[DIK_TAB] & 0x80))) tab = true; - if ((pressed == DIK_RSHIFT) && ((buf[DIK_TAB] & 0x80))) tab = true; - - if (!(buf[pressed] & 0x80)) - { - if (!tab) - { - if (pressed>255) - { - if (pressed>255 && pressed<260) - { - SetWindowText(GetFocus(), DIJoyNames[pressed-256]); - } - else - { - char buf[20]; - memset(buf, 0, sizeof(buf)); - wsprintf(buf, "JB%02i", pressed-259); - SetWindowText(GetFocus(), buf); - } - } - else - { - SetWindowText(GetFocus(), DIkeysNames[pressed]); - } - for (i=0; i255) + { + if (pressed>255 && pressed<260) + { + SetWindowText(GetFocus(), DIJoyNames[pressed-256]); + } + else + { + char buf[20]; + memset(buf, 0, sizeof(buf)); + wsprintf(buf, "JB%02i", pressed-259); + SetWindowText(GetFocus(), buf); + } + } + else + { + SetWindowText(GetFocus(), DIkeysNames[pressed]); + } + for (i=0; i255) { - if (tempKeyPad[i]>255 && tempKeyPad[i]<260) - { - SetWindowText(GetDlgItem(hDlg, inputIDs[i]), DIJoyNames[tempKeyPad[i]-256]); - } - else - { - char buf[20]; - memset(buf, 0, sizeof(buf)); - wsprintf(buf, "JB%02i", tempKeyPad[i]-259); - SetWindowText(GetDlgItem(hDlg, inputIDs[i]), buf); + if (tempKeyPad[i]>255 && tempKeyPad[i]<260) + { + SetWindowText(GetDlgItem(hDlg, inputIDs[i]), DIJoyNames[tempKeyPad[i]-256]); + } + else + { + char buf[20]; + memset(buf, 0, sizeof(buf)); + wsprintf(buf, "JB%02i", tempKeyPad[i]-259); + SetWindowText(GetDlgItem(hDlg, inputIDs[i]), buf); } } else @@ -338,10 +338,10 @@ BOOL CALLBACK InputConfigDlgProc( HWND hDlg, case IDOK: if (GetFocus() == GetDlgItem(hDlg, IDOK)) { - for (int t=0; t255) - { - if (!input->JoystickEnabled()) - { - keyPad[i] = keyPadDefs[i]; - } - } + keyPad[i] = GetPrivateProfileInt("NDS_Input",buf,keyPadDefs[i], IniName); + if (keyPad[i]>255) + { + if (!input->JoystickEnabled()) + { + keyPad[i] = keyPadDefs[i]; + } + } } } -void NDS_inputPost(BOOL paused, LPSTR buf) -{ - if (paused) return; - - bool R = (buf[keyPad[KEY_RIGHT]] & 0x80)!=0; - bool L = (buf[keyPad[KEY_LEFT]] & 0x80)!=0; - bool D = (buf[keyPad[KEY_DOWN]] & 0x80)!=0; - bool U = (buf[keyPad[KEY_UP]] & 0x80)!=0; - bool T = (buf[keyPad[KEY_START]] & 0x80)!=0; - bool S = (buf[keyPad[KEY_SELECT]] & 0x80)!=0; - bool B = (buf[keyPad[KEY_B]] & 0x80)!=0; - bool A = (buf[keyPad[KEY_A]] & 0x80)!=0; - bool Y = (buf[keyPad[KEY_Y]] & 0x80)!=0; - bool X = (buf[keyPad[KEY_X]] & 0x80)!=0; - bool W = (buf[keyPad[KEY_L]] & 0x80)!=0; - bool E = (buf[keyPad[KEY_R]] & 0x80)!=0; - bool G = (buf[keyPad[KEY_DEBUG]] & 0x80)!=0; - bool F = (buf[keyPad[KEY_FOLD]] & 0x80)!=0; - - NDS_setPad( R, L, D, U, T, S, B, A, Y, X, W, E, G, F); +void NDS_inputPost(BOOL paused, LPSTR buf) +{ + if (paused) return; + + bool R = (buf[keyPad[KEY_RIGHT]] & 0x80)!=0; + bool L = (buf[keyPad[KEY_LEFT]] & 0x80)!=0; + bool D = (buf[keyPad[KEY_DOWN]] & 0x80)!=0; + bool U = (buf[keyPad[KEY_UP]] & 0x80)!=0; + bool T = (buf[keyPad[KEY_START]] & 0x80)!=0; + bool S = (buf[keyPad[KEY_SELECT]] & 0x80)!=0; + bool B = (buf[keyPad[KEY_B]] & 0x80)!=0; + bool A = (buf[keyPad[KEY_A]] & 0x80)!=0; + bool Y = (buf[keyPad[KEY_Y]] & 0x80)!=0; + bool X = (buf[keyPad[KEY_X]] & 0x80)!=0; + bool W = (buf[keyPad[KEY_L]] & 0x80)!=0; + bool E = (buf[keyPad[KEY_R]] & 0x80)!=0; + bool G = (buf[keyPad[KEY_DEBUG]] & 0x80)!=0; + bool F = (buf[keyPad[KEY_FOLD]] & 0x80)!=0; + + NDS_setPad( R, L, D, U, T, S, B, A, Y, X, W, E, G, F); } // TODO @@ -491,8 +491,8 @@ BOOL INPUTCLASS::Init(HWND hParentWnd, INPUTPROC inputProc) if (!FAILED(IDirectInput8_CreateDevice(pDI,GUID_Joystick,&pJoystick,NULL))) { - if(!FAILED(IDirectInputDevice8_SetDataFormat(pJoystick,&c_dfDIJoystick2))) - { + if(!FAILED(IDirectInputDevice8_SetDataFormat(pJoystick,&c_dfDIJoystick2))) + { if(FAILED(IDirectInputDevice8_SetCooperativeLevel(pJoystick,hParentWnd,DISCL_FOREGROUND|DISCL_NONEXCLUSIVE))) { IDirectInputDevice8_Release(pJoystick); @@ -500,8 +500,8 @@ BOOL INPUTCLASS::Init(HWND hParentWnd, INPUTPROC inputProc) } else { - memset(&DIJoycap,0,sizeof(DIDEVCAPS)); - DIJoycap.dwSize=sizeof(DIDEVCAPS); + memset(&DIJoycap,0,sizeof(DIDEVCAPS)); + DIJoycap.dwSize=sizeof(DIDEVCAPS); IDirectInputDevice8_GetCapabilities(pJoystick,&DIJoycap); } } @@ -539,7 +539,7 @@ void INPUTCLASS::process() if (pKeyboard) { - hr=IDirectInputDevice8_GetDeviceState(pKeyboard,256,cDIBuf); + hr=IDirectInputDevice8_GetDeviceState(pKeyboard,256,cDIBuf); if (FAILED(hr)) { //LOG("DInput: keyboard acquire\n"); @@ -551,31 +551,31 @@ void INPUTCLASS::process() { DIJOYSTATE2 JoyStatus; - hr=IDirectInputDevice8_Poll(pJoystick); - if (FAILED(hr)) IDirectInputDevice8_Acquire(pJoystick); - else - { - hr=IDirectInputDevice8_GetDeviceState(pJoystick,sizeof(JoyStatus),&JoyStatus); - if (FAILED(hr)) hr=IDirectInputDevice8_Acquire(pJoystick); - else - { - memset(cDIBuf+255,0,sizeof(cDIBuf)-255); - //TODO: analog - //if (JoyStatus.lX<-1) cDIBuf[258]=-128; - //if (JoyStatus.lX>1) cDIBuf[259]=-128; - //if (JoyStatus.lY<-1) cDIBuf[256]=-128; - //if (JoyStatus.lY>1) cDIBuf[257]=-128; - - if (JoyStatus.rgdwPOV[0]==0) cDIBuf[256]=-128; - if (JoyStatus.rgdwPOV[0]==4500) { cDIBuf[256]=-128; cDIBuf[259]=-128;} - if (JoyStatus.rgdwPOV[0]==9000) cDIBuf[259]=-128; - if (JoyStatus.rgdwPOV[0]==13500) { cDIBuf[259]=-128; cDIBuf[257]=-128;} - if (JoyStatus.rgdwPOV[0]==18000) cDIBuf[257]=-128; - if (JoyStatus.rgdwPOV[0]==22500) { cDIBuf[257]=-128; cDIBuf[258]=-128;} - if (JoyStatus.rgdwPOV[0]==27000) cDIBuf[258]=-128; - if (JoyStatus.rgdwPOV[0]==31500) { cDIBuf[258]=-128; cDIBuf[256]=-128;} - memcpy(cDIBuf+260,JoyStatus.rgbButtons,sizeof(JoyStatus.rgbButtons)); - } + hr=IDirectInputDevice8_Poll(pJoystick); + if (FAILED(hr)) IDirectInputDevice8_Acquire(pJoystick); + else + { + hr=IDirectInputDevice8_GetDeviceState(pJoystick,sizeof(JoyStatus),&JoyStatus); + if (FAILED(hr)) hr=IDirectInputDevice8_Acquire(pJoystick); + else + { + memset(cDIBuf+255,0,sizeof(cDIBuf)-255); + //TODO: analog + //if (JoyStatus.lX<-1) cDIBuf[258]=-128; + //if (JoyStatus.lX>1) cDIBuf[259]=-128; + //if (JoyStatus.lY<-1) cDIBuf[256]=-128; + //if (JoyStatus.lY>1) cDIBuf[257]=-128; + + if (JoyStatus.rgdwPOV[0]==0) cDIBuf[256]=-128; + if (JoyStatus.rgdwPOV[0]==4500) { cDIBuf[256]=-128; cDIBuf[259]=-128;} + if (JoyStatus.rgdwPOV[0]==9000) cDIBuf[259]=-128; + if (JoyStatus.rgdwPOV[0]==13500) { cDIBuf[259]=-128; cDIBuf[257]=-128;} + if (JoyStatus.rgdwPOV[0]==18000) cDIBuf[257]=-128; + if (JoyStatus.rgdwPOV[0]==22500) { cDIBuf[257]=-128; cDIBuf[258]=-128;} + if (JoyStatus.rgdwPOV[0]==27000) cDIBuf[258]=-128; + if (JoyStatus.rgdwPOV[0]==31500) { cDIBuf[258]=-128; cDIBuf[256]=-128;} + memcpy(cDIBuf+260,JoyStatus.rgbButtons,sizeof(JoyStatus.rgbButtons)); + } } } diff --git a/desmume/src/windows/inputdx.h b/src/windows/inputdx.h similarity index 100% rename from desmume/src/windows/inputdx.h rename to src/windows/inputdx.h diff --git a/desmume/src/windows/lightView.cpp b/src/windows/lightView.cpp similarity index 100% rename from desmume/src/windows/lightView.cpp rename to src/windows/lightView.cpp diff --git a/desmume/src/windows/lightView.h b/src/windows/lightView.h similarity index 100% rename from desmume/src/windows/lightView.h rename to src/windows/lightView.h diff --git a/desmume/src/windows/main.cpp b/src/windows/main.cpp similarity index 100% rename from desmume/src/windows/main.cpp rename to src/windows/main.cpp diff --git a/desmume/src/windows/mapView.cpp b/src/windows/mapView.cpp similarity index 100% rename from desmume/src/windows/mapView.cpp rename to src/windows/mapView.cpp diff --git a/desmume/src/windows/mapView.h b/src/windows/mapView.h similarity index 100% rename from desmume/src/windows/mapView.h rename to src/windows/mapView.h diff --git a/desmume/src/windows/matrixView.cpp b/src/windows/matrixView.cpp similarity index 100% rename from desmume/src/windows/matrixView.cpp rename to src/windows/matrixView.cpp diff --git a/desmume/src/windows/matrixView.h b/src/windows/matrixView.h similarity index 100% rename from desmume/src/windows/matrixView.h rename to src/windows/matrixView.h diff --git a/desmume/src/windows/memView.cpp b/src/windows/memView.cpp similarity index 100% rename from desmume/src/windows/memView.cpp rename to src/windows/memView.cpp diff --git a/desmume/src/windows/memView.h b/src/windows/memView.h similarity index 100% rename from desmume/src/windows/memView.h rename to src/windows/memView.h diff --git a/desmume/src/windows/oamView.cpp b/src/windows/oamView.cpp similarity index 100% rename from desmume/src/windows/oamView.cpp rename to src/windows/oamView.cpp diff --git a/desmume/src/windows/oamView.h b/src/windows/oamView.h similarity index 100% rename from desmume/src/windows/oamView.h rename to src/windows/oamView.h diff --git a/desmume/src/windows/ogl.cpp b/src/windows/ogl.cpp similarity index 100% rename from desmume/src/windows/ogl.cpp rename to src/windows/ogl.cpp diff --git a/desmume/src/windows/palView.cpp b/src/windows/palView.cpp similarity index 100% rename from desmume/src/windows/palView.cpp rename to src/windows/palView.cpp diff --git a/desmume/src/windows/palView.h b/src/windows/palView.h similarity index 100% rename from desmume/src/windows/palView.h rename to src/windows/palView.h diff --git a/desmume/src/windows/resource.h b/src/windows/resource.h similarity index 100% rename from desmume/src/windows/resource.h rename to src/windows/resource.h diff --git a/desmume/src/windows/resources.rc b/src/windows/resources.rc similarity index 100% rename from desmume/src/windows/resources.rc rename to src/windows/resources.rc diff --git a/desmume/src/windows/snddx.cpp b/src/windows/snddx.cpp similarity index 100% rename from desmume/src/windows/snddx.cpp rename to src/windows/snddx.cpp diff --git a/desmume/src/windows/snddx.h b/src/windows/snddx.h similarity index 100% rename from desmume/src/windows/snddx.h rename to src/windows/snddx.h diff --git a/desmume/src/windows/throttle.cpp b/src/windows/throttle.cpp similarity index 100% rename from desmume/src/windows/throttle.cpp rename to src/windows/throttle.cpp diff --git a/desmume/src/windows/throttle.h b/src/windows/throttle.h similarity index 100% rename from desmume/src/windows/throttle.h rename to src/windows/throttle.h diff --git a/desmume/src/windows/tileView.cpp b/src/windows/tileView.cpp similarity index 100% rename from desmume/src/windows/tileView.cpp rename to src/windows/tileView.cpp diff --git a/desmume/src/windows/tileView.h b/src/windows/tileView.h similarity index 100% rename from desmume/src/windows/tileView.h rename to src/windows/tileView.h diff --git a/desmume/src/windows/windriver.h b/src/windows/windriver.h similarity index 100% rename from desmume/src/windows/windriver.h rename to src/windows/windriver.h diff --git a/desmume/src/windows/zlib123/README b/src/windows/zlib123/README similarity index 100% rename from desmume/src/windows/zlib123/README rename to src/windows/zlib123/README diff --git a/desmume/src/windows/zlib123/zconf.h b/src/windows/zlib123/zconf.h similarity index 100% rename from desmume/src/windows/zlib123/zconf.h rename to src/windows/zlib123/zconf.h diff --git a/desmume/src/windows/zlib123/zlib-2005-x32.lib b/src/windows/zlib123/zlib-2005-x32.lib similarity index 100% rename from desmume/src/windows/zlib123/zlib-2005-x32.lib rename to src/windows/zlib123/zlib-2005-x32.lib diff --git a/desmume/src/windows/zlib123/zlib-2005-x64.lib b/src/windows/zlib123/zlib-2005-x64.lib similarity index 100% rename from desmume/src/windows/zlib123/zlib-2005-x64.lib rename to src/windows/zlib123/zlib-2005-x64.lib diff --git a/desmume/src/windows/zlib123/zlib-2008-x32.lib b/src/windows/zlib123/zlib-2008-x32.lib similarity index 100% rename from desmume/src/windows/zlib123/zlib-2008-x32.lib rename to src/windows/zlib123/zlib-2008-x32.lib diff --git a/desmume/src/windows/zlib123/zlib-2008-x64.lib b/src/windows/zlib123/zlib-2008-x64.lib similarity index 100% rename from desmume/src/windows/zlib123/zlib-2008-x64.lib rename to src/windows/zlib123/zlib-2008-x64.lib diff --git a/desmume/src/windows/zlib123/zlib.h b/src/windows/zlib123/zlib.h similarity index 100% rename from desmume/src/windows/zlib123/zlib.h rename to src/windows/zlib123/zlib.h diff --git a/desmume/src/windows/zlib123/zutil.h b/src/windows/zlib123/zutil.h similarity index 100% rename from desmume/src/windows/zlib123/zutil.h rename to src/windows/zlib123/zutil.h diff --git a/desmume/src/windows/zziplib/README b/src/windows/zziplib/README similarity index 100% rename from desmume/src/windows/zziplib/README rename to src/windows/zziplib/README diff --git a/desmume/src/windows/zziplib/zzip/_msvc.h b/src/windows/zziplib/zzip/_msvc.h similarity index 100% rename from desmume/src/windows/zziplib/zzip/_msvc.h rename to src/windows/zziplib/zzip/_msvc.h diff --git a/desmume/src/windows/zziplib/zzip/conf.h b/src/windows/zziplib/zzip/conf.h similarity index 100% rename from desmume/src/windows/zziplib/zzip/conf.h rename to src/windows/zziplib/zzip/conf.h diff --git a/desmume/src/windows/zziplib/zzip/types.h b/src/windows/zziplib/zzip/types.h similarity index 100% rename from desmume/src/windows/zziplib/zzip/types.h rename to src/windows/zziplib/zzip/types.h diff --git a/desmume/src/windows/zziplib/zzip/zzip.h b/src/windows/zziplib/zzip/zzip.h similarity index 100% rename from desmume/src/windows/zziplib/zzip/zzip.h rename to src/windows/zziplib/zzip/zzip.h diff --git a/desmume/src/windows/zziplib/zziplib-2005-x32.lib b/src/windows/zziplib/zziplib-2005-x32.lib similarity index 100% rename from desmume/src/windows/zziplib/zziplib-2005-x32.lib rename to src/windows/zziplib/zziplib-2005-x32.lib diff --git a/desmume/src/windows/zziplib/zziplib-2005-x64.lib b/src/windows/zziplib/zziplib-2005-x64.lib similarity index 100% rename from desmume/src/windows/zziplib/zziplib-2005-x64.lib rename to src/windows/zziplib/zziplib-2005-x64.lib diff --git a/desmume/src/windows/zziplib/zziplib-2008-x32.lib b/src/windows/zziplib/zziplib-2008-x32.lib similarity index 100% rename from desmume/src/windows/zziplib/zziplib-2008-x32.lib rename to src/windows/zziplib/zziplib-2008-x32.lib diff --git a/desmume/src/windows/zziplib/zziplib-2008-x64.lib b/src/windows/zziplib/zziplib-2008-x64.lib similarity index 100% rename from desmume/src/windows/zziplib/zziplib-2008-x64.lib rename to src/windows/zziplib/zziplib-2008-x64.lib diff --git a/src/zero_private.h b/src/zero_private.h new file mode 100644 index 000000000..16279c0ae --- /dev/null +++ b/src/zero_private.h @@ -0,0 +1,12 @@ +#ifndef _zero_private_h +#define _zero_private_h + +//#define ZERO_MODE + +#ifdef ZERO_MODE +#define ASSERT_UNALIGNED(x) assert(x) +#else +#define ASSERT_UNALIGNED(x) +#endif + +#endif