From 0e05f39b215ec11196c4b369a7661826de33eb3b Mon Sep 17 00:00:00 2001 From: mtabachenko Date: Fri, 11 Dec 2009 19:16:15 +0000 Subject: [PATCH] core: - fix MMU crashes; --- desmume/src/MMU.cpp | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/desmume/src/MMU.cpp b/desmume/src/MMU.cpp index de39463e8..47acc309c 100644 --- a/desmume/src/MMU.cpp +++ b/desmume/src/MMU.cpp @@ -2344,7 +2344,7 @@ void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val) } - MMU.MMU_MEM[ARMCPU_ARM9][0x40][adr&MMU.MMU_MASK[ARMCPU_ARM9][0x40]]=val; + MMU.MMU_MEM[ARMCPU_ARM9][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]]=val; return; } @@ -2834,7 +2834,7 @@ void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val) } } - T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr&MMU.MMU_MASK[ARMCPU_ARM9][0x40], val); + T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20], val); return; } @@ -3257,7 +3257,7 @@ void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val) } } - T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM9][0x40], val); + T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][adr>>20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr>>20], val); return; } if(adr>=0x05000000 && adr<0x06200000) @@ -3305,7 +3305,6 @@ u8 FASTCALL _MMU_ARM9_read08(u32 adr) case eng_3D_GXSTAT: return MMU_new.gxstat.read(8,adr); } - return MMU.MMU_MEM[ARMCPU_ARM9][0x40][adr&MMU.MMU_MASK[ARMCPU_ARM9][0x40]]; } bool unmapped; @@ -3318,7 +3317,7 @@ u8 FASTCALL _MMU_ARM9_read08(u32 adr) //================================================= MMU ARM9 read 16 u16 FASTCALL _MMU_ARM9_read16(u32 adr) { - mmu_log_debug_ARM9(adr, "(read16) 0x%04X", T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr >> 20])); + mmu_log_debug_ARM9(adr, "(read16) 0x%04X", T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][(adr>>20)&0xFF], adr&MMU.MMU_MASK[ARMCPU_ARM9][(adr>>20)&0xFF])); if(adr<0x02000000) return T1ReadWord_guaranteedAligned(MMU.ARM9_ITCM, adr & 0x7FFE); @@ -3394,7 +3393,7 @@ u16 FASTCALL _MMU_ARM9_read16(u32 adr) } - return T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM9][0x40]); + return T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][adr>>20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]); } bool unmapped; @@ -3408,7 +3407,7 @@ u16 FASTCALL _MMU_ARM9_read16(u32 adr) //================================================= MMU ARM9 read 32 u32 FASTCALL _MMU_ARM9_read32(u32 adr) { - mmu_log_debug_ARM9(adr, "(read32) 0x%08X", T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][(adr >> 20)], adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20)])); + mmu_log_debug_ARM9(adr, "(read32) 0x%08X", T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][(adr>>20)&0xFF], adr&MMU.MMU_MASK[ARMCPU_ARM9][(adr>>20)&0xFF])); if(adr<0x02000000) return T1ReadLong_guaranteedAligned(MMU.ARM9_ITCM, adr&0x7FFC); @@ -3502,7 +3501,7 @@ u32 FASTCALL _MMU_ARM9_read32(u32 adr) case REG_GCDATAIN: return MMU_readFromGC(); } - return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM9][0x40]); + return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][adr>>20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]); } bool unmapped; @@ -3510,7 +3509,7 @@ u32 FASTCALL _MMU_ARM9_read32(u32 adr) if(unmapped) return 0; // Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [zeromus, inspired by shash] - return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][(adr >> 20)], adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20)]); + return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]); } //================================================================================================== ARM7 * //========================================================================================================= @@ -3568,7 +3567,7 @@ void FASTCALL _MMU_ARM7_write08(u32 adr, u8 val) write_auxspicnt(9,8,1,val); return; } - MMU.MMU_MEM[ARMCPU_ARM7][0x40][adr&MMU.MMU_MASK[ARMCPU_ARM7][0x40]]=val; + MMU.MMU_MEM[ARMCPU_ARM7][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]]=val; return; } @@ -3866,7 +3865,7 @@ void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val) } - T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], adr&MMU.MMU_MASK[ARMCPU_ARM7][0x40], val); + T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20], val); return; } @@ -3981,7 +3980,7 @@ void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val) MMU_writeToGCControl(val); return; } - T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM7][0x40], val); + T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr>>20], val); return; } @@ -4020,7 +4019,7 @@ u8 FASTCALL _MMU_ARM7_read08(u32 adr) // Address is an IO register //switch(adr) {} - return MMU.MMU_MEM[ARMCPU_ARM7][0x40][adr&MMU.MMU_MASK[ARMCPU_ARM7][0x40]]; + return MMU.MMU_MEM[ARMCPU_ARM7][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]]; } bool unmapped; @@ -4032,7 +4031,7 @@ u8 FASTCALL _MMU_ARM7_read08(u32 adr) //================================================= MMU ARM7 read 16 u16 FASTCALL _MMU_ARM7_read16(u32 adr) { - mmu_log_debug_ARM7(adr, "(read16) 0x%04X", T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr >> 20])); + mmu_log_debug_ARM7(adr, "(read16) 0x%04X", T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][(adr>>20)&0xFF], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr>>20)&0xFF])); //wifi mac access if ((adr>=0x04800000)&&(adr<0x05000000)) @@ -4085,7 +4084,7 @@ u16 FASTCALL _MMU_ARM7_read16(u32 adr) case REG_POSTFLG: return 1; } - return T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM7][0x40]); + return T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]); } bool unmapped; @@ -4099,7 +4098,7 @@ u16 FASTCALL _MMU_ARM7_read16(u32 adr) //================================================= MMU ARM7 read 32 u32 FASTCALL _MMU_ARM7_read32(u32 adr) { - mmu_log_debug_ARM7(adr, "(read32) 0x%08X", T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20)], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20)])); + mmu_log_debug_ARM7(adr, "(read32) 0x%08X", T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][(adr>>20)&0xFF], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr>>20)&0xFF])); //wifi mac access if ((adr>=0x04800000)&&(adr<0x05000000)) @@ -4145,7 +4144,7 @@ u32 FASTCALL _MMU_ARM7_read32(u32 adr) return MMU_readFromGC(); } - return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM7][0x40]); + return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]); } bool unmapped; @@ -4154,7 +4153,7 @@ u32 FASTCALL _MMU_ARM7_read32(u32 adr) //Returns data from memory // Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [zeromus, inspired by shash] - return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20)], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20)]); + return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr >> 20]); } //========================================================================================================= @@ -4501,3 +4500,4 @@ struct armcpu_memory_iface arm9_direct_memory_iface = { //print_memory_profiling( void) { //} //#endif /* End of PROFILE_MEMORY_ACCESS area */ +