From 0accc4eaf822035b99d2d77be1460d86b900d354 Mon Sep 17 00:00:00 2001 From: nitsuja Date: Tue, 22 Sep 2009 08:31:00 +0000 Subject: [PATCH] enabling cache emulation. this seems to fix timing bugs in several games. we can worry about the speed later. --- desmume/src/MMU_timing.h | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/desmume/src/MMU_timing.h b/desmume/src/MMU_timing.h index 4f405a8b3..dd51e1127 100644 --- a/desmume/src/MMU_timing.h +++ b/desmume/src/MMU_timing.h @@ -53,8 +53,7 @@ #define ACCOUNT_FOR_DATA_TCM_SPEED // enables simulation of cache hits and cache misses. - // currently disabled for a few FPS of emulator speedup. -//#define ENABLE_CACHE_CONTROLLER_EMULATION +#define ENABLE_CACHE_CONTROLLER_EMULATION // //////////////////////////////////////////////////////////////// @@ -283,9 +282,20 @@ FORCEINLINE u32 _MMU_accesstime(u32 addr, bool sequential) cached = MMU_timing.arm9dataCache.Cached(addr); if(cached) return MC; + u32 c; if(sequential && AT==MMU_AT_DATA) - return M16; - return M16 * ((DIRECTION == MMU_AD_READ) ? 5 : 4); + c = M16; // bonus for sequential data access + else if(DIRECTION == MMU_AD_READ) + c = M16 * 5; + else + c = M16 * 2; // should be 4, but write buffer isn't emulated yet. + if(DIRECTION == MMU_AD_READ) + { + // cache miss while reading means it has to fill a whole cache line + // by reading 32 bytes... + c += 8 * M32*2; + } + return c; #elif defined(ACCOUNT_FOR_NON_SEQUENTIAL_ACCESS) // this is the closest approximation I could find // to the with-cache-controller timing