mirror of https://github.com/bsnes-emu/bsnes.git
290 lines
7.4 KiB
C++
290 lines
7.4 KiB
C++
#ifdef CPU_CPP
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void CPU::dma_add_clocks(unsigned clocks) {
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status.dma_clocks += clocks;
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add_clocks(clocks);
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}
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//=============
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//memory access
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//=============
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bool CPU::dma_transfer_valid(uint8 bbus, uint32 abus) {
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//transfers from WRAM to WRAM are invalid; chip only has one address bus
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if(bbus == 0x80 && ((abus & 0xfe0000) == 0x7e0000 || (abus & 0x40e000) == 0x0000)) return false;
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return true;
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}
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bool CPU::dma_addr_valid(uint32 abus) {
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//A-bus access to B-bus or S-CPU registers are invalid
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if((abus & 0x40ff00) == 0x2100) return false; //$[00-3f|80-bf]:[2100-21ff]
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if((abus & 0x40fe00) == 0x4000) return false; //$[00-3f|80-bf]:[4000-41ff]
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if((abus & 0x40ffe0) == 0x4200) return false; //$[00-3f|80-bf]:[4200-421f]
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if((abus & 0x40ff80) == 0x4300) return false; //$[00-3f|80-bf]:[4300-437f]
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return true;
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}
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uint8 CPU::dma_read(uint32 abus) {
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if(dma_addr_valid(abus) == false) return 0x00;
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return bus.read(abus);
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}
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//simulate two-stage pipeline for DMA transfers; example:
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//cycle 0: read N+0
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//cycle 1: write N+0 & read N+1 (parallel; one on A-bus, one on B-bus)
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//cycle 2: write N+1 & read N+2 (parallel)
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//cycle 3: write N+2
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void CPU::dma_write(bool valid, unsigned addr, uint8 data) {
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if(pipe.valid) bus.write(pipe.addr, pipe.data);
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pipe.valid = valid;
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pipe.addr = addr;
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pipe.data = data;
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}
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void CPU::dma_transfer(bool direction, uint8 bbus, uint32 abus) {
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if(direction == 0) {
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dma_add_clocks(4);
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regs.mdr = dma_read(abus);
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dma_add_clocks(4);
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dma_write(dma_transfer_valid(bbus, abus), 0x2100 | bbus, regs.mdr);
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} else {
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dma_add_clocks(4);
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regs.mdr = dma_transfer_valid(bbus, abus) ? bus.read(0x2100 | bbus) : 0x00;
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dma_add_clocks(4);
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dma_write(dma_addr_valid(abus), abus, regs.mdr);
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}
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}
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//===================
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//address calculation
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//===================
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uint8 CPU::dma_bbus(unsigned i, unsigned index) {
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switch(channel[i].transfer_mode) { default:
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case 0: return (channel[i].dest_addr); //0
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case 1: return (channel[i].dest_addr + (index & 1)); //0,1
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case 2: return (channel[i].dest_addr); //0,0
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case 3: return (channel[i].dest_addr + ((index >> 1) & 1)); //0,0,1,1
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case 4: return (channel[i].dest_addr + (index & 3)); //0,1,2,3
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case 5: return (channel[i].dest_addr + (index & 1)); //0,1,0,1
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case 6: return (channel[i].dest_addr); //0,0 [2]
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case 7: return (channel[i].dest_addr + ((index >> 1) & 1)); //0,0,1,1 [3]
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}
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}
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inline uint32 CPU::dma_addr(unsigned i) {
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uint32 r = (channel[i].source_bank << 16) | (channel[i].source_addr);
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if(channel[i].fixed_transfer == false) {
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if(channel[i].reverse_transfer == false) {
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channel[i].source_addr++;
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} else {
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channel[i].source_addr--;
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}
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}
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return r;
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}
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inline uint32 CPU::hdma_addr(unsigned i) {
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return (channel[i].source_bank << 16) | (channel[i].hdma_addr++);
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}
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inline uint32 CPU::hdma_iaddr(unsigned i) {
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return (channel[i].indirect_bank << 16) | (channel[i].indirect_addr++);
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}
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//==============
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//channel status
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//==============
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uint8 CPU::dma_enabled_channels() {
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uint8 r = 0;
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for(unsigned i = 0; i < 8; i++) {
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if(channel[i].dma_enabled) r++;
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}
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return r;
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}
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inline bool CPU::hdma_active(unsigned i) {
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return (channel[i].hdma_enabled && !channel[i].hdma_completed);
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}
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inline bool CPU::hdma_active_after(unsigned i) {
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for(unsigned n = i + 1; n < 8; n++) {
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if(hdma_active(n) == true) return true;
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}
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return false;
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}
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inline uint8 CPU::hdma_enabled_channels() {
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uint8 r = 0;
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for(unsigned i = 0; i < 8; i++) {
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if(channel[i].hdma_enabled) r++;
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}
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return r;
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}
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inline uint8 CPU::hdma_active_channels() {
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uint8 r = 0;
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for(unsigned i = 0; i < 8; i++) {
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if(hdma_active(i) == true) r++;
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}
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return r;
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}
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//==============
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//core functions
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//==============
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void CPU::dma_run() {
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dma_add_clocks(8);
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dma_write(false);
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dma_edge();
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for(unsigned i = 0; i < 8; i++) {
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if(channel[i].dma_enabled == false) continue;
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unsigned index = 0;
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do {
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dma_transfer(channel[i].direction, dma_bbus(i, index++), dma_addr(i));
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dma_edge();
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} while(channel[i].dma_enabled && --channel[i].transfer_size);
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dma_add_clocks(8);
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dma_write(false);
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dma_edge();
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channel[i].dma_enabled = false;
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}
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status.irq_lock = true;
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}
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void CPU::hdma_update(unsigned i) {
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dma_add_clocks(4);
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regs.mdr = dma_read((channel[i].source_bank << 16) | channel[i].hdma_addr);
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dma_add_clocks(4);
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dma_write(false);
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if((channel[i].line_counter & 0x7f) == 0) {
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channel[i].line_counter = regs.mdr;
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channel[i].hdma_addr++;
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channel[i].hdma_completed = (channel[i].line_counter == 0);
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channel[i].hdma_do_transfer = !channel[i].hdma_completed;
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if(channel[i].indirect) {
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dma_add_clocks(4);
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regs.mdr = dma_read(hdma_addr(i));
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channel[i].indirect_addr = regs.mdr << 8;
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dma_add_clocks(4);
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dma_write(false);
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if(!channel[i].hdma_completed || hdma_active_after(i)) {
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dma_add_clocks(4);
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regs.mdr = dma_read(hdma_addr(i));
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channel[i].indirect_addr >>= 8;
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channel[i].indirect_addr |= regs.mdr << 8;
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dma_add_clocks(4);
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dma_write(false);
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}
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}
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}
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}
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void CPU::hdma_run() {
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dma_add_clocks(8);
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dma_write(false);
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for(unsigned i = 0; i < 8; i++) {
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if(hdma_active(i) == false) continue;
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channel[i].dma_enabled = false; //HDMA run during DMA will stop DMA mid-transfer
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if(channel[i].hdma_do_transfer) {
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static const unsigned transfer_length[8] = { 1, 2, 2, 4, 4, 4, 2, 4 };
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unsigned length = transfer_length[channel[i].transfer_mode];
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for(unsigned index = 0; index < length; index++) {
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unsigned addr = channel[i].indirect == false ? hdma_addr(i) : hdma_iaddr(i);
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dma_transfer(channel[i].direction, dma_bbus(i, index), addr);
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}
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}
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}
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for(unsigned i = 0; i < 8; i++) {
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if(hdma_active(i) == false) continue;
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channel[i].line_counter--;
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channel[i].hdma_do_transfer = channel[i].line_counter & 0x80;
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hdma_update(i);
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}
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status.irq_lock = true;
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}
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void CPU::hdma_init_reset() {
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for(unsigned i = 0; i < 8; i++) {
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channel[i].hdma_completed = false;
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channel[i].hdma_do_transfer = false;
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}
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}
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void CPU::hdma_init() {
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dma_add_clocks(8);
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dma_write(false);
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for(unsigned i = 0; i < 8; i++) {
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if(!channel[i].hdma_enabled) continue;
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channel[i].dma_enabled = false; //HDMA init during DMA will stop DMA mid-transfer
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channel[i].hdma_addr = channel[i].source_addr;
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channel[i].line_counter = 0;
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hdma_update(i);
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}
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status.irq_lock = true;
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}
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//==============
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//initialization
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//==============
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void CPU::dma_power() {
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for(unsigned i = 0; i < 8; i++) {
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channel[i].direction = 1;
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channel[i].indirect = true;
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channel[i].unused = true;
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channel[i].reverse_transfer = true;
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channel[i].fixed_transfer = true;
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channel[i].transfer_mode = 7;
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channel[i].dest_addr = 0xff;
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channel[i].source_addr = 0xffff;
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channel[i].source_bank = 0xff;
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channel[i].transfer_size = 0xffff;
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channel[i].indirect_bank = 0xff;
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channel[i].hdma_addr = 0xffff;
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channel[i].line_counter = 0xff;
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channel[i].unknown = 0xff;
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}
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}
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void CPU::dma_reset() {
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for(unsigned i = 0; i < 8; i++) {
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channel[i].dma_enabled = false;
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channel[i].hdma_enabled = false;
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channel[i].hdma_completed = false;
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channel[i].hdma_do_transfer = false;
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}
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pipe.valid = false;
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pipe.addr = 0;
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pipe.data = 0;
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}
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#endif
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