bsnes/higan/processor
Tim Allen d6e9d94ec3 Update to v101r17 release.
byuu says:

Changelog:

  - Z80: added most opcodes between 0x00 and 0x3f (two or three hard
    ones missing still)
  - Z80: redid register declaration *again* to handle AF', BC', DE',
    HL' (ugggggh, the fuck? Alternate registers??)
      - basically, using `#define <register name>` values to get around
        horrendously awful naming syntax
  - Z80: improved handling of displace() so that it won't ever trigger
    on (BC) or (DE)
2016-09-06 23:53:14 +10:00
..
arm Update to v099r13 release. 2016-06-29 21:10:28 +10:00
gsu Update to v099r12 release. 2016-06-28 20:43:47 +10:00
hg51b Update to v098r06 release. 2016-04-22 23:35:51 +10:00
lr35902 Update to v098r17 release. 2016-06-06 08:10:01 +10:00
m68k Update to v101r15 release. 2016-09-04 23:51:27 +10:00
r6502 Update to v099r12 release. 2016-06-28 20:43:47 +10:00
r65816 Update to v100r07 release. 2016-07-17 13:24:28 +10:00
spc700 Update to v100r15 release. 2016-07-31 12:11:20 +10:00
upd96050 Update to v099r12 release. 2016-06-28 20:43:47 +10:00
v30mz Update to v100r01 release. 2016-07-08 22:31:35 +10:00
z80 Update to v101r17 release. 2016-09-06 23:53:14 +10:00
GNUmakefile Update to v100r03 release. 2016-07-10 15:28:26 +10:00
processor.hpp Update to v097r01 release. 2016-01-23 18:29:34 +11:00