mirror of https://github.com/bsnes-emu/bsnes.git
95 lines
2.7 KiB
C++
95 lines
2.7 KiB
C++
auto GSU::instruction(uint8 opcode) -> void {
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#define op(id, name, ...) \
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case id: return instruction##name(__VA_ARGS__); \
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#define op4(id, name) \
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case id+ 0: return instruction##name((uint4)opcode); \
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case id+ 1: return instruction##name((uint4)opcode); \
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case id+ 2: return instruction##name((uint4)opcode); \
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case id+ 3: return instruction##name((uint4)opcode); \
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#define op6(id, name) \
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op4(id, name) \
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case id+ 4: return instruction##name((uint4)opcode); \
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case id+ 5: return instruction##name((uint4)opcode); \
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#define op12(id, name) \
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op6(id, name) \
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case id+ 6: return instruction##name((uint4)opcode); \
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case id+ 7: return instruction##name((uint4)opcode); \
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case id+ 8: return instruction##name((uint4)opcode); \
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case id+ 9: return instruction##name((uint4)opcode); \
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case id+10: return instruction##name((uint4)opcode); \
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case id+11: return instruction##name((uint4)opcode); \
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#define op15(id, name) \
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op12(id, name) \
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case id+12: return instruction##name((uint4)opcode); \
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case id+13: return instruction##name((uint4)opcode); \
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case id+14: return instruction##name((uint4)opcode); \
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#define op16(id, name) \
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op15(id, name) \
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case id+15: return instruction##name((uint4)opcode); \
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switch(opcode) {
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op (0x00, STOP)
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op (0x01, NOP)
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op (0x02, CACHE)
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op (0x03, LSR)
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op (0x04, ROL)
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op (0x05, Branch, 1) //bra
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op (0x06, Branch, (regs.sfr.s ^ regs.sfr.ov) == 0) //blt
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op (0x07, Branch, (regs.sfr.s ^ regs.sfr.ov) == 1) //bge
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op (0x08, Branch, regs.sfr.z == 0) //bne
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op (0x09, Branch, regs.sfr.z == 1) //beq
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op (0x0a, Branch, regs.sfr.s == 0) //bpl
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op (0x0b, Branch, regs.sfr.s == 1) //bmi
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op (0x0c, Branch, regs.sfr.cy == 0) //bcc
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op (0x0d, Branch, regs.sfr.cy == 1) //bcs
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op (0x0e, Branch, regs.sfr.ov == 0) //bvc
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op (0x0f, Branch, regs.sfr.ov == 1) //bvs
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op16(0x10, TO_MOVE)
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op16(0x20, WITH)
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op12(0x30, Store)
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op (0x3c, LOOP)
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op (0x3d, ALT1)
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op (0x3e, ALT2)
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op (0x3f, ALT3)
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op12(0x40, Load)
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op (0x4c, PLOT_RPIX)
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op (0x4d, SWAP)
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op (0x4e, COLOR_CMODE)
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op (0x4f, NOT)
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op16(0x50, ADD_ADC)
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op16(0x60, SUB_SBC_CMP)
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op (0x70, MERGE)
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op15(0x71, AND_BIC)
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op16(0x80, MULT_UMULT)
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op (0x90, SBK)
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op4 (0x91, LINK)
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op (0x95, SEX)
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op (0x96, ASR_DIV2)
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op (0x97, ROR)
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op6 (0x98, JMP_LJMP)
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op (0x9e, LOB)
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op (0x9f, FMULT_LMULT)
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op16(0xa0, IBT_LMS_SMS)
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op16(0xb0, FROM_MOVES)
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op (0xc0, HIB)
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op15(0xc1, OR_XOR)
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op15(0xd0, INC)
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op (0xdf, GETC_RAMB_ROMB)
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op15(0xe0, DEC)
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op (0xef, GETB)
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op16(0xf0, IWT_LM_SM)
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}
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#undef op
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#undef op4
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#undef op6
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#undef op12
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#undef op15
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#undef op16
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}
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