mirror of https://github.com/bsnes-emu/bsnes.git
490 lines
13 KiB
C++
490 lines
13 KiB
C++
struct MMC5 : Chip {
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MMC5(Board& board) : Chip(board) {
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revision = Revision::MMC5;
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}
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auto main() -> void {
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//scanline() resets this; if no scanlines detected, enter video blanking period
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if(++cpu_cycle_counter >= 200) blank(); //113-114 normal; ~2500 across Vblank period
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cpu.irqLine(irq_enable && irq_pending);
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tick();
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}
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auto scanline(uint y) -> void {
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//used for testing only, to verify MMC5 scanline detection is accurate:
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//if(y != vcounter && y <= 240) print(y, " vs ", vcounter, "\n");
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}
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auto prg_access(bool write, uint addr, uint8 data = 0x00) -> uint8 {
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uint bank;
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if((addr & 0xe000) == 0x6000) {
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bank = (ram_select << 2) | ram_bank;
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addr &= 0x1fff;
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} else if(prg_mode == 0) {
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bank = prg_bank[3] & ~3;
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addr &= 0x7fff;
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} else if(prg_mode == 1) {
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if((addr & 0xc000) == 0x8000) bank = (prg_bank[1] & ~1);
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if((addr & 0xe000) == 0xc000) bank = (prg_bank[3] & ~1);
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addr &= 0x3fff;
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} else if(prg_mode == 2) {
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if((addr & 0xe000) == 0x8000) bank = (prg_bank[1] & ~1) | 0;
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if((addr & 0xe000) == 0xa000) bank = (prg_bank[1] & ~1) | 1;
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if((addr & 0xe000) == 0xc000) bank = (prg_bank[2]);
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if((addr & 0xe000) == 0xe000) bank = (prg_bank[3]);
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addr &= 0x1fff;
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} else if(prg_mode == 3) {
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if((addr & 0xe000) == 0x8000) bank = prg_bank[0];
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if((addr & 0xe000) == 0xa000) bank = prg_bank[1];
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if((addr & 0xe000) == 0xc000) bank = prg_bank[2];
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if((addr & 0xe000) == 0xe000) bank = prg_bank[3];
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addr &= 0x1fff;
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}
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bool rom = bank & 0x80;
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bank &= 0x7f;
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if(write == false) {
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if(rom) {
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return board.prgrom.read((bank << 13) | addr);
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} else {
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return board.prgram.read((bank << 13) | addr);
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}
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} else {
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if(rom) {
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board.prgrom.write((bank << 13) | addr, data);
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} else {
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if(prgram_write_protect[0] == 2 && prgram_write_protect[1] == 1) {
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board.prgram.write((bank << 13) | addr, data);
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}
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}
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return 0x00;
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}
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}
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auto prg_read(uint addr) -> uint8 {
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if((addr & 0xfc00) == 0x5c00) {
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if(exram_mode >= 2) return exram[addr & 0x03ff];
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return cpu.mdr();
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}
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if(addr >= 0x6000) {
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return prg_access(0, addr);
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}
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switch(addr) {
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case 0x5204: {
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uint8 result = (irq_pending << 7) | (in_frame << 6);
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irq_pending = false;
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return result;
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}
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case 0x5205: return (multiplier * multiplicand) >> 0;
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case 0x5206: return (multiplier * multiplicand) >> 8;
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}
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}
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auto prg_write(uint addr, uint8 data) -> void {
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if((addr & 0xfc00) == 0x5c00) {
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//writes 0x00 *during* Vblank (not during screen rendering ...)
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if(exram_mode == 0 || exram_mode == 1) exram[addr & 0x03ff] = in_frame ? data : (uint8)0x00;
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if(exram_mode == 2) exram[addr & 0x03ff] = data;
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return;
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}
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if(addr >= 0x6000) {
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prg_access(1, addr, data);
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return;
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}
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switch(addr) {
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case 0x2000:
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sprite_8x16 = data & 0x20;
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break;
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case 0x2001:
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//if BG+sprites are disabled; enter video blanking period
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if((data & 0x18) == 0) blank();
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break;
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case 0x5100: prg_mode = data & 3; break;
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case 0x5101: chr_mode = data & 3; break;
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case 0x5102: prgram_write_protect[0] = data & 3; break;
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case 0x5103: prgram_write_protect[1] = data & 3; break;
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case 0x5104:
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exram_mode = data & 3;
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break;
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case 0x5105:
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nametable_mode[0] = (data & 0x03) >> 0;
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nametable_mode[1] = (data & 0x0c) >> 2;
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nametable_mode[2] = (data & 0x30) >> 4;
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nametable_mode[3] = (data & 0xc0) >> 6;
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break;
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case 0x5106:
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fillmode_tile = data;
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break;
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case 0x5107:
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fillmode_color = data & 3;
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fillmode_color |= fillmode_color << 2;
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fillmode_color |= fillmode_color << 4;
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break;
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case 0x5113:
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ram_select = data & 0x04;
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ram_bank = data & 0x03;
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break;
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case 0x5114: prg_bank[0] = data; break;
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case 0x5115: prg_bank[1] = data; break;
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case 0x5116: prg_bank[2] = data; break;
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case 0x5117: prg_bank[3] = data | 0x80; break;
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case 0x5120: chr_sprite_bank[0] = (chr_bank_hi << 8) | data; chr_active = 0; break;
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case 0x5121: chr_sprite_bank[1] = (chr_bank_hi << 8) | data; chr_active = 0; break;
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case 0x5122: chr_sprite_bank[2] = (chr_bank_hi << 8) | data; chr_active = 0; break;
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case 0x5123: chr_sprite_bank[3] = (chr_bank_hi << 8) | data; chr_active = 0; break;
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case 0x5124: chr_sprite_bank[4] = (chr_bank_hi << 8) | data; chr_active = 0; break;
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case 0x5125: chr_sprite_bank[5] = (chr_bank_hi << 8) | data; chr_active = 0; break;
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case 0x5126: chr_sprite_bank[6] = (chr_bank_hi << 8) | data; chr_active = 0; break;
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case 0x5127: chr_sprite_bank[7] = (chr_bank_hi << 8) | data; chr_active = 0; break;
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case 0x5128: chr_bg_bank[0] = (chr_bank_hi << 8) | data; chr_active = 1; break;
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case 0x5129: chr_bg_bank[1] = (chr_bank_hi << 8) | data; chr_active = 1; break;
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case 0x512a: chr_bg_bank[2] = (chr_bank_hi << 8) | data; chr_active = 1; break;
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case 0x512b: chr_bg_bank[3] = (chr_bank_hi << 8) | data; chr_active = 1; break;
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case 0x5130:
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chr_bank_hi = data & 3;
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break;
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case 0x5200:
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vs_enable = data & 0x80;
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vs_side = data & 0x40;
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vs_tile = data & 0x1f;
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break;
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case 0x5201:
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vs_scroll = data;
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break;
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case 0x5202:
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vs_bank = data;
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break;
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case 0x5203:
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irq_line = data;
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break;
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case 0x5204:
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irq_enable = data & 0x80;
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break;
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case 0x5205:
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multiplicand = data;
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break;
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case 0x5206:
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multiplier = data;
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break;
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}
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}
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auto chr_sprite_addr(uint addr) -> uint {
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if(chr_mode == 0) {
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auto bank = chr_sprite_bank[7];
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return (bank * 0x2000) + (addr & 0x1fff);
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}
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if(chr_mode == 1) {
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auto bank = chr_sprite_bank[(addr / 0x1000) * 4 + 3];
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return (bank * 0x1000) + (addr & 0x0fff);
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}
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if(chr_mode == 2) {
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auto bank = chr_sprite_bank[(addr / 0x0800) * 2 + 1];
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return (bank * 0x0800) + (addr & 0x07ff);
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}
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if(chr_mode == 3) {
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auto bank = chr_sprite_bank[(addr / 0x0400)];
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return (bank * 0x0400) + (addr & 0x03ff);
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}
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}
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auto chr_bg_addr(uint addr) -> uint {
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addr &= 0x0fff;
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if(chr_mode == 0) {
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auto bank = chr_bg_bank[3];
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return (bank * 0x2000) + (addr & 0x0fff);
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}
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if(chr_mode == 1) {
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auto bank = chr_bg_bank[3];
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return (bank * 0x1000) + (addr & 0x0fff);
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}
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if(chr_mode == 2) {
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auto bank = chr_bg_bank[(addr / 0x0800) * 2 + 1];
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return (bank * 0x0800) + (addr & 0x07ff);
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}
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if(chr_mode == 3) {
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auto bank = chr_bg_bank[(addr / 0x0400)];
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return (bank * 0x0400) + (addr & 0x03ff);
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}
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}
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auto chr_vs_addr(uint addr) -> uint {
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return (vs_bank * 0x1000) + (addr & 0x0ff8) + (vs_vpos & 7);
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}
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auto blank() -> void {
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in_frame = false;
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}
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auto scanline() -> void {
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hcounter = 0;
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if(in_frame == false) {
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in_frame = true;
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irq_pending = false;
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vcounter = 0;
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} else {
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if(vcounter == irq_line) irq_pending = true;
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vcounter++;
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}
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cpu_cycle_counter = 0;
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}
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auto ciram_read(uint addr) -> uint8 {
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if(vs_fetch && (hcounter & 2) == 0) return exram[vs_vpos / 8 * 32 + vs_hpos / 8];
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if(vs_fetch && (hcounter & 2) != 0) return exram[vs_vpos / 32 * 8 + vs_hpos / 32 + 0x03c0];
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switch(nametable_mode[(addr >> 10) & 3]) {
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case 0: return ppu.readCIRAM(0x0000 | (addr & 0x03ff));
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case 1: return ppu.readCIRAM(0x0400 | (addr & 0x03ff));
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case 2: return exram_mode < 2 ? exram[addr & 0x03ff] : (uint8)0x00;
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case 3: return (hcounter & 2) == 0 ? fillmode_tile : fillmode_color;
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}
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}
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auto chr_read(uint addr) -> uint8 {
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chr_access[0] = chr_access[1];
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chr_access[1] = chr_access[2];
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chr_access[2] = chr_access[3];
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chr_access[3] = addr;
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//detect two unused nametable fetches at end of each scanline
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if((chr_access[0] & 0x2000) == 0
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&& (chr_access[1] & 0x2000)
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&& (chr_access[2] & 0x2000)
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&& (chr_access[3] & 0x2000)) scanline();
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if(in_frame == false) {
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vs_fetch = false;
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if(addr & 0x2000) return ciram_read(addr);
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return board.chrrom.read(chr_active ? chr_bg_addr(addr) : chr_sprite_addr(addr));
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}
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bool bg_fetch = (hcounter < 256 || hcounter >= 320);
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uint8 result = 0x00;
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if((hcounter & 7) == 0) {
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vs_hpos = hcounter >= 320 ? hcounter - 320 : hcounter + 16;
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vs_vpos = vcounter + vs_scroll;
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vs_fetch = vs_enable && bg_fetch && exram_mode < 2
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&& (vs_side ? vs_hpos / 8 >= vs_tile : vs_hpos / 8 < vs_tile);
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if(vs_vpos >= 240) vs_vpos -= 240;
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result = ciram_read(addr);
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exbank = (chr_bank_hi << 6) | (exram[addr & 0x03ff] & 0x3f);
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exattr = exram[addr & 0x03ff] >> 6;
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exattr |= exattr << 2;
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exattr |= exattr << 4;
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} else if((hcounter & 7) == 2) {
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result = ciram_read(addr);
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if(bg_fetch && exram_mode == 1) result = exattr;
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} else {
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if(vs_fetch) result = board.chrrom.read(chr_vs_addr(addr));
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else if(sprite_8x16 ? bg_fetch : chr_active) result = board.chrrom.read(chr_bg_addr(addr));
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else result = board.chrrom.read(chr_sprite_addr(addr));
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if(bg_fetch && exram_mode == 1) result = board.chrrom.read(exbank * 0x1000 + (addr & 0x0fff));
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}
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hcounter += 2;
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return result;
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}
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auto chr_write(uint addr, uint8 data) -> void {
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if(addr & 0x2000) {
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switch(nametable_mode[(addr >> 10) & 3]) {
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case 0: return ppu.writeCIRAM(0x0000 | (addr & 0x03ff), data);
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case 1: return ppu.writeCIRAM(0x0400 | (addr & 0x03ff), data);
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case 2: exram[addr & 0x03ff] = data; break;
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}
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}
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}
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auto power() -> void {
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}
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auto reset() -> void {
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for(auto& n : exram) n = 0xff;
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prg_mode = 3;
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chr_mode = 0;
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for(auto& n : prgram_write_protect) n = 0;
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exram_mode = 0;
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for(auto& n : nametable_mode) n = 0;
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fillmode_tile = 0;
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fillmode_color = 0;
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ram_select = 0;
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ram_bank = 0;
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prg_bank[0] = 0x00;
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prg_bank[1] = 0x00;
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prg_bank[2] = 0x00;
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prg_bank[3] = 0xff;
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for(auto& n : chr_sprite_bank) n = 0;
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for(auto& n : chr_bg_bank) n = 0;
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chr_bank_hi = 0;
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vs_enable = 0;
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vs_side = 0;
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vs_tile = 0;
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vs_scroll = 0;
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vs_bank = 0;
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irq_line = 0;
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irq_enable = 0;
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multiplicand = 0;
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multiplier = 0;
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cpu_cycle_counter = 0;
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irq_counter = 0;
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irq_pending = 0;
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in_frame = 0;
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vcounter = 0;
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hcounter = 0;
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for(auto& n : chr_access) n = 0;
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chr_active = 0;
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sprite_8x16 = 0;
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exbank = 0;
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exattr = 0;
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vs_fetch = 0;
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vs_vpos = 0;
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vs_hpos = 0;
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}
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auto serialize(serializer& s) -> void {
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s.array(exram);
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s.integer(prg_mode);
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s.integer(chr_mode);
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for(auto& n : prgram_write_protect) s.integer(n);
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s.integer(exram_mode);
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for(auto& n : nametable_mode) s.integer(n);
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s.integer(fillmode_tile);
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s.integer(fillmode_color);
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s.integer(ram_select);
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s.integer(ram_bank);
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for(auto& n : prg_bank) s.integer(n);
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for(auto& n : chr_sprite_bank) s.integer(n);
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for(auto& n : chr_bg_bank) s.integer(n);
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s.integer(chr_bank_hi);
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s.integer(vs_enable);
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s.integer(vs_side);
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s.integer(vs_tile);
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s.integer(vs_scroll);
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s.integer(vs_bank);
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s.integer(irq_line);
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s.integer(irq_enable);
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s.integer(multiplicand);
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s.integer(multiplier);
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s.integer(cpu_cycle_counter);
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s.integer(irq_counter);
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s.integer(irq_pending);
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s.integer(in_frame);
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s.integer(vcounter);
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s.integer(hcounter);
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for(auto& n : chr_access) s.integer(n);
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s.integer(chr_active);
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s.integer(sprite_8x16);
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s.integer(exbank);
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s.integer(exattr);
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s.integer(vs_fetch);
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s.integer(vs_vpos);
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s.integer(vs_hpos);
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}
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enum class Revision : uint {
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MMC5,
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MMC5B,
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} revision;
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uint8 exram[1024];
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//programmable registers
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uint2 prg_mode; //$5100
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uint2 chr_mode; //$5101
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uint2 prgram_write_protect[2]; //$5102,$5103
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uint2 exram_mode; //$5104
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uint2 nametable_mode[4]; //$5105
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uint8 fillmode_tile; //$5106
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uint8 fillmode_color; //$5107
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bool ram_select; //$5113
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uint2 ram_bank; //$5113
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uint8 prg_bank[4]; //$5114-5117
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uint10 chr_sprite_bank[8]; //$5120-5127
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uint10 chr_bg_bank[4]; //$5128-512b
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uint2 chr_bank_hi; //$5130
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bool vs_enable; //$5200
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bool vs_side; //$5200
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uint5 vs_tile; //$5200
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uint8 vs_scroll; //$5201
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uint8 vs_bank; //$5202
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uint8 irq_line; //$5203
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bool irq_enable; //$5204
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uint8 multiplicand; //$5205
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uint8 multiplier; //$5206
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//status registers
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uint cpu_cycle_counter;
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uint irq_counter;
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bool irq_pending;
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bool in_frame;
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uint vcounter;
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uint hcounter;
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uint16 chr_access[4];
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bool chr_active;
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bool sprite_8x16;
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uint8 exbank;
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uint8 exattr;
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bool vs_fetch;
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|
uint8 vs_vpos;
|
|
uint8 vs_hpos;
|
|
};
|