mirror of https://github.com/bsnes-emu/bsnes.git
111 lines
3.2 KiB
C++
111 lines
3.2 KiB
C++
struct VRC2 : Chip {
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uint5 prg_bank[2];
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uint8 chr_bank[8];
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uint2 mirror;
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bool latch;
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unsigned prg_addr(unsigned addr) const {
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unsigned bank;
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switch(addr & 0xe000) {
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case 0x8000: bank = prg_bank[0]; break;
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case 0xa000: bank = prg_bank[1]; break;
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case 0xc000: bank = 0x1e; break;
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case 0xe000: bank = 0x1f; break;
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}
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return (bank * 0x2000) + (addr & 0x1fff);
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}
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unsigned chr_addr(unsigned addr) const {
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unsigned bank = chr_bank[addr / 0x0400];
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return (bank * 0x0400) + (addr & 0x03ff);
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}
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unsigned ciram_addr(unsigned addr) const {
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switch(mirror) {
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case 0: return ((addr & 0x0400) >> 0) | (addr & 0x03ff); //vertical mirroring
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case 1: return ((addr & 0x0800) >> 1) | (addr & 0x03ff); //horizontal mirroring
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case 2: return 0x0000 | (addr & 0x03ff); //one-screen mirroring (first)
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case 3: return 0x0400 | (addr & 0x03ff); //one-screen mirroring (second)
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}
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throw;
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}
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uint8 ram_read(unsigned addr) {
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if(board.prgram.size == 0) {
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if((addr & 0xf000) == 0x6000) return cpu.mdr() | latch;
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return cpu.mdr();
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}
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return board.prgram.read(addr & 0x1fff);
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}
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void ram_write(unsigned addr, uint8 data) {
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if(board.prgram.size == 0) {
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if((addr & 0xf000) == 0x6000) latch = data & 0x01;
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return;
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}
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return board.prgram.write(addr & 0x1fff, data);
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}
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void reg_write(unsigned addr, uint8 data) {
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switch(addr) {
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case 0x8000: case 0x8001: case 0x8002: case 0x8003:
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prg_bank[0] = data & 0x1f;
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break;
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case 0x9000: case 0x9001: case 0x9002: case 0x9003:
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mirror = data & 0x03;
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break;
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case 0xa000: case 0xa001: case 0xa002: case 0xa003:
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prg_bank[1] = data & 0x1f;
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break;
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case 0xb000: chr_bank[0] = (chr_bank[0] & 0xf0) | ((data & 0x0f) << 0); break;
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case 0xb001: chr_bank[0] = (chr_bank[0] & 0x0f) | ((data & 0x0f) << 4); break;
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case 0xb002: chr_bank[1] = (chr_bank[1] & 0xf0) | ((data & 0x0f) << 0); break;
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case 0xb003: chr_bank[1] = (chr_bank[1] & 0x0f) | ((data & 0x0f) << 4); break;
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case 0xc000: chr_bank[2] = (chr_bank[2] & 0xf0) | ((data & 0x0f) << 0); break;
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case 0xc001: chr_bank[2] = (chr_bank[2] & 0x0f) | ((data & 0x0f) << 4); break;
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case 0xc002: chr_bank[3] = (chr_bank[3] & 0xf0) | ((data & 0x0f) << 0); break;
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case 0xc003: chr_bank[3] = (chr_bank[3] & 0x0f) | ((data & 0x0f) << 4); break;
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case 0xd000: chr_bank[4] = (chr_bank[4] & 0xf0) | ((data & 0x0f) << 0); break;
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case 0xd001: chr_bank[4] = (chr_bank[4] & 0x0f) | ((data & 0x0f) << 4); break;
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case 0xd002: chr_bank[5] = (chr_bank[5] & 0xf0) | ((data & 0x0f) << 0); break;
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case 0xd003: chr_bank[5] = (chr_bank[5] & 0x0f) | ((data & 0x0f) << 4); break;
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case 0xe000: chr_bank[6] = (chr_bank[6] & 0xf0) | ((data & 0x0f) << 0); break;
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case 0xe001: chr_bank[6] = (chr_bank[6] & 0x0f) | ((data & 0x0f) << 4); break;
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case 0xe002: chr_bank[7] = (chr_bank[7] & 0xf0) | ((data & 0x0f) << 0); break;
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case 0xe003: chr_bank[7] = (chr_bank[7] & 0x0f) | ((data & 0x0f) << 4); break;
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}
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}
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void power() {
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}
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void reset() {
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for(auto& n : prg_bank) n = 0;
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for(auto& n : chr_bank) n = 0;
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mirror = 0;
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latch = 0;
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}
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void serialize(serializer& s) {
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for(auto& n : prg_bank) s.integer(n);
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for(auto& n : chr_bank) s.integer(n);
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s.integer(mirror);
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s.integer(latch);
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}
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VRC2(Board& board) : Chip(board) {
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}
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};
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