mirror of https://github.com/bsnes-emu/bsnes.git
132 lines
3.3 KiB
C++
Executable File
132 lines
3.3 KiB
C++
Executable File
struct Decompressor;
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struct SPC7110 : Coprocessor {
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MappedRAM prom; //program ROM
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MappedRAM drom; //data ROM
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MappedRAM ram;
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static void Enter();
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void enter();
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void init();
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void load();
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void unload();
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void power();
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void reset();
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void add_clocks(unsigned clocks);
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uint8 read(unsigned addr);
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void write(unsigned addr, uint8 data);
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uint8 mcurom_read(unsigned addr);
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void mcurom_write(unsigned addr, uint8 data);
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uint8 mcuram_read(unsigned addr);
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void mcuram_write(unsigned addr, uint8 data);
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void serialize(serializer&);
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SPC7110();
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~SPC7110();
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//dcu.cpp
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void dcu_load_address();
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void dcu_begin_transfer();
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uint8 dcu_read();
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void deinterleave_1bpp(unsigned length);
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void deinterleave_2bpp(unsigned length);
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void deinterleave_4bpp(unsigned length);
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//data.cpp
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uint8 datarom_read(unsigned addr);
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unsigned data_offset();
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unsigned data_adjust();
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unsigned data_stride();
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void set_data_offset(unsigned addr);
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void set_data_adjust(unsigned addr);
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void data_port_read();
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void data_port_increment_4810();
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void data_port_increment_4814();
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void data_port_increment_4815();
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void data_port_increment_481a();
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//alu.cpp
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void alu_multiply();
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void alu_divide();
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private:
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//==================
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//decompression unit
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//==================
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uint8 r4801; //compression table B0
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uint8 r4802; //compression table B1
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uint7 r4803; //compression table B2
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uint8 r4804; //compression table index
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uint8 r4805; //adjust length B0
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uint8 r4806; //adjust length B1
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uint8 r4807; //stride length
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uint8 r4809; //compression counter B0
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uint8 r480a; //compression counter B1
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uint8 r480b; //decompression settings
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uint8 r480c; //decompression status
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bool dcu_pending;
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uint2 dcu_mode;
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uint23 dcu_addr;
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unsigned dcu_offset;
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uint8 dcu_tile[32];
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Decompressor *decompressor;
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//==============
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//data port unit
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//==============
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uint8 r4810; //data port read + seek
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uint8 r4811; //data offset B0
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uint8 r4812; //data offset B1
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uint7 r4813; //data offset B2
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uint8 r4814; //data adjust B0
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uint8 r4815; //data adjust B1
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uint8 r4816; //data stride B0
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uint8 r4817; //data stride B1
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uint8 r4818; //data port settings
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uint8 r481a; //data port seek
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//=====================
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//arithmetic logic unit
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//=====================
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uint8 r4820; //16-bit multiplicand B0, 32-bit dividend B0
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uint8 r4821; //16-bit multiplicand B1, 32-bit dividend B1
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uint8 r4822; //32-bit dividend B2
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uint8 r4823; //32-bit dividend B3
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uint8 r4824; //16-bit multiplier B0
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uint8 r4825; //16-bit multiplier B1
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uint8 r4826; //16-bit divisor B0
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uint8 r4827; //16-bit divisor B1
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uint8 r4828; //32-bit product B0, 32-bit quotient B0
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uint8 r4829; //32-bit product B1, 32-bit quotient B1
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uint8 r482a; //32-bit product B2, 32-bit quotient B2
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uint8 r482b; //32-bit product B3, 32-bit quotient B3
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uint8 r482c; //16-bit remainder B0
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uint8 r482d; //16-bit remainder B1
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uint8 r482e; //math settings
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uint8 r482f; //math status
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bool mul_pending;
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bool div_pending;
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//===================
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//memory control unit
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//===================
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uint8 r4830; //bank 0 mapping + SRAM write enable
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uint8 r4831; //bank 1 mapping
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uint8 r4832; //bank 2 mapping
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uint8 r4833; //bank 3 mapping
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uint8 r4834; //bank mapping settings
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};
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extern SPC7110 spc7110;
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