mirror of https://github.com/bsnes-emu/bsnes.git
95 lines
2.5 KiB
C++
95 lines
2.5 KiB
C++
auto GSU::instruction(uint8 opcode) -> void {
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#define op(id, name, ...) \
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case id: return op_##name(__VA_ARGS__); \
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#define op4(id, name) \
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case id+ 0: return op_##name((uint4)opcode); \
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case id+ 1: return op_##name((uint4)opcode); \
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case id+ 2: return op_##name((uint4)opcode); \
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case id+ 3: return op_##name((uint4)opcode); \
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#define op6(id, name) \
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op4(id, name) \
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case id+ 4: return op_##name((uint4)opcode); \
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case id+ 5: return op_##name((uint4)opcode); \
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#define op12(id, name) \
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op6(id, name) \
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case id+ 6: return op_##name((uint4)opcode); \
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case id+ 7: return op_##name((uint4)opcode); \
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case id+ 8: return op_##name((uint4)opcode); \
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case id+ 9: return op_##name((uint4)opcode); \
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case id+10: return op_##name((uint4)opcode); \
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case id+11: return op_##name((uint4)opcode); \
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#define op15(id, name) \
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op12(id, name) \
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case id+12: return op_##name((uint4)opcode); \
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case id+13: return op_##name((uint4)opcode); \
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case id+14: return op_##name((uint4)opcode); \
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#define op16(id, name) \
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op15(id, name) \
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case id+15: return op_##name((uint4)opcode); \
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switch(opcode) {
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op (0x00, stop)
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op (0x01, nop)
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op (0x02, cache)
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op (0x03, lsr)
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op (0x04, rol)
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op (0x05, branch, 1) //bra
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op (0x06, branch, (regs.sfr.s ^ regs.sfr.ov) == 0) //blt
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op (0x07, branch, (regs.sfr.s ^ regs.sfr.ov) == 1) //bge
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op (0x08, branch, regs.sfr.z == 0) //bne
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op (0x09, branch, regs.sfr.z == 1) //beq
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op (0x0a, branch, regs.sfr.s == 0) //bpl
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op (0x0b, branch, regs.sfr.s == 1) //bmi
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op (0x0c, branch, regs.sfr.cy == 0) //bcc
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op (0x0d, branch, regs.sfr.cy == 1) //bcs
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op (0x0e, branch, regs.sfr.ov == 0) //bvc
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op (0x0f, branch, regs.sfr.ov == 1) //bvs
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op16(0x10, to_move)
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op16(0x20, with)
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op12(0x30, store)
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op (0x3c, loop)
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op (0x3d, alt1)
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op (0x3e, alt2)
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op (0x3f, alt3)
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op12(0x40, load)
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op (0x4c, plot_rpix)
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op (0x4d, swap)
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op (0x4e, color_cmode)
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op (0x4f, not)
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op16(0x50, add_adc)
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op16(0x60, sub_sbc_cmp)
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op (0x70, merge)
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op15(0x71, and_bic)
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op16(0x80, mult_umult)
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op (0x90, sbk)
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op4 (0x91, link)
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op (0x95, sex)
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op (0x96, asr_div2)
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op (0x97, ror)
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op6 (0x98, jmp_ljmp)
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op (0x9e, lob)
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op (0x9f, fmult_lmult)
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op16(0xa0, ibt_lms_sms)
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op16(0xb0, from_moves)
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op (0xc0, hib)
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op15(0xc1, or_xor)
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op15(0xd0, inc)
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op15(0xe0, dec)
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op (0xdf, getc_ramb_romb)
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op (0xef, getb)
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op16(0xf0, iwt_lm_sm)
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}
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#undef op
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#undef op4
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#undef op6
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#undef op12
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#undef op15
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#undef op16
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}
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